Mlan-Nc1 (X2150A00) Mlan - Yamaha i88x Service Manual

i88X

mLAN-NC1 (X2150A00) mLAN

PIN
NAME I/O
NO.
1 VDD
2 TEST5 I
3 TEST4 I
4 TEST3 I
5 TEST2 I
6 TEST1 I
7 SCANE I
8 TRST I
9 TMS I
10 TCK I
11 VSS
12 TDO O
13 TDI I
14 SCL O
15 SDA I/O
16 ASYNCFLG I/O
17 ISOFLG I/O
18 BUSRST O
19 VDD
20 D7 I/O
21 D6 I/O
22 D5 I/O
23 D4 I/O
24 VSS
25 D3 I/O
26 D2 I/O
27 D1 I/O
28 D0 I/O
29 VDD
30 CTL1 I/O
31 CTL0 I/O
32 VSS
33 SCLK I
34 VDD
35 LREQ O
36 VSS
37 LPS O
38 DAI0 I
39 DAI1 I
40 DAI2 I
41 DAI3 I
42 BCKI I
43 WCKI I
44 DITI I
45 DIT MCI I
46 DIT BCI I
47 DIT WCI I
48 SLV I
49 SEQI I
50 VSS
51 ECKI I
52 EWCKI I
53 EWCKI2 I
54 ECKI2 I
55 SEQO O
56 ECKO O
57 EWCKO O
58 DAO0 O
59 VDD
60 DAO1 O
61 DAO2 O
62 DAO3 O
63 BCKO O
64 VSS
65 WCKO O
16
TM
FUNCTION
Power terminal
Test terminal
Test terminal
Test terminal
Test terminal
Test terminal
Test terminal
JTAG terminal
JTAG terminal
JTAG terminal
Ground terminal
JTAG terminal
JTAG terminal
EEPROM serial clock
EEPROM serial data
Asynchronous flag
Isochronous flag
Bus reset
Power terminal
PHY I/F data bus
PHY I/F data bus
PHY I/F data bus
PHY I/F data bus
Ground terminal
PHY I/F data bus
PHY I/F data bus
PHY I/F data bus
PHY I/F data bus
Power terminal
PHY-LINK control: Control signal for interface
with PHY chip
PHY-LINK control: Control signal for interface
with PHY chip
Ground terminal
Master clock
Power terminal
Link request
Ground terminal
Link power status
Digital audio input 0 /MIDI input 4
Digital audio input 1 /MIDI input 5
Digital audio input 2 /MIDI input 6
Digital audio input 3 /MIDI input 7
Bit clock input for digital audio input
Word clock input for digital audio input
Audio data input when using built-in DIT separately
Master clock input when using built-in DIT
separately (128Fs clock)
Bit clock input when using built-in DIT
separately (32Fs to 128Fs)
Word clock input when using built-in DIT
separately
Master: L, Slave : H when using a multiple
number of packet handler chips simultaneously,
fixed at Low when using mLAN-NC1 only
Loop connection input pin when using a multiple
number of packet handler chips simultaneously,
fixed at Low when using mLAN-NC1 only
Ground terminal
Bit clock input for audio signal receiving (128Fs cloc k)
Word clock input for audio signal receiving
Word clock input for PSC4 function
Bit clock input for PSC4 function (128Fs clock)
Loop connection output pin when using a
multiple number of packet handler chips
simultaneously
Bit clock output for audio signal receiving (128Fx)
Word clock output for audio signal receiving
Digital audio output 0/MIDI output 4
Power terminal
Digital audio output 1/MIDI output 5
Digital audio output 2/MIDI output 6
Digital audio output 3/MIDI output 7
Bit clock output for digital audio output (64Fs clock)
Ground terminal
Word clock output for digital audio output
Node Controller 1
PIN
NAME
NO.
66 MCKO
67 WCKOD
68 IEC958O
69 INT R SEL
70 SEL MCK1
71 SEL MCK0
72 SEL VCO1
73 SEL VCO0
74 AUX1
75 VDD
76 PCA
77 PCB
78 LOCKN1
79 VSS
80 VCO 01 CLK
81 VDD
82 PLL 01 Pump SK TRI Pump signal to sink current for PLL1
83 VSS
84 PLL 01 Pump SC TRI Pump signal to source current for PLL1
85 VDD
86 VCO 02 CLK
87 VSS
88 PLL 02 Pump SK TRI Pump signal to sink current for PLL2
89 VDD
90 PLL 02 Pump SC TRI Pump signal to source current for PLL2
91 VSS
92 MI0
93 MI1
94 MI2
95 MI3
96 VDD
97 MO0
98 MO1
99 MO2
100 MO3
101 VSS
102 DIR SCK
103 DIR SO
104 DIR SI I(PU) To SO of built-in DIR5
105 DIR CSN
106 DIR INT
107 DIR LOCKN
108 ERR BS
109 VDD
110 XTAL(OSC3)
111 XTAL(OSC4) O
112 VSS
113 DBL V
114 FS128 C
115 SYNC U
116 DIR SDI
117 VDD
118 WRH#
119 WAIT#
120 WRL#
121 PLLC
122 VSS
123 RD#
124 RESET#
125 BCLK
126 VSS
127 DMAEND0# I/O
128 DREQ# mLAN I/O
129 DACK# mLAN I/O
130 CS# mLAN/CE9# I/O
131 BUSGET# I/O
132 BUSACK# I/O
133 BUSREQ# I/O
134 VDD
I/O FUNCTION
O Master clock output for digital audio output
O Delay output of WCKO
O IEC60958 signal output from built-in DIT
I Selection of PLL division rate setting bit for SYT
I MCKO division rate setting bit 1
I MCKO division rate setting bit 0
I PLL division rate setting bit 1 for SYT
I PLL division rate setting bit 0 for SYT
I PLL external VCO clock input for SYT
Power terminal
O PLL external phase comparator output for SYT
O PLL external phase comparator output for SYT
O PLL lock flag output for SYT
Ground terminal
I External VCXO input for digital PLL1 (SYT)
Power terminal
Ground terminal
Power supply terminal
I External VCO input for digital PLL2 (SYT)
Ground terminal
Power terminal
Ground terminal
I MIDI input 0
I MIDI input 1
I MIDI input 2
I MIDI input 3
Power supply terminal
O MIDI output 0
O MIDI output 1
O MIDI output 2
O MIDI output 3
Ground terminal
O To SCK of built-in DIR5
O To SI of built-in DIR5
O To /CS of built-in DIR5
I To INT of built-in DIR5
I To /LOCK of built-in DIR5
I To ERR/BS of built-in DIR5
Power terminal
I MPU clock oscillation circuit terminal
MPU clock oscillation circuit output terminal
Ground terminal
I To DBL/V of built-in DIR5
I To FS128/C of built-in DIR5
I To SYNC/U of built-in DIR5
I To SDO of built-in DIR5
Power terminal
I/O Write enable high: host data bus write signal
I/O External bus wait signal
I/O Write enable low: host data bus write signal
I Capacitor connection terminal for MPU
oscillation PLL circuit
Ground terminal
I/O Read enable : host data bus read signal
I Hardware reset signal
O MPU bus clock output signal
Ground terminal
DMA END signal
In 8415 mode, data request output when
transferring DMA of Non-Audio RxFIFO#0 and in
standalone mode, MPU K50/DMAREQ0 signal
In 8415 mode, acknowledge input when
transferring DMA of Non-Audio RxFIFO#0 and in
standalone mode, MPU P32/DMADACK0 signal
In 8415 mode, chip select input of PH1 block
from microprocessor and in standalone mode,
MPUCE9 signal
MPU bus GET signal
MPU bus ACK signal
MPU bus REQ signal
Power terminal
MLN2: IC8