Sony DVW-A500P Maintenance Manual page 46

3-2. CIRCUIT BLOCK
[CIRCUIT DESCRIPTION OF VPR-1 BOARD] (Lot No. 341 or higher)
VPR-1 board is a video processor board that converts the
input video signal into digital data, converts the playback
digital data into a video signal, and generates timing
reference signals for video/audio processing.
The recording process is described below.
For the video input, a component video signal is the standard
analog signal, and a Serial V/A signal is the standard digital
signal.
An analog composite signal can also be input using the
optional "BKDW-505(NTSC)/506(PAL)" (DEC-65 board).
The component video signal is input to VPR-1 board, where
Y, R-Y, and B-Y signals are converted each from analog to
digital, passed through a digital filter, where converted into
10-bit parallel data, and sent to the TBC IC (IC307).
In this case, the R-Y and B-Y signals are multiplexed in the
digital filter and converted into chroma (C) data.
The Serial V/A signal is input to DIF-16 board and separated
into video data and audio data.
The video data is decoded and converted into 10-bit parallel
data ("D1 DATA 0 through 9"), then input to VPR-1 board and
sent to the TBC IC mentioned above.
If DEC-65 board (optional) is used, the input analog
composite video signal is decoded on DEC-65 board and
converted into 10-bit parallel data ("DEC DATA 0 through 9"),
then input to VPR-1 board and sent to the same TBC IC.
The TBC IC clamps the component video input signal,
selects a necessary data from these input data, transfers it to
the reference clock, multiplexes the Y data and C data, and
converts them into 10-bit parallel data.
It also generates various test signals under the control of the
MPU (IC753).
The 10-bit parallel data output from the TBC IC is added
VITC data in IC312, then sent to DPR-36 board as recording
video data ("REC DATA 0 through 9").
In case that a setup is added to the signal in NTSC system,
the data is removed the setup and corrected the level by
IC310(NTSC only) in the previous stage of IC312.
Next, the playback process is described below.
The decoded video PB data ("PB DATA 0 through 9") sent
from DPR-36 board is input to the video process IC (IC504).
The TBC-processed Betacam PB data ("B-CAM DATA 0
through 9") is also sent from TBC-23 board.
The "EE data 0 through 9" that is bypassed from the "REC
data" is also input. IC504 selects the input data according to
the system mode and sends it to encoder IC (IC505).
The encoder IC converts the input data into various 10-bit
parallel data (component Y, R-Y, and B-Y data, composite
data, VISC Y data, and D1/D2 data) and outputs them
together with the control data and clock signals required for
after data processing.
The component Y, R-Y, and B-Y data are converted each
from digital to analog so as to produce an analog signal, then
output via clamp circuits.
The composite data branches into two paths.
One is converted from digital to analog, clamped, output, and
divided on CP-218 board to produce "OUTPUT VIDEO 1 and
VPR-1
2" signals.
The another is converted from digital to analog,
superimposed a character signal by the switching of IC514,
and output as "OUTPUT VIDEO 3" signal.
The VISC Y data is converted from digital to analog, sent
through a low-pass filter to TBC-23 board, and used to adjust
the video phase of a Betacam PB signal.
The D1/D2 data is sent directly to DIF-16 board.
Lastly, the control system is described below.
Two systems (video process control circuit and timing
reference signal generator circuit) are provided for the
control system.
The video process control is performed by the MPU (IC753)
under the command ("SYIF2 CMD") of the serial
communication from the main CPU on SS-52 board.
The MPU sends control signals to each main IC on VPR-1
board, and controls each signal level and phase in A/D and
D/A conversion systems via EVRs (IC754 and IC755).
For the timing reference signal generation, the timing
generator IC (IC1019) controls a PLL circuit to generate a
27MHz reference clock signal according to the sync and
burst signals separated from an "INPUT REF VIDEO" signal.
The generated signal is sent to each board as the video
process timing reference signal.
Moreover, audio clock generator IC (IC1032), while
receiving this signal, generates various reference audio
clock signals synchronized with the reference video signal
and sends them to each board as the audio process timing
reference signal.
3-6
VPR-1
[CIRCUIT DESCRIPTION OF VPR-1 BOARD] (Lot No. 302 through 334)
VPR-1 board is a video processor board that converts the
input video signal into digital data, converts the playback
digital data into a video signal, and generates timing
reference signals for video/audio processing.
The recording process is described below.
For the video input, a component video signal is the standard
analog signal, and a Serial V/A signal is the standard digital
signal.
An analog composite signal can also be input using the
optional "BKDW-505(NTSC)/506(PAL)" (DEC-65 board).
The component video signal is input to VPR-1 board, where
Y, R-Y, and B-Y signals are converted each from analog to
digital, passed through a digital filter, where converted into
10-bit parallel data, and sent to the TBC IC (IC307).
In this case, the R-Y and B-Y signals are multiplexed in the
digital filter and converted into chroma (C) data.
The Serial V/A signal is input to DIF-16 board and separated
into video data and audio data.
The video data is decoded and converted into 10-bit parallel
data ("D1 DATA 0 through 9"), then input to VPR-1 board and
sent to the TBC IC mentioned above.
If DEC-65 board (optional) is used, the input analog
composite video signal is decoded on DEC-65 board and
converted into 10-bit parallel data ("DEC DATA 0 through 9"),
then input to VPR-1 board and sent to the same TBC IC.
The TBC IC clamps the component video input signal,
selects a necessary data from these input data, transfers it to
the reference clock, multiplexes the Y data and C data, and
converts them into 10-bit parallel data.
It also generates various test signals under the control of the
MPU (IC753), receives the "REC DATA", "PB DATA", and
"D1/D2 DATA" (encoder outputs) that are fed back as
"multiloops", and executes the diagnosis.
The 10-bit parallel data output from the TBC IC is added
VITC data in IC312, then sent to DPR-36 board as recording
video data ("REC DATA 0 through 9").
In case that a setup is added to the signal in NTSC system,
the data is removed the setup and corrected the level by
IC310(NTSC only) in the previous stage of IC312.
Next, the playback process is described below.
The decoded video PB data ("PB DATA 0 through 9") sent
from DPR-36 board is input to the video process IC (IC504).
The TBC-processed Betacam PB data ("B-CAM DATA 0
through 9") is also sent from TBC-23 board.
The "EE data 0 through 9" that is bypassed from the "REC
data" is also input. IC504 selects the input data according to
the system mode and sends it to encoder IC (IC505).
The encoder IC converts the input data into various 10-bit
parallel data (component Y, R-Y, and B-Y data, composite
data, VISC Y data, and D1/D2 data) and outputs them
together with the control data and clock signals required for
after data processing.
The component Y, R-Y, and B-Y data are converted each
from digital to analog so as to produce an analog signal, then
output via clamp circuits.
The composite data branches into two paths.
3-6
One is converted from digital to analog, clamped, output, and
divided on CP-218 board to produce "OUTPUT VIDEO 1 and
2" signals.
The another is converted from digital to analog,
superimposed a character signal by the switching of IC514,
and output as "OUTPUT VIDEO 3" signal.
The VISC Y data is converted from digital to analog, sent
through a low-pass filter to TBC-23 board, and used to adjust
the video phase of a Betacam PB signal.
The D1/D2 data is sent directly to DIF-16 board.
Lastly, the control system is described below.
Two systems (video process control circuit and timing
reference signal generator circuit) are provided for the
control system.
The video process control is performed by the MPU (IC753)
under the command ("SYIF2 CMD") of the serial
communication from the main CPU on SS-52 board.
The MPU sends control signals to each main IC on VPR-1
board, and controls each signal level and phase in A/D and
D/A conversion systems via EVRs (IC754 and IC755).
For the timing reference signal generation, the timing
generator IC (IC1019) controls a PLL circuit to generate a
27MHz reference clock signal according to the sync and
burst signals separated from an "INPUT REF VIDEO" signal.
The generated signal is sent to each board as the video
process timing reference signal.
Moreover, audio clock generator IC (IC1032), while
receiving this signal, generates various reference audio
clock signals synchronized with the reference video signal
and sends them to each board as the audio process timing
reference signal.
DVW-A500P/500P