JVC GR-D370UC Schematic Diagrams page 8

MAIN(PARAGON) SCHEMATIC DIAGRAM
0 1 MAIN(PARAGON)
HDIN
TO CDS/TG HDIN
VDIN
TO MAIN IF(CN104),
VDIN
CDS/TG CLKI
CLKI
ADIN9
ADIN9
ADIN8
ADIN8
ADIN7
ADIN7
ADIN6
ADIN6
ADIN5
TO CDS/TG ADIN5
ADIN4
ADIN4
ADIN3
ADIN3
ADIN2
ADIN2
ADIN1
ADIN1
ADIN0
ADIN0
PAL
NTSC
R3078
R3075
OPEN
TVSEL SW 0Ω
CLK27B
DSYO0
DSYO0
DSYO1
DSYO1
DSYO2
DSYO2
DSYO3
DSYO3
DSYO4
DSYO4
DSYO5
DSYO5
DSYO6
DSYO6
DSYO7
DSYO7
TL3006
DSCO0
DSCO0 TL3005
DSCO1 TL3004
DSCO1 TL3003
DSCO2 TL3002
DSCO2 C3064
DSCO3
DSCO3
DSCO4
DSCO4
DSYO0
DSCO5 DSYO1
DSCO5
DSYO2
DSCO6 DSYO3
DSCO6
DSYO4
DSCO7
DSYO5
DSCO7
DSYO6
DSYIO0
DSYO7
DSYIO0
TO DSC DSYIO1
DSYIO1
DSYIO2
DSCO0
DSYIO2
DSCO1
DSYIO3
DSCO2
DSYIO3
DSCO3
DSYIO4
DSCO4
DSYIO4
DSCO5
DSYIO5 DSCO6
DSYIO5 DSCO7
DSYIO6
DSYIO6
DSYIO7
DSYIO7
DSYIO0
DSCIO0
DSYIO1
DSCIO0
DSYIO2
DSCIO1
DSYIO3
DSCIO1
DSYIO4
DSCIO2
DSYIO5
DSCIO2
DSYIO6
DSCIO3
DSYIO7
DSCIO3
DSCIO4
DSCIO4
DSCIO0
DSCIO5 DSCIO1
DSCIO5 DSCIO2
DSCIO6
DSCIO3
DSCIO6
DSCIO4
DSCIO7
DSCIO5
DSCIO7
DSCIO6
HDDSC
DSCIO7
HDDSC
HDDSC
VDDSC
VDDSC
VDDSC
FLDDSC
FLDDSC
CLKDSC
FLDDSC
CLKDSC
CLKDSC
R3037 56 _0.5%
CH
TPB-
R3036 56 _0.5%
TPB+
TO JACK
R3035 56 _0.5% R3038 5.1k
TPA-
R3034 56 _0.5%
TPA+
TL3012
GND
DAC_RST
TO CPU
DAC_CS
VOI_CLK
TO CPU,VIDEO
VOI_OUT
16 15 14 13 12 11 10 9
IC3004
BH2226FV-X
L3013
10µ
1 2 3 4 5 6 7 8
REC_ADJ
TO PRE/REC
ATF_GAIN C3078
1
TO VIDEO ASPECT
H_GAIN
H_OFFSET
TO OP DRV
VD_F/Z
VD_F/Z
F/Z_MCK
F/Z_MCK
NOTES: 1. For the destination of each signal and further line connections that are cut off from this diagram, refer to "BOARD INTERCONNECTIONS".
2. The parts with marked ( ) is not used.
313
VSS
230
ADD_VDDL
145
VSS
311 OJSEL
312 CCDSEL
234 TVSEL
314
PLLSEL
235 CLK27SEL
318 CPUBUSTYPE
236 VCC
2 VPD
20 PBI
TL3007
R3096 10k 148 PWR1
R3097 10k 316 PWR2
R3098 10k 53 PWR3
149 TTST
55 TBST
C3065 315 FRRES
0.01 237 VCC
54 ADD_VDDL
150 ADD_VSS
238 VCC
317 MTEST
56 TCK
239 TMS
152 TRST
240 TDI
57 TDO
153 VCC
320 ADD_VSS
0.1 319 ADD_VDDE
151 CLK24O
154 VCC
58 DSYO0
241 DSYO1
59 DSYO2
242 DSYO3
155 DSYO4
60 DSYO5
321 DSYO6
322 DSYO7
243 VCC
C3062 IC3001
156 ADD_VSS
0.01
61 ADD_VDDE
244 DSCO0
C3063 157 DSCO1
0.01 324 DSCO2
JCY0205-3
323 DSCO3
62 DSCO4
245 DSCO5
158 DSCO6
63 DSCO7
64 ADD_VDDL
159 ADD_VSS
246 ADD_VDDE
65 DSYIO0
325 DSYIO1
328 DSYIO2
160 DSYIO3
247 DSYIO4
66 DSYIO5
161 DSYIO6
248 DSYIO7
327 ADD_VSS
67 ADD_VDDE
326 DSCIO0
162 DSCIO1
249 DSCIO2
68 DSCIO3
163 DSCIO4
250 DSCIO5
69 DSCIO6
329 DSCIO7
R3081 10 171 HDDSC
R3082 10 335 VDDSC
R3083 10 257 FLDDSC
R3084 10 78 CLKDSC
332 ADD_VDDE
164 ADD_VSS
252 ADD_VDDL
251 PHYAVS2
165 PHYAVD2
OPEN
C3061 R3040 70 PHYTPB
2.4k 71 PHYXTPB
166 PHYRO
330 PHYAVD3
253 PHYAVS3
331 PHYTPBIAS
C3059
C3060
1
270p
_0.5%
TL3019
215
ADD_VDDE
297
ADD_VSS
24
VCC
224
INVA
37
INHA
125
ACI3
214
ACI2 123
ACI1
295
ACI0
122
AYI3
121
AYI2
23 C3020
AYI1
22 0.01
AYI0
212
VCC
294
ADD_VDDE
210
ADD_VSS
21
ADD_VDDL
116
KO
120
VCC
292
ADD_VDDE
19
ADD_VSS C3022
118 0.01
ADD_VDDE
209
VCC
208
AODAT0 290
AIDAT/AIDAT2
AIDAT0
119
AILRCK
207
AIBCK
205
AIMCK
17
VDDI
213 R3005
PWMAUDIO
117
VCC
211
OSC11O
293
OSC11I
291
ADD_VSS
115
ADD_VDDL
16
VCXO11O
18
VCXO11I
15
VCC 114
ADD_VSS 289
VCXO12O
14
VCXO12I
288 C3025
ADD_VDDE
287 0.01
ADD_VSS
206
OSC24O
13
OSC24I
204
VDDE
113
VSS
12 C3032
VDDI
112 0.01
NC
203
PLLAVS6
286
PLLAVD6
11 C3033 1
VCIAUD
285
PLLAVS5 111
PLLAVD5 10
VCI4185
110
PLLAVS4
202
PLLAVD4
284
LPF24OUT
9
LPF24IN
201 R3011
PLLAVS3
283 C3035 3.3k
PLLAVD3
200 0.01
PLLAVS2
109
PLLAVD2
108
LPF41OUT
8
LPF41IN
199
PLLAVS1 R3013
281 C3036
PLLAVD1 3.3k
7 R3056 68k OPEN
DAVRO1
107
DAVREF1 C3071 0.1
282
DAAVS1 198
DAAVD1 106 C3021 0.01
DAAOUT1
6 R3057 68k
DAVRO0
197
DAVREF0
279
DAAVS0
105
DAAVD0
5 C3072
DAAOUT0
195 0.1
ADVRL0
280
ADVRH0
196
ADAVS0
104
ADAVD0 C3048
4 OPEN
ADVIN0
277
ADVRH1
278
ADVRL1 103
ADAVS1
194 C3073
ADAVD1 3
0.1
ADVIN1
102
NC
R3094 56k 3
R3095 56k
2
1
D3005
DAN222-X
CPUWAITLOGIC D3004
R3090 0 EC2C01C-TR-X
L3012
C3053
2.7µ R3104
R3029
1000p 18k R3103
220k
C3051 100k
82p
3 1
5 2
Q3003
C3080
R3030 HN1B01FU/G/-X
0.1
10k
4 6
R3105
10k
R3031
C3052
OPEN
0.1
(No.YF124)2-13 2-14(No.YF124)
L3001
NQR0602-001X
C3002
1
L3002
C3004
OPEN
OPEN
L3003
NQR0602-001X
C3006
1
L3004
NQR0602-001X
C3008
1
L3005
NQR0602-001X
C3010
1
L3007
NQR0602-001X
R3001
2.2k C3014
1
Q3001
2SC4617/QR/-X
R3002
C3018 C3016
2.2k
0.1 0.01
L3009
NQR0602-001X
R3106
1k C3017
1
R3004
1k
AODAT
AILRCK
D3002
AIBCK
1SV303-X
AIMCK R3006 2.2k
10k
R3010
C3029 OPEN
R3101
1000p R3100
R3008 39k
100k
L3010 220k
10µ
C3031 3 1
OPEN
5 2 C3079
0.1
C3026
0.1 C3030 4 6
100p
R3102
D3003
10k
OPEN
Q3002
HN1B01FU/G/-X
C3037
0.33
R3012 820
C3038 OPEN
R3014 820 C3039
0.01
C3040 220p
VREF_1.1
VRB_AGC
AGC_OUT
VRB_ATF
ATFI
R3026
1k
TL3017
GND
TO REG
REG_12V
REG_1.7V TO VIDEO,REG
TO PRE/REC,REG
REG_2.5V
REG_3.1V
REG_4.8V
TO MAIN IF(CN104),
OUTV
CPU,VIDEO
OUTV
OUTH
OUTH
DYO3
DYO3
DYO2
DYO2
DYO1
D3001 DYO1
RB551V-30-X DYO0
DYO0
DCO3 TO VIDEO
DCO3
DCO2
DCO2
DCO1
DCO1
DCO0
DCO0
CLK27A
CLK27A
OSD_VD
OSD_VD TO CPU,VIDEO
S_SHUT
AODAT
AODAT
AIDAT/AIDAT2
AIDAT/AIDAT2
TO AUDIO
AIMCK
AIMCK
AIBCK
AIBCK
AILRCK
AILRCK
AGC_OUT
AGC_OUT
TO PRE/REC
VRB_AGC
VRB_AGC
ATFI
ATFI TO MAIN IF(CN102),
VRB_ATF
PRE/REC
VRB_ATF
VREF_1.1
VREF_1.1
REC_DATA
REC_DATA
TO REG
REC_CLK
REC_CLK
REC_CTL
REC_CTL
REF_CLK
REF_CLK
FS_PLL
TO MAIN IF(CN102)
MAIN_VCO
TL3016
SBE
SPA
TO CPU
DSP_RST
DSP_RST
XINT
XINT
HID
TO MAIN IF(CN102).CPU
HID
SPA
TO CPU
SPA
TSR
TSR
FRP
FRP
OMT TO MAIN IF(CN104),CPU
OMT
MFLD
MFLD
MVD
MVD TO MAIN IF(CN102),CPU
CDAS
CDAS
DSP_CS
DSP_CS
CDRE
CDRE
CDWE
CDWE
CPU_WAIT
CPU_WAIT
ADDT15
ADDT15
ADDT14
ADDT14
ADDT13
ADDT13
ADDT12
ADDT12
ADDT11
ADDT11
ADDT10
TO CPU
ADDT10
ADDT09
ADDT09
ADDT08
ADDT08
ADDT07
ADDT07
ADDT06
ADDT06
ADDT05
ADDT05
ADDT04
ADDT04
ADDT03
ADDT03
ADDT02
ADDT02
ADDT01
ADDT01
ADDT00
ADDT00 TO MAIN IF(CN104),
OUTV CPU,VIDEO
CLK27SEL TO CPU
yf124_y10600001a_rev1.1