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All and
more about Sharp
PC-1
500 at http:f/www.PC-1500.info
0
D
D
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B D
B B
4
3
2
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T
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R_C
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PEOUT 11
0
145696
Vee.
'loo
Vss
•
CLOCK
circuit
(SW
2)
V
ss
150K
cl--~~~~-<.,:-7=~~'-..>-~
C
F
CTLA
CTLe
154KHt
According to
commands
from the
CPU,
the
frequency
dividing ratio is
changed
to
make
a clock
pulse
corresponding to
respective
baud
rates.
In
init
ial
setting,
after
turning the power
switch
on,
the
baud
rat
e of
300 is automatically
provided.
Thus
a
specified
baud rate
can
be
obtained
with
ch•nge command
from the
CPU. The
commands
3rC
delivered
to LH581 l
ports PCO
thru
PC4,
PA6
or PA7.
(T/
R
clock
=
baud r3tc
X 16)
• CDP1854ACE
CH IP S ELECT
The
conditions
to
select this
chip
are
that
CSI and
CS3
arc at
HIGH
posi1 ion and that CS2 is
at
LOW
position.
The
circuit
is
a
s
shown below
.
A015(1
)
j d
)
A0
14(1)- - -
--l
-
·>---
-
CS2
-----
A012(1)
CS3
.--•
)
CS
1
A09 (1
1108
AD
I
RO/WR
A015(t
A014 (1
~
)
·
:
~
I
)
)
\
.
110 13
(0
11
0
12(1
A011 (0
11010(0
1109
(1
ME
l (1
_J
r -
40H 138P
Y1
h
o,.
er;;
G
1
c
B
A
Of-
0
of-
YI •
G1 •
Do not sale
this PDF
!!!
0200
................
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0
201
................
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7
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