Pioneer MD-P100 Service Manual page 32

MD-P100
- Pin Functions(CXD2535CR-1)
Pin No. Pin Name
1 FS256
2 FOK
3 DFCT
4 SHCK
5 SHCKEN
6 WRPWR
7 DIRC
8 SWDT
9 SCLK
10 XLAT
11 SRDT
12 SENS
13 ADSY
14 SQSY
15 DQSY
xrst
16
17 TEST4
18 CLVSCK
19 TEST5
20 DOUT
21 DIN
22 FMCK
ater
23
24 REC
25 DVSS
26 DOVF
27 DODT
28 DIDT
29 DTI
30 DTO
31 C2PO
32 BCK
33 LRCK
34 XTAO
35 XTAI
36 MCLK
37 XBCK
38 DVDDO
39 WDCK
40 RFCK
41 WFCK
42 GTOP
gfs
43
44 XPLCK
32
I/O Function and Operation
O 11.2896MHz clock signal output (MCLK system) Not used this set (OPEN)
O Focus OK signal output to the system controller (IC600)
"H" is output when the focus is applied
O Defect ON/OFF selection signal output to CXD2536CR (IC500)
O Track jump detection signal output to the system controller
Not used this set (OPEN)
I Track jump detection enable input Not used this set (Fixed at "L")
I Laser power selection signal input from the system controller
Not used this set (Fixed at "L")
I Not used this set (Fixed at "H")
I Write data signal input from the system controller (IC600)
I Serial clock signal input from the system controller (IC600)
I Serial latch signal input from the system controller (IC600)
O Read data signal output to the system controller (IC600)
O Internal status (SENS) output to the system controller (IC600)
O ADIP sync signal output Not used this set (OPEN)
O Sub-code Q sync (SCOR) output to the system controller (IC600)
"L" every 13.3msec,Almost "H"
O Digital in U-bit CD format sub-code Q sync (SCOR) output to the system con-
troller (IC600) "L" every 13.3msec,Almost "H"
I Reset signal input from the system controller (IC600) When reset "L"
I Test input terminal (Fixed at "L")
O Not used this set (OPEN)
I Test input terminal (Fixed at "L")
O Output terminal of the digital audio signal (for optical out)
Not used this set (OPEN)
I Input terminal of the digital audio signal (for optical out)
Not used this set (Fixed at "L")
O FM modulation clock signal output of the ADIP Not used this set (OPEN)
O ADIP CRC flag output When error "H" Not used this set (OPEN)
I Record/playback selection signal input
When recording :"H", when playback:"L" (Fixed at "L")
Ground terminal (Digital system)
I Validity flag input terminal for the digital audio out
Not used this set (Fixed at "L")
I Input terminal of 16-bit data signal for the digital audio out
Not used this set (Fixed at "L")
O Output terminal of 16-bit data signal for the digital audio in
Not used this set (OPEN)
I Record audio data signal input from CXD2536CR (IC500)
O Playback audio data signal output to CXD2536CR (IC500)
O C2PO (indicate the error state of the data) signal output to CXD2536AR (IC500)
Playback:C2PO ("H"), Digital recording:D.In-Vflag,Analog recording:"L"
O Bit clock (2.8224MHz) signal output to CXD2536CR (IC500) (MCLK system)
O L/R clock (44.1kHz) signal output to CXD2536CR (IC500) (MCLK system)
O System clock (512Fs=22.5792MHz) signal output Not used this set (OPEN)
I System clock (512Fs=22.5792MHz) signal input from CXD2536CR (IC500)
O MCLK clock (22.5792MHz) signal output Not used this set (OPEN)
O BCK (pin 32)inverted output Not used this set (OPEN)
Power supply terminal (+3.3V) (Digital system)
O WDCK clock (88.2kHz) signal output (MCLK system) Not used this set (OPEN)
O RFCK clock (7.35kHz) signal output (MCLK system) Not used this set (OPEN)
O WFCK clock (7.35kHz) signal output (When playback:EFM decoder PLL system,
When recoding:EFM encoder PLL system) Not used this set (OPEN)
O Opens the playback EFM frame sync protection window when "H"
Not used set (OPEN)
O The playback EFM frame sync and interpolation protection timing match
when "H" Not used this set (OPEN)
O EFM decoder PLL clock (98Fs=4.3218MHz) signal output Falling edge of the
EFM PLL clock and the EFM signal match Not used this set (OPEN)