Epson S1C17F13 Manuals

Manuals and User Guides for Epson S1C17F13. We have 1 Epson S1C17F13 manual available for free PDF download: Technical Manual

Epson S1C17F13 Technical Manual (247 pages)

CMOS 16-BIT SINGLE CHIP MICROCONTROLLER

Brand: Epson | Category: Microcontrollers | Size: 8.87 MB

Configuration of Product Number
3
Preface
4
Notational Conventions and Symbols in this Manual
4
Table of Contents
5
1 Overview

14
- Features
  14
- Block Diagram
  16
- Pins
  17
2 Power Supply, Reset, and Clocks

22
- Power Generator (PWG)
  22
  - Overview
    22
  - Pins
    23
  - D1 Regulator
    23
  - VOSC Regulator
    23
  - Flash Programming Power Supply (V )
    23
- System Reset Controller (SRC)
  23
  - Overview
    23
  - Input Pin
    24
  - Reset Sources
    24
  - Initialization Conditions (Reset Groups)
    25
- Clock Generator (CLG)
  26
  - Overview
    26
  - Input/Output Pins
    27
  - Clock Sources
    27
  - Operations
    29
- Operating Mode
  32
  - Initial Boot Sequence
    32
  - Transition between Operating Modes
    32
- Interrupts
  33
- Control Registers
  34
3 CPU and Debugger

40
- Overview
  40
- CPU Core
  41
  - CPU Registers
    41
  - Instruction Set
    41
  - Reading PSR
    41
  - I/O Area Reserved for the S1C17 Core
    41
- Debugger
  41
- Control Register
  42
  - MISC PSR Register
    42
  - Debug RAM Base Register
    43
4 Memory and Bus

44
- Overview
  44
- Bus Access Cycle
  44
- Flash Memory
  45
  - Flash Bus Access Cycle Setting
    45
  - Flash Programming
    45
  - Flash Security Function
    46
- Ram1
  46
- Ram2
  46
- Peripheral Circuit Control Registers
  46
- Control Registers
  50
5 Interrupt Controller (ITC)

52
- Overview
  52
- Vector Table
  52
  - Vector Table Base Address (TTBR)
    54
- Initialization
  54
- Maskable Interrupt Control and Operations
  54
- Nmi
  55
- Software Interrupts
  55
- Interrupt Processing by the CPU
  56
- Control Registers
  56
6 O Ports (PPORT)

58
- Overview
  58
- I/O Cell Structure and Functions
  59
- Clock Settings
  60
  - PPORT Operating Clock
    60
  - Clock Supply in SLEEP Mode
    60
  - Clock Supply in DEBUG Mode
    60
- Operations
  60
  - Initialization
    60
  - Port Input/Output Control
    62
- Interrupts
  63
- Control Registers
  63
- Control Register and Port Function Configuration of this IC
  68
  - P0 Port Group
    68
  - P1 Port Group
    69
  - P2 Port Group
    69
  - P3 Port Group
    70
  - P4 Port Group
    71
  - Pd Port Group
    72
  - Common Registers between Port Groups
    72
7 Watchdog Timer (WDT)

73
- Overview
  73
- Clock Settings
  73
  - WDT Operating Clock
    73
  - Clock Supply in DEBUG Mode
    74
- Operations
  74
  - WDT Control
    74
  - Operations in HALT and SLEEP Modes
    74
- Control Registers
  75
  - WDT Clock Control Register
    75
  - WDT Control Register
    75
8 Supply Voltage Detector (SVD)

77
- Overview
  77
- Input Pin and External Connection
  78
  - Input Pin
    78
  - External Connection
    78
- Clock Settings
  78
  - SVD Operating Clock
    78
  - Clock Supply in SLEEP Mode
    78
  - Clock Supply in DEBUG Mode
    79
- Operations
  79
  - SVD Control
    79
  - SVD Operations
    80
- SVD Interrupt and Reset
  80
  - SVD Interrupt
    80
  - SVD Reset
    81
- Control Registers
  81
16-Bit Timers (T16)

85
- Overview
  85
- Input Pin
  85
- Clock Settings
  86
  - T16 Operating Clock
    86
  - Clock Supply in SLEEP Mode
    86
  - Clock Supply in DEBUG Mode
    86
  - Event Counter Clock
    86
- Operations
  86
  - Initialization
    86
  - Counter Underflow
    87
  - Operations in Repeat Mode
    87
  - Operations in One-Shot Mode
    87
  - Counter Value Read
    88
- Interrupt
  88
- Control Registers
  88
10 Uart (Uart)

92
- Overview
  92
11 Synchronous Serial Interface (SPI)

93
- Input/Output Pins and External Connections
  93
- Clock Settings
  93
  - UART Operating Clock
    93
  - Clock Supply in SLEEP Mode
    93
  - Clock Supply in DEBUG Mode
    94
  - Baud Rate Generator
    94
- Data Format
  94
- Operations
  95
  - Initialization
    95
  - Data Transmission
    95
  - Data Reception
    96
  - Irda Interface
    97
- Receive Errors
  98
  - Framing Error
    98
  - Parity Error
    99
  - Overrun Error
    99
- Interrupts
  99
- Control Registers
  99
  - UART Ch.n Clock Control Register
    99
  - UART Ch.n Mode Register
    100
  - UART Ch.n Baud-Rate Register
    101
- Input/Output Pins and External Connections
  106
- Data Format
  109
  - Data Transmission in Master Mode
    109
  - Data Reception in Master Mode
    111
  - Terminating Data Transfer in Master Mode
    112
  - Data Transfer in Slave Mode
    112
  - Terminating Data Transfer in Slave Mode
    114
    
    SPI Ch.n Mode Register
    115
    
    SPI Ch.n Control Register
    115
    
    SPI Ch.n Transmit Data Register
    116
    
    SPI Ch.n Receive Data Register
    116
    
    SPI Ch.n Interrupt Flag Register
    116
    
    SPI Ch.n Interrupt Enable Register
    117
100 C (I2C)

118
- Overview
  118
- Input/Output Pins and External Connections
  119
  - List of Input/Output Pins
    119
  - External Connections
    119
- Clock Settings
  120
  - I2C Operating Clock
    120
  - Clock Supply in DEBUG Mode
    120
  - Baud Rate Generator
    120
- Operations
  121
  - Initialization
    121
  - Data Transmission in Master Mode
    122
  - Data Reception in Master Mode
    124
  - 10-Bit Addressing in Master Mode
    126
  - Data Transmission in Slave Mode
    127
  - Data Reception in Slave Mode
    129
  - Slave Operations in 10-Bit Address Mode
    131
  - Error Detection
    132
  - Interrupts
    133
- Control Registers
  134
  - I2C Ch.n Clock Control Register
    134
  - I2C Ch.n Mode Register
    135
  - I2C Ch.n Baud-Rate Register
    135
  - I2C Ch.n Own Address Register
    135
  - I2C Ch.n Control Register
    136
  - I2C Ch.n Transmit Data Register
    137
  - I2C Ch.n Receive Data Register
    137
  - I2C Ch.n Status and Interrupt Flag Register
    137
  - I2C Ch.n Interrupt Enable Register
    138
13 Clock Timer (CT)

140
- Overview
  140
- Clock Settings
  140
- Operations
  140
- Interrupts
  141
- Control Registers
  142
  - CT Control Register
    142
  - CT Counter Data Register
    142
  - CT Interrupt Flag Register
    143
  - CT Interrupt Enable Register
    143
14 Real-Time Clock (RTC)

144
- Overview
  144
- Clock Settings
  144
- RTC Counters
  144
- Operations
  146
  - Time Setting
    146
  - Time Read
    147
- Interrupts
  147
- Control Registers
  148
  - RTC Control Register
    148
  - RTC Interrupt Enable Register
    149
  - RTC Interrupt Flag Register
    149
  - RTC Minute/Second Register
    150
  - RTC Hour Register
    150
15 Theoretical Regulation (TR)

152
- Overview
  152
- Output Pin
  152
- Operations
  152
  - Executing Theoretical Regulation
    152
  - Regulated Clock External Monitor
    154
- Control Register
  154
  - Theoretical Regulation Control Register
    154
16-Bit PWM Timers (T16A3)

156
- Overview
  156
- Input/Output Pins
  157
- Clock Settings
  157
  - T16A3 Operating Clock
    157
  - Clock Supply in SLEEP Mode
    158
  - Event Counter Clock
    158
  - Counter Block Operations
    159
  - Comparator/Capture Block Operations
    160
  - TOUT Output Control
    164
- Interrupt
  166
- Parallel Interface (PIO) Characteristics
  173
  - External Connections
    174
  - Operations in SRAM Mode
    175
  - Operations in GPIO Mode
    176
    
    Control Registers
    177
    
    PIO Control Register
    178
    
    PIO Status Register
    179
18 EPD Timing Controller (EPD Tcon)

180
- Control Registers
  181
19 R/F Converter (RFC)

182
- Input/Output Pins and External Connections
  183
- Clock Settings
  184
- Temperature Detection Circuit (TEM)
  193
  - Temperature Detection
    195
  - Interrupt
    197
    
    TEM Control Register
    198
    
    TEM Interrupt Enable Register
    199
21 Multiplier/Divider (COPRO)

200
- Multiplication
  201
- Division
  202
- Reading Operation Results
  205
22 Electrical Characteristics

206
23 Basic External Connection Diagram

219
24 Package

219
Appendix A List of Peripheral Circuit Control Registers

220
- 0X4000-0X4008
  220
- Misc Registers (MISC)
  220
  - 0X4020
    220
- Power Generator (PWG)
  220
  - 0X4040-0X404E
    220
- Clock Generator (CLG)
  220
  - 0X4052
    221
  - 0X4080-0X4092
    221
  - 0X40A0-0X40A2
    222
- Watchdog Timer (WDT)
  222
  - 0X40C0-0X40C8
    223
  - 0X4100-0X4106
    223
- Supply Voltage Detector (SVD)
  223
  - 0X4160-0X416C
    224
  - 0X41B0
    224
- Flash Controller (FLASHC)
  224
  - 0X4200-0X42E2
    224
- I/O Ports (PPORT)
  224
  - 0X4380-0X438E
    227
- Uart (Uart)
  227
  - 0X43A0-0X43Ac
    228
  - 0X43B0-0X43Ba
    229
  - 0X43C0-0X43D2
    229
- I 2 C (I2C)
  229
  - 0X5000-0X500E
    230
  - 0X5020-0X502E
    231
  - 0X5180-0X5186
    232
  - 0X5260-0X526C
    233
  - 0X5270-0X527A
    233
  - 0X5280-0X528C
    234
  - 0X5290-0X529A
    234
  - 0X52E0-0X52Ea
    235
  - 0X5380-0X5384
    235
  - 0X5440-0X5450
    236
  - 0X5460-0X5470
    237
  - 0X54C0-0X54Ca
    238
  - 0Xffff90
    238
- Debugger (DBG)
  238
Appendix B Power Saving

239
- Operating Status Configuration Examples for Power Saving
  239
- Other Power Saving Methods
  240
Appendix C Mounting Precautions

242
Appendix D Measures against Noise

243
Appendix E Initialization Routine

245
Revision History

246

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Epson S1C17F13 Technical Manual (247 pages)

Table of Contents

1 Overview

2 Power Supply, Reset, and Clocks

3 CPU and Debugger

4 Memory and Bus

5 Interrupt Controller (ITC)

6 O Ports (PPORT)

7 Watchdog Timer (WDT)

8 Supply Voltage Detector (SVD)

16-Bit Timers (T16)

10 Uart (Uart)

11 Synchronous Serial Interface (SPI)

100 C (I2C)

13 Clock Timer (CT)

14 Real-Time Clock (RTC)

15 Theoretical Regulation (TR)

16-Bit PWM Timers (T16A3)

18 EPD Timing Controller (EPD Tcon)

19 R/F Converter (RFC)

21 Multiplier/Divider (COPRO)

22 Electrical Characteristics

23 Basic External Connection Diagram

24 Package

Appendix A List of Peripheral Circuit Control Registers

Appendix B Power Saving

Appendix C Mounting Precautions

Appendix D Measures against Noise

Appendix E Initialization Routine

Revision History

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