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F2MC-8L MB89623
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Fujitsu F2MC-8L MB89623 manual available for free PDF download: Hardware Manual
Fujitsu F2MC-8L MB89623 Hardware Manual (354 pages)
8-BIT MICROCONTROLLER
Brand:
Fujitsu
| Category:
Microcontrollers
| Size: 2.24 MB
Table of Contents
Figures
12
Table of Contents
12
Cpu/Chapter 4 I\/O Ports
21
Table 1.2A MB89620 Series Product Lineup
25
Table 1.2B Common Specifications for MB89620 Series
26
Table 1.3 Package and Corresponding Products
27
Chapter 1 Overview
29
Figure 1.4 MB89620 Series Block Diagram
29
Figure 1.5A DIP-64P-M01, DIP-64C-A06, and MDP-64C-P02 Pin Assignment
31
Figure 1.5B FPT-64P-M03 and FPT-64P-M09 Pin Assignment
32
Figure 1.5C FPT-64P-M06 and MQP-64C-P01 Pin Assignment
33
Figure 1.6A DIP-64P-M01 Package Dimensions
35
Figure 1.6B DIP-64C-A06 Package Dimensions
36
Figure 1.6C FPT-64P-M03 Package Dimensions
37
Figure 1.6D FPT-64P-M06 Package Dimensions
38
Figure 1.6E FPT-64P-M09 Package Dimensions
39
Figure 1.6F MDP-64C-P02 Package Dimensions
40
Figure 1.6G MQP-64C-P01 Package Dimensions
41
Table 1.7A Pin Description
43
Table 1.7B Pin Description for External EPROM Pin (MB89PV620 Only)
46
Table 1.7C I/O Circuit Type
47
Cpu
52
Chapter 3 Cpu
52
Memory Space
53
Figure 3.1 Memory Map
54
Chapter 3 Cpu
55
Table 3.1.1 Vector Table
55
Figure 3.1.2A Storing 16-Bit Data in Memory
56
Figure 3.1.2B Byte Order of 16-Bit Data in an Instruction
56
Figure 3.2 Dedicated Register Configuration
57
Dedicated Registers
57
Figure 3.2.1A Structure of Condition Code Register
59
Figure 3.2.1B Change of Carry Flag by Shift Instruction
59
Table 3.2.1 Interrupt Level
60
Figure 3.2.2A Structure of Register Bank Pointer
61
Figure 3.2.2B Rule for Conversion of Actual Addresses of General-Purpose Register Area
61
Figure 3.3 Register Bank Structure
63
General-Purpose Registers
63
Table 3.4 Interrupt Request and Interrupt Vector
65
Interrupts
65
Figure 3.4.1 Structure of Interrupt Level Setting Registers
66
Table 3.4.1 Interrupt Level Setting Bit and Interrupt Level
66
Figure 3.4.2 Interrupt Processing
67
Figure 3.4.3 Example of Multiple Interrupts
69
Figure 3.4.4 Interrupt Processing Time
70
Figure 3.4.5 Stack Operation at Start of Interrupt Processing
71
Figure 3.4.6 Stack Area for Interrupt Processing
72
Table 3.5 Reset Source
73
Resets
73
Figure 3.5.1 Block Diagram of External Reset Pin
74
Table 3.5.1 Reset Source and Reset Output (Optional)
74
Figure 3.5.2 Reset Operation Flowchart
75
Clocks
79
Figure 3.6 Clock Supply Map
80
Figure 3.6.1A Connection Example for Crystal or Ceramic Resonator
81
Figure 3.6.1B Connection Example for External Clock
81
Figure 3.6.2 Block Diagram of Clock Controller
83
Figure 3.6.3 Operation of an Oscillator after Starting Oscillation
85
Table 3.7 Standby Mode Operating States
87
Standby Modes (Low-Power Consumption)
87
Figure 3.7.3 Standby Control Register (STBC)
91
Table 3.7.3 Standby Control Register (STBC) Bits
92
Figure 3.7.4A State Transition Diagram for Products with Power-On Reset
93
Figure 3.7.4B State Transition Diagram for Products Without Power-On Reset
93
Table 3.7.5 Pin States in Standby Modes
94
Memory Access Modes
97
Figure 3.8 Memory Map in each Mode
98
Figure 3.8.1A Mode Data Structure
99
Table 3.8.1A Mode Pin Setting
99
Figure 3.8.1B Memory Access Selection Operation
100
Table 3.8.1B Mode Pins and Mode Data
100
Table 3.8.2 External Bus Pin Functions in each Mode
101
Figure 3.8.3 External Bus Pin Control Register (BCTR)
102
Table 3.8.3 External Bus Pin Control Register (BCTR) Bit
102
Figure 3.8.4A External Bus Operation (Bus Cycle)
103
Figure 3.8.4B Example of Connecting External Memory and Peripheral Function
104
Figure 3.8.5A Ready Operation
105
Figure 3.8.5B Ready Signal Generator
105
Figure 3.8.5C Ready Signal Generation Timing
106
Figure 3.8.6 Hold Operation
107
I\/O Ports
108
Chapter 4 I/O Ports
108
Overview of I/O Ports
109
Table 4.1A Port Function
110
Table 4.1B Port Register
110
Table 4.2A Port 0 and 1 Pins
111
Ports 0 and 1
111
Figure 4.2 Block Diagram of Port 0 and 1 Pin (Single-Chip Mode)
112
Table 4.2B Correspondence between Pin and Register for Port 0 and Port 1
112
Table 4.2.1 Port 0 and 1 Register Function
113
Table 4.2.2 Port 0 and 1 Pin State (Single-Chip Mode)
114
Table 4.3A Port 2 Pin
115
Port 2
115
Figure 4.3 Block Diagram of Port 2 Pin (Single-Chip Mode)
116
Table 4.3B Correspondence between Pin and Register for Port 2
116
Table 4.3.1 Port 2 Register Function
117
Table 4.3.2 Port 2 Pin State (Single-Chip Mode)
118
Table 4.4A Port 3 Pin
119
Port 3
119
Figure 4.4 Block Diagram of Port 3 Pin
120
Table 4.4B Correspondence between Pin and Register for Port 3
120
Table 4.4.1 Port 3 Register Function
121
Port 4
125
Figure 4.5 Block Diagram of Port 4 Pin
126
Port 5
129
Figure 4.6 Block Diagram of Port 5 Pin
130
Figure 4.7 Block Diagram of Port 6 Pin
133
Port 6
133
Figure 4.8 Connection Example for an Eight Segment LED
137
Program Example for I/O Ports
137
Chapter 5 Timebase Timer
140
Figure 5.2 Block Diagram of Timebase Timer
140
Figure 5.3 Timebase Timer Control Register (TBTC)
141
Figure 5.5A Interval Timer Function Settings
145
Figure 5.5B Timebase Timer Operation
146
Figure 5.6 Effect on Buzzer Output of Clearing Timebase Timer
147
Chapter 6 Watchdog Timer
152
Figure 6.2 Block Diagram of Watchdog Timer
152
Figure 6.3 Watchdog Timer Control Register (WDTC)
153
Figure 6.4 Watchdog Timer Clear and Interval Time (for a 10 Mhz Source Oscillation)
154
-Bit Pwm Timer
158
Overview of 8-Bit PWM Timer
159
Chapter 7 8-Bit Pwm Timer
160
Figure 7.1 Example D/A Converter Configuration Using PWM Output and Low Pass Filter
160
Figure 7.2 Block Diagram of 8-Bit PWM Timer
161
Block Diagram of 8-Bit PWM Timer
161
Figure 7.3A Block Diagram of 8-Bit PWM Timer Pin
163
Structure of 8-Bit PWM Timer
163
Figure 7.3B 8-Bit PWM Timer Registers
164
Figure 7.3.1 PWM Control Register (CNTR)
165
Figure 7.3.2 PWM Compare Register (COMR)
167
8-Bit PWM Timer Interrupts
168
Figure 7.5A Interval Timer Function Settings
169
Figure 7.5B Operation of 8-Bit PWM Timer
169
Operation of Interval Timer Function
169
Figure 7.6A PWM Timer Function Settings
170
Figure 7.6B Example of PWM Waveform Output (PTO Pin)
170
Operation of PWM Timer Function
170
Figure 7.7A Counter Operation During Standby Modes or Operation Halt (for Interval Timer Function)
171
States in each Mode During 8-Bit PWM Timer
171
Operation
171
Figure 7.7B Operation During Standby Modes or Operation Halt (for PWM Timer Function)
172
Figure 7.8 Error on Starting Counter Operation
173
Notes on Using 8-Bit PWM Timer
173
Program Example for 8-Bit PWM Timer
175
Pulse Width Count Timer (Pwc)
178
Overview of Pulse Width Count Timer
179
Chapter 8 Pulse Width Count Timer (Pwc)
181
Figure 8.2 Block Diagram of Pulse Width Count Timer
181
Block Diagram of Pulse Width Count Timer
181
Figure 8.3A Block Diagram of Pulse Width Count Timer Pins
183
Structure of Pulse Width Count Timer
183
Figure 8.3B Pulse Width Count Timer Registers
184
Figure 8.3.1 PWC Pulse Width Control Register 1 (PCR1)
185
Figure 8.3.2 PWC Pulse Width Control Register 2 (PCR2)
187
Figure 8.3.3 PWC Reload Buffer Register (RLBR)
189
Pulse Width Count Timer Interrupts
190
Function
190
Figure 8.5A Interval Timer Function (Reload Timer Mode) Settings
191
Figure 8.5B Operation in Reload Timer Mode
191
Operation of Interval Timer Function
191
Figure 8.5C Interval Timer Function (One-Shot Timer Mode) Settings
192
Figure 8.5D Operation in One-Shot Timer Mode
192
Figure 8.6A Pulse Width Measurement Function Settings
193
Figure 8.6B Example of "H" Width Measurement Using Pulse Width Measurement Function
193
Figure 8.6C Measuring Long Pulse Widths
194
Figure 8.7 Counter Operation During Standby Modes or Operation Halt
195
States in each Mode During Pulse Width Count
195
Timer Operation
195
Figure 8.8 Error on Starting Counter Operation
196
Notes on Using Pulse Width Count Timer
196
Program Example for Timer Function of Pulse Width
197
Program Example for Pulse Width Measurement Function of Pulse Width Count Timer
199
-Bit Timer/Counter
200
Overview of 16-Bit Timer/Counter
201
Chapter 9 16-Bit Timer/Counter
203
Figure 9.2 Block Diagram of 16-Bit Timer/Counter
203
Block Diagram of 16-Bit Timer/Counter
203
Figure 9.3A Block Diagram of 16-Bit Timer/Counter Pin
205
Structure of 16-Bit Timer/Counter
205
Figure 9.3B 16-Bit Timer/Counter Registers
206
Figure 9.3.1 16-Bit Timer Control Register (TMCR)
207
Figure 9.3.2 16-Bit Timer Count Register (TCR)
209
16-Bit Timer/Counter Interrupts
210
Figure 9.5A Interval Timer Function Settings
211
Figure 9.5B Operation of Interval Timer
211
Operation of Interval Timer Function
211
Figure 9.6A Counter Function Settings
212
Figure 9.6B Operation of 16-Bit Counter
212
Operation of Counter Function
212
Figure 9.7 Counter Operation During Standby Modes or Operation Halt
213
States in each Mode During 16-Bit Timer/Counter Operation
213
Figure 9.8 Error on Starting Counter Operation
214
Notes on Using 16-Bit Timer/Counter
214
Program Examples for 16-Bit Timer/Counter
215
-Bit Serial I\/O (Serial I/O-1 and Serial I/O-2)
218
Overview of 8-Bit Serial I/O
219
Chapter 10 8-Bit Serial I/O (Serial I/O-1 and Serial I/O-2)
221
Figure 10.2 Block Diagram of 8-Bit Serial I/O
221
Block Diagram of 8-Bit Serial I/O
221
Structure of 8-Bit Serial I/O-1
223
Figure 10.3A Block Diagram of 8-Bit Serial I/O-1 Pins
224
Figure 10.3B 8-Bit Serial I/O-1 Registers
224
Figure 10.3.1 Serial 1 Mode Register (SMR1)
225
Figure 10.3.2 Serial 1 Data Register (SDR1)
227
Structure of 8-Bit Serial I/O-2
229
Figure 10.4A Block Diagram of 8-Bit Serial I/O-2 Pins
230
Figure 10.4B 8-Bit Serial I/O-2 Registers
230
Figure 10.4.1 Serial 2 Mode Register (SMR2)
231
Figure 10.4.2 Serial 2 Data Register (SDR2)
233
8-Bit Serial I/O Interrupts
234
Figure 10.6A Serial Output Settings (When Using Internal Shift Clock)
235
Figure 10.6B Serial Output Settings (When Using External Shift Clock)
235
Operation of Serial Output
235
Figure 10.6C 8-Bit Serial Output Operation
236
Figure 10.7A Serial Input Settings (When Using Internal Shift Clock)
237
Figure 10.7B Serial Input Settings (When Using External Shift Clock)
237
Operation of Serial Input
237
Figure 10.7C 8-Bit Serial Input Operation
238
Figure 10.8A Operation in Sleep Mode (Internal Shift Clock)
239
Figure 10.8B Operation in Stop Mode (Internal Shift Clock)
239
Figure 10.8C Operation During Halt (Internal Shift Clock)
239
States in each Mode During 8-Bit Serial I/O Operation
239
Figure 10.8D Operation in Sleep Mode (External Shift Clock)
240
Figure 10.8E Operation in Stop Mode (External Shift Clock)
240
Figure 10.8F Operation During Halt (External Shift Clock)
240
Figure 10.9 Idle State of Shift Clock
241
Notes on Using 8-Bit Serial I/O
241
Figure 10.10A Connection Example for 8-Bit Serial I/O (Interface between Two Mb89620S)
242
Figure 10.10B Bidirectional Serial I/O Operation
242
Connection Example for 8-Bit Serial I/O
242
Program Examples for 8-Bit Serial I/O
243
Buzzer Output
246
Overview of Buzzer Output
247
Chapter 11 Buzzer Output
248
Figure 11.2 Block Diagram of Buzzer Output
248
Block Diagram of Buzzer Output
248
Figure 11.3A Block Diagram of P44/BZ Pin
249
Figure 11.3B Buzzer Output Register
249
Structure of Buzzer Output
249
Figure 11.4 Buzzer Register (BZCR)
250
Buzzer Register (BZCR)
250
Program Example for Buzzer Output
251
External Interrupt Circuit (Edge)
252
Overview of External Interrupt Circuit
253
Chapter 12 External Interrupt Circuit (Edge)
254
Figure 12.2 Block Diagram of External Interrupt Circuit
254
Block Diagram of External Interrupt Circuit
254
Figure 12.3A Block Diagram of External Interrupt Circuit Pins
255
Structure of External Interrupt Circuit
255
Figure 12.3B External Interrupt Circuit Registers
256
Figure 12.3.1 External Interrupt 1 Control Register (EIC1)
257
Figure 12.3.2 External Interrupt 2 Control Register (EIC2)
259
External Interrupt Circuit Interrupts
261
Figure 12.5A External Interrupt Circuit Settings
262
Figure 12.5B External Interrupt (INT1) Operation
262
Operation of External Interrupt Circuit
262
Program Example for External Interrupt Circuit
263
A/D Converter
264
Overview of A/D Converter
265
Chapter 13 A/D Converter
267
Figure 13.2 Block Diagram of A/D Converter
267
Block Diagram of A/D Converter
267
Figure 13.3A Block Diagram of P30/ADST Pin
269
Structure of A/D Converter
269
Figure 13.3B Block Diagram of P57/AN7 to P50/AN0 Pins
270
Figure 13.3C A/D Converter Registers
270
Figure 13.3.1 A/D Control Register 1 (ADC1)
271
Figure 13.3.2 A/D Control Register 2 (ADC2)
273
Figure 13.3.3 A/D Data Register (ADCD)
275
A/D Converter Interrupts
276
Figure 13.5A A/D Conversion Function (Software Activation) Settings
277
Figure 13.5B A/D Conversion Function (Continuous Activation) Settings
277
A/D Converter Operation
277
Figure 13.5C Sense Function (Software Activation) Settings
278
Figure 13.5D Sense Function (Continuous Activation) Settings
278
Figure 13.6 Analog Input Equivalent Circuit
279
Notes on Using A/D Converter
279
Program Example for A/D Converter
281
Clock Monitor Function
284
Overview of Clock Monitor Function
285
Chapter 14 Clock Monitor Function
286
Figure 14.2 Block Diagram of Clock Monitor Function
286
Block Diagram of Clock Monitor Function
286
Figure 14.3 Block Diagram of P30/ADST/CLKO Pin
287
Structure of Clock Monitor Function
287
Figure 14.4 Clock Output Control Register (CLKE)
288
Clock Output Control Register (CLKE)
288
Appendix
295
Figure B.1A Direct Addressing
295
Figure B.1B Extended Addressing
295
Figure B.1C Bit Direct Addressing
295
Figure B.1D Index Addressing
296
Figure B.1E Pointer Addressing
296
Figure B.1F General-Purpose Register Addressing
296
Figure B.1G Immediate Addressing
296
Figure B.1H Vector Addressing
297
Figure B.1I Relative Addressing
297
Figure B.1J Inherent Addressing
297
Figure B.2A JMP @A
298
Figure B.2B MOVW A, PC
298
Figure B.2C MULU a
298
Figure B.2D DIVU a
299
Figure B.2E XCHW A,PC
299
Figure B.2F Example Using XCHW A,PC
299
Figure B.2G Execution Example of CALLV #3
300
Figure da Memory Map in EPROM Mode (MB89P625)
310
Figure Db Memory Map in EPROM Mode (MB89P627, MB89P629)
310
Figure DC Screening Procedure
314
Figure D.2 Memory Map of Piggyback/Evaluation Device
316
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