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HD64F2376
Hitachi HD64F2376 Manuals
Manuals and User Guides for Hitachi HD64F2376. We have
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Hitachi HD64F2376 manual available for free PDF download: Hardware Manual
Hitachi HD64F2376 Hardware Manual (949 pages)
16 Bit Single-Chip Microcomputer
Brand:
Hitachi
| Category:
Computer Hardware
| Size: 4.57 MB
Table of Contents
Table of Contents
7
Overview
25
Electrical Characteristics
36
Section 1 Overview
45
Features
45
Block Diagram
46
Pin Description
47
Pin Arrangement
47
Pin Arrangement in each Operating Mode
48
Pin Functions
54
Section 2 CPU
61
Features
61
Differences between H8S/2600 CPU and H8S/2000 CPU
62
Differences from H8/300 CPU
63
Differences from H8/300H CPU
63
CPU Operating Modes
64
Normal Mode
64
Advanced Mode
65
Address Space
68
Register Configuration
69
General Registers
70
Program Counter (PC)
71
Extended Register (EXR)
71
Condition-Code Register (CCR)
72
Initial Register Values
74
Data Formats
74
General Register Data Formats
74
Memory Data Formats
76
Instruction Set
77
Table of Instructions Classified by Function
78
Basic Instruction Formats
87
Addressing Modes and Effective Address Calculation
88
Register Direct-Rn
89
Register Indirect-@Ern
89
Register Indirect with Displacement-@(D:16, Ern) or @(D:32, Ern)
89
Register Indirect with Post-Increment or Pre-Decrement-@Ern+ or @-Ern
89
Absolute Address-@Aa:8, @Aa:16, @Aa:24, or @Aa:32
89
Immediate-#XX:8, #XX:16, or #XX:32
90
Program-Counter Relative-@(D:8, PC) or @(D:16, PC)
90
Memory Indirect-@@Aa:8
91
Effective Address Calculation
91
Processing States
94
Usage Notes
95
Note on Bit Manipulation Instructions
95
Section 3 MCU Operating Modes
97
Operating Mode Selection
97
Register Descriptions
98
Mode Control Register (MDCR)
98
System Control Register (SYSCR)
98
Operating Mode Descriptions
100
Mode 1
100
Mode 2
100
Mode 3
100
Mode 4
100
Mode 5
100
Mode 6
101
Mode 7
101
Pin Functions
102
Memory Map in each Operating Mode
103
Section 4 Exception Handling
107
Exception Handling Types and Priority
107
Exception Sources and Exception Vector Table
107
Reset
109
Reset Exception Handling
109
Interrupts after Reset
111
On-Chip Peripheral Functions after Reset Release
111
Traces
112
Interrupts
112
Trap Instruction
113
Stack Status after Exception Handling
114
Usage Notes
115
Section 5 Interrupt Controller
117
Features
117
Input/Output Pins
119
Register Descriptions
119
Interrupt Control Register (INTCR)
120
Interrupt Priority Registers a to K (IPRA to IPRK)
120
IRQ Enable Register (IER)
122
IRQ Sense Control Registers H and L (ISCRH, ISCRL)
124
IRQ Status Register (ISR)
129
IRQ Pin Select Register (ITSR)
130
Software Standby Release IRQ Enable Register (SSIER)
132
Interrupt Sources
132
External Interrupts
132
Internal Interrupts
133
Interrupt Exception Handling Vector Table
134
Interrupt Control Modes and Interrupt Operation
139
Interrupt Control Mode 0
139
Interrupt Control Mode 2
141
Interrupt Exception Handling Sequence
142
Interrupt Response Times
144
DTC and DMAC Activation by Interrupt
145
Usage Notes
146
Contention between Interrupt Generation and Disabling
146
Instructions that Disable Interrupts
147
Times When Interrupts Are Disabled
147
Interrupts During Execution of EEPMOV Instruction
147
Change of IRQ Pin Select Register (ITSR) Setting
147
Section 6 Bus Controller (BSC)
149
Features
149
Input/Output Pins
151
Register Descriptions
153
Bus Width Control Register (ABWCR)
154
Access State Control Register (ASTCR)
154
Wait Control Registers AH, AL, BH, and BL (WTCRAH, WTCRAL, WTCRBH, and WTCRBL)
155
Read Strobe Timing Control Register (RDNCR)
160
CS Assertion Period Control Registers H, L (CSACRH, CSACRL)
161
Area 0 Burst ROM Interface Control Register (BROMCRH) Area 1 Burst ROM Interface Control Register (BROMCRL)
163
Bus Control Register (BCR)
164
DRAM Control Register (DRAMCR)
166
DRAM Access Control Register (DRACCR)
173
Refresh Control Register (REFCR)
176
Refresh Timer Counter (RTCNT)
179
Refresh Time Constant Register (RTCOR)
179
Bus Control
179
Area Division
179
Bus Specifications
181
Memory Interfaces
182
Chip Select Signals
184
Basic Bus Interface
185
Data Size and Data Alignment
185
Valid Strobes
187
Basic Timing
187
Wait Control
195
Read Strobe ( RD ) Timing
197
Extension of Chip Select ( CS ) Assertion Period
198
DRAM Interface
199
Setting DRAM Space
199
Address Multiplexing
200
Data Bus
201
Pins Used for DRAM Interface
202
Basic Timing
203
Column Address Output Cycle Control
204
Row Address Output State Control
205
Precharge State Control
207
Wait Control
208
Byte Access Control
211
Burst Operation
212
Refresh Control
216
DMAC and EXDMAC Single Address Transfer Mode and DRAM Interface
221
Synchronous DRAM Interface
224
Setting Continuous Synchronous DRAM Space
224
Address Multiplexing
225
Data Bus
226
Pins Used for Synchronous DRAM Interface
226
Synchronous DRAM Clock
228
Basic Timing
228
CAS Latency Control
230
Row Address Output State Control
232
Precharge State Count
234
Bus Cycle Control in Write Cycle
236
Byte Access Control
237
Burst Operation
239
Refresh Control
243
Mode Register Setting of Synchronous DRAM
248
DMAC and EXDMAC Single Address Transfer Mode and Synchronous DRAM Interface
250
Burst ROM Interface
255
Basic Timing
255
Wait Control
257
Write Access
257
Idle Cycle
258
Operation
258
Pin States in Idle Cycle
274
Write Data Buffer Function
274
Bus Release
275
Operation
275
Pin States in External Bus Released State
277
Transition Timing
278
Bus Arbitration
280
Operation
280
Bus Transfer Timing
280
Bus Controller Operation in Reset
282
Usage Notes
282
External Bus Release Function and All-Module-Clocks-Stopped Mode
282
External Bus Release Function and Software Standby
282
External Bus Release Function and CBR Refreshing/Auto Refreshing
282
BREQO Output Timing
283
Notes on Usage of the Synchronous DRAM
283
Section 7 DMA Controller (DMAC)
285
Features
285
Input/Output Pins
287
Register Descriptions
287
Memory Address Registers (MARA and MARB)
288
I/O Address Registers (IOARA and IOARB)
289
Execute Transfer Count Registers (ETCRA and ETCRB)
289
DMA Control Registers (DMACRA and DMACRB)
291
DMA Band Control Registers H and L (DMABCRH and DMABCRL)
298
DMA Write Enable Register (DMAWER)
310
DMA Terminal Control Register (DMATCR)
312
Activation Sources
313
Activation by Internal Interrupt Request
313
Activation by External Request
314
Activation by Auto-Request
314
Operation
315
Transfer Modes
315
Sequential Mode
317
Idle Mode
319
Repeat Mode
321
Single Address Mode
324
Normal Mode
327
Block Transfer Mode
330
Basic Bus Cycles
336
DMA Transfer (Dual Address Mode) Bus Cycles
336
DMA Transfer (Single Address Mode) Bus Cycles
344
Write Data Buffer Function
350
Multi-Channel Operation
351
Relation between DMAC and External Bus Requests, Refresh Cycles, and EXDMAC
352
DMAC and NMI Interrupts
353
Forced Termination of DMAC Operation
353
Clearing Full Address Mode
354
Interrupt Sources
355
Usage Notes
356
DMAC Register Access During Operation
356
Module Stop
358
Write Data Buffer Function
358
TEND Output
358
Activation by Falling Edge on DREQ Pin
359
Activation Source Acceptance
360
Internal Interrupt after End of Transfer
360
Channel Re-Setting
360
Section 8 EXDMA Controller
361
Features
361
Input/Output Pins
363
Register Descriptions
363
EXDMA Source Address Register (EDSAR)
364
EXDMA Destination Address Register (EDDAR)
364
EXDMA Transfer Count Register (EDTCR)
365
EXDMA Mode Control Register (EDMDR)
367
EXDMA Address Control Register (EDACR)
371
Operation
375
Transfer Modes
375
Address Modes
376
DMA Transfer Requests
380
Bus Modes
380
Transfer Modes
382
Repeat Area Function
384
Registers During DMA Transfer Operation
386
Channel Priority Order
390
EXDMAC Bus Cycles (Dual Address Mode)
393
EXDMAC Bus Cycles (Single Address Mode)
398
Examples of Operation Timing in each Mode
403
Ending DMA Transfer
416
Relationship between EXDMAC and Other Bus Masters
417
Interrupt Sources
417
Usage Notes
420
EXDMAC Register Access During Operation
420
Module Stop State
420
EDREQ Pin Falling Edge Activation
420
Activation Source Acceptance
420
Enabling Interrupt Requests When IRF = 1 in EDMDR
421
ETEND Pin and CBR Refresh Cycle
421
Section 9 Data Transfer Controller (DTC)
423
Features
423
Register Configuration
424
DTC Mode Register a (MRA)
425
DTC Mode Register B (MRB)
426
DTC Source Address Register (SAR)
426
DTC Destination Address Register (DAR)
426
DTC Transfer Count Register a (CRA)
426
DTC Transfer Count Register B (CRB)
427
DTC Enable Registers a to H (DTCERA to DTCERH)
427
DTC Vector Register (DTVECR)
427
Activation Sources
428
Location of Register Information and DTC Vector Table
429
Operation
432
Normal Mode
434
Repeat Mode
435
Block Transfer Mode
436
Chain Transfer
437
Interrupts
438
Operation Timing
439
Number of DTC Execution States
440
Procedures for Using DTC
441
Activation by Interrupt
441
Activation by Software
441
Examples of Use of the DTC
441
Normal Mode
441
Chain Transfer
442
Chain Transfer When Counter = 0
443
Software Activation
444
Usage Notes
445
Module Stop Mode Setting
445
On-Chip RAM
445
DTCE Bit Setting
445
DMAC Transfer End Interrupt
445
Chain Transfer
445
Section 10 I/O Ports
447
Port 1
452
Port 1 Data Direction Register (P1DDR)
452
Port 1 Data Register (P1DR)
452
Port 1 Register (PORT1)
453
Pin Functions
453
Port 2
463
Port 2 Data Direction Register (P2DDR)
463
Port 2 Data Register (P2DR)
463
Port 2 Register (PORT2)
464
Pin Functions
465
Port 3
473
Port 3 Data Direction Register (P3DDR)
473
Port 3 Data Register (P3DR)
474
Port 3 Register (PORT3)
474
Port 3 Open Drain Control Register (P3ODR)
475
Port Function Control Register 2 (PFCR2)
476
Pin Functions
477
Port 4
480
Port 4 Register (PORT4)
480
Pin Functions
480
Port 5
482
Port 5 Data Direction Register (P5DDR)
482
Port 5 Data Register (P5DR)
482
Port 5 Register (PORT5)
483
Pin Functions
483
Port 6
485
Port 6 Data Direction Register (P6DDR)
485
Port 6 Data Register (P6DR)
485
Port 6 Register (PORT6)
486
Pin Functions
486
Port 8
489
Port 8 Data Direction Register (P8DDR)
489
Port 8 Data Register (P8DR)
490
Port 8 Register (PORT8)
490
Pin Functions
491
Port 9
495
Port 9 Register (PORT9)
495
Pin Functions
495
Port a
497
Port a Data Direction Register (PADDR)
498
Port a Data Register (PADR)
499
Port a Register (PORTA)
499
Port a MOS Pull-Up Control Register (PAPCR)
500
Port a Open Drain Control Register (PAODR)
500
Port Function Control Register 1 (PFCR1)
500
Pin Functions
502
Port a MOS Input Pull-Up States
503
Port B
504
Port B Data Direction Register (PBDDR)
504
Port B Data Register (PBDR)
505
Port B Register (PORTB)
505
Port B MOS Pull-Up Control Register (PBPCR)
506
10.10.5 Pin Functions
506
10.10.6 Port B MOS Input Pull-Up States
507
Port C
508
Port C Data Direction Register (PCDDR)
508
Port C Data Register (PCDR)
509
Port C Register (PORTC)
509
Port C MOS Pull-Up Control Register (PCPCR)
510
10.11.5 Pin Functions
510
10.11.6 Port C MOS Input Pull-Up States
511
Port D
512
Port D Data Direction Register (PDDDR)
512
Port D Data Register (PDDR)
512
Port D Register (PORTD)
513
Port D Pull-Up Control Register (PDPCR)
513
10.12.5 Pin Functions
513
10.12.6 Port D MOS Input Pull-Up States
514
Port E
515
Port E Data Direction Register (PEDDR)
515
Port E Data Register (PEDR)
516
Port E Register (PORTE)
516
Port E Pull-Up Control Register (PEPCR)
517
10.13.5 Pin Functions
517
10.13.6 Port E MOS Input Pull-Up States
518
Port F
519
Port F Data Direction Register (PFDDR)
519
Port F Data Register (PFDR)
521
Port F Register (PORTF)
521
10.14.4 Pin Functions
522
Port G
526
Port G Data Direction Register
526
Port G Data Register
528
Port G Register (PORTG)
528
Port Function Control Register 0 (PFCR0)
529
Pin Functions
529
Port H
532
Port H Data Direction Register (PHDDR)
532
Port H Data Register (PHDR)
534
Port H Register (PORTH)
534
10.16.4 Pin Functions
535
Section 11 16-Bit Timer Pulse Unit (TPU)
537
Features
537
Input/Output Pins
541
Register Descriptions
542
Timer Control Register (TCR)
543
Timer Mode Register (TMDR)
549
Timer I/O Control Register (TIOR)
550
Timer Interrupt Enable Register (TIER)
568
Timer Status Register (TSR)
570
Timer Counter (TCNT)
572
Timer General Register (TGR)
573
Timer Start Register (TSTR)
573
Timer Synchronous Register (TSYR)
574
Operation
575
Basic Functions
575
Synchronous Operation
580
Buffer Operation
582
Cascaded Operation
585
PWM Modes
587
Phase Counting Mode
592
Interrupts
598
DTC Activation
600
DMAC Activation
600
A/D Converter Activation
600
Operation Timing
601
Input/Output Timing
601
Interrupt Signal Timing
604
Usage Notes
607
11.10.1 Module Stop Mode Setting
607
11.10.2 Input Clock Restrictions
607
11.10.3 Caution on Cycle Setting
608
11.10.4 Contention between TCNT Write and Clear Operations
608
11.10.5 Contention between TCNT Write and Increment Operations
609
11.10.6 Contention between TGR Write and Compare Match
610
11.10.7 Contention between Buffer Register Write and Compare Match
610
11.10.8 Contention between TGR Read and Input Capture
611
11.10.9 Contention between TGR Write and Input Capture
612
11.10.10 Contention between Buffer Register Write and Input Capture
612
11.10.11 Contention between Overflow/Underflow and Counter Clearing
613
11.10.12 Contention between TCNT Write and Overflow/Underflow
614
11.10.13 Multiplexing of I/O Pins
614
11.10.14 Interrupts and Module Stop Mode
614
Section 12 Programmable Pulse Generator (PPG)
615
Features
615
Input/Output Pins
617
Register Descriptions
617
Next Data Enable Registers H, L (NDERH, NDERL)
618
Output Data Registers H, L (PODRH, PODRL)
619
Next Data Registers H, L (NDRH, NDRL)
620
PPG Output Control Register (PCR)
622
PPG Output Mode Register (PMR)
623
Operation
625
Output Timing
626
Sample Setup Procedure for Normal Pulse Output
627
Example of Normal Pulse Output (Example of Five-Phase Pulse Output)
628
Non-Overlapping Pulse Output
629
Sample Setup Procedure for Non-Overlapping Pulse Output
630
Example of Non-Overlapping Pulse Output (Example of Four-Phase Complementary Non-Overlapping Output)
631
Inverted Pulse Output
632
Pulse Output Triggered by Input Capture
633
Usage Notes
633
Module Stop Mode Setting
633
Operation of Pulse Output Pins
633
Section 13 8-Bit Timers (TMR)
635
Features
635
Input/Output Pins
637
Register Descriptions
637
Timer Counter (TCNT)
637
Time Constant Register a (TCORA)
638
Time Constant Register B (TCORB)
638
Timer Control Register (TCR)
638
Timer Control/Status Register (TCSR)
640
Operation
643
Pulse Output
643
Operation Timing
644
TCNT Incrementation Timing
644
Timing of CMFA and CMFB Setting When Compare-Match Occurs
645
Timing of Timer Output When Compare-Match Occurs
645
Timing of Compare Match Clear
646
Timing of TCNT External Reset
646
Timing of Overflow Flag (OVF) Setting
647
Operation with Cascaded Connection
647
16-Bit Counter Mode
647
Compare Match Count Mode
648
Interrupts
648
Interrupt Sources and DTC Activation
648
A/D Converter Activation
649
Usage Notes
650
Contention between TCNT Write and Clear
650
Contention between TCNT Write and Increment
650
Contention between TCOR Write and Compare Match
651
Contention between Compare Matches a and B
652
Switching of Internal Clocks and TCNT Operation
653
Mode Setting with Cascaded Connection
655
Interrupts in Module Stop Mode
655
Section 14 Watchdog Timer
657
Features
657
Input/Output Pin
658
Register Descriptions
658
Timer Counter (TCNT)
659
Timer Control/Status Register (TCSR)
659
Reset Control/Status Register (RSTCSR)
661
Operation
662
Watchdog Timer Mode
662
Interval Timer Mode
663
Interrupts
664
Usage Notes
664
Notes on Register Access
664
Contention between Timer Counter (TCNT) Write and Increment
665
Changing Value of CKS2 to CKS0
666
Switching between Watchdog Timer Mode and Interval Timer Mode
666
Internal Reset in Watchdog Timer Mode
666
System Reset by WDTOVF Signal
667
Section 15 Serial Communication Interface (SCI, Irda)
669
Features
669
Input/Output Pins
672
Register Descriptions
672
Receive Shift Register (RSR)
674
Receive Data Register (RDR)
674
Transmit Data Register (TDR)
674
Transmit Shift Register (TSR)
674
Serial Mode Register (SMR)
674
Serial Control Register (SCR)
677
Serial Status Register (SSR)
682
Smart Card Mode Register (SCMR)
689
Bit Rate Register (BRR)
690
Irda Control Register (Ircr)
699
Serial Extension Mode Register (SEMR)
700
Operation in Asynchronous Mode
702
Data Transfer Format
702
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
704
Clock
705
SCI Initialization (Asynchronous Mode)
706
Data Transmission (Asynchronous Mode)
707
Serial Data Reception (Asynchronous Mode)
709
Multiprocessor Communication Function
713
Multiprocessor Serial Data Transmission
715
Multiprocessor Serial Data Reception
717
Operation in Clocked Synchronous Mode
720
Clock
720
SCI Initialization (Clocked Synchronous Mode)
721
Serial Data Transmission (Clocked Synchronous Mode)
722
Serial Data Reception (Clocked Synchronous Mode)
725
Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode)
727
Operation in Smart Card Interface Mode
729
Pin Connection Example
729
Data Format (Except for Block Transfer Mode)
729
Block Transfer Mode
731
Receive Data Sampling Timing and Reception Margin
731
Initialization
732
Data Transmission (Except for Block Transfer Mode)
733
Serial Data Reception (Except for Block Transfer Mode)
736
Clock Output Control
737
Irda Operation
739
SCI Interrupts
742
Interrupts in Normal Serial Communication Interface Mode
742
Interrupts in Smart Card Interface Mode
743
Usage Notes
745
15.10.1 Module Stop Mode Setting
745
15.10.2 Break Detection and Processing
745
15.10.3 Mark State and Break Sending
745
Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)
745
15.10.5 Relation between Writes to TDR and the TDRE Flag
745
15.10.6 Restrictions on Use of DMAC or DTC
746
15.10.7 Operation in Case of Mode Transition
746
Section 16 I C Bus Interface2 (IIC2) (Option)
751
Features
751
Input/Output Pins
753
Register Description
753
C Bus Control Register a (ICCRA)
754
C Bus Control Register B (ICCRB)
756
C Bus Mode Register (ICMR)
757
C Bus Interrupt Enable Register (ICIER)
759
C Bus Status Register (ICSR)
761
Slave Address Register (SAR)
763
C Bus Transmit Data Register (ICDRT)
763
C Bus Receive Data Register (ICDRR)
763
C Bus Shift Register (ICDRS)
763
Operation
764
C Bus Format
764
Master Transmit Operation
765
Master Receive Operation
767
Slave Transmit Operation
769
Slave Receive Operation
771
Noise Canceler
773
Example of Use
773
Interrupt Request
778
Bit Synchronous Circuit
779
Section 17 A/D Converter
781
Features
781
Input/Output Pins
782
Register Description
783
A/D Data Registers a to H (ADDRA to ADDRH)
784
A/D Control/Status Register (ADCSR)
785
A/D Control Register (ADCR)
787
Operation
788
Single Mode
788
Scan Mode
788
Input Sampling and A/D Conversion Time
789
External Trigger Input Timing
790
Interrupts
791
A/D Conversion Precision Definitions
791
Usage Notes
793
Module Stop Mode Setting
793
Permissible Signal Source Impedance
793
Influences on Absolute Precision
793
Setting Range of Analog Power Supply and Other Pins
794
Notes on Board Design
794
Notes on Noise Countermeasures
794
Section 18 D/A Converter
797
Features
797
Input/Output Pins
798
Register Description
798
D/A Data Registers 0 to
798
D/A Control Registers 01, 23, and 45 (DACR01, DACR23, DACR45)
799
Operation
804
Usage Notes
805
Setting for Module Stop Mode
805
D/A Output Hold Function in Software Standby Mode
805
Section 19 RAM
807
Section 20 Flash Memory (F-ZTAT Version)
809
Features
809
Mode Transitions
810
Block Configuration
814
Input/Output Pins
816
Register Descriptions
816
Flash Memory Control Register 1 (FLMCR1)
816
Flash Memory Control Register 2 (FLMCR2)
817
Erase Block Register 1 (EBR1)
818
Erase Block Register 2 (EBR2)
818
RAM Emulation Register (RAMER)
820
On-Board Programming Modes
822
Boot Mode
822
User Program Mode
825
Flash Memory Emulation in RAM
826
Flash Memory Programming/Erasing
828
Program/Program-Verify
828
Erase/Erase-Verify
830
Interrupt Handling When Programming/Erasing Flash Memory
830
Program/Erase Protection
832
Hardware Protection
832
Software Protection
832
Error Protection
832
Programmer Mode
833
Power-Down States for Flash Memory
833
Usage Notes
833
Section 21 Clock Pulse Generator
837
Register Description
837
System Clock Control Register (SCKCR)
837
PLL Control Register (PLLCR)
839
Oscillator
839
Connecting a Crystal Oscillator
840
External Clock Input
841
PLL Circuit
842
Frequency Divider
843
Usage Notes
843
Notes on Clock Pulse Generator
843
Notes on Oscillator
843
Notes on Board Design
844
Section 22 Power-Down Modes
845
Register Descriptions
848
Standby Control Register (SBYCR)
848
Module Stop Control Registers H and L (MSTPCRH, MSTPCRL)
850
Extension Module Stop Control Registers H and L (EXMSTPCRH, EXMSTPCRL)
851
Operation
852
Clock Division Mode
852
Sleep Mode
852
Software Standby Mode
853
Hardware Standby Mode
855
Module Stop Mode
856
All-Module-Clocks-Stop Mode
857
Ø Clock Output Control
857
Usage Notes
858
I/O Port Status
858
Current Dissipation During Oscillation Stabilization Standby Period
858
EXDMAC/DMAC/DTC Module Stop
858
On-Chip Peripheral Module Interrupts
858
Writing to MSTPCR, EXMSTPCR
858
Section 23 List of Registers
859
Register Addresses (Address Order)
859
Register Bits
871
Register States in each Operating Mode
885
Section 24 Electrical Characteristics
895
Absolute Maximum Ratings
895
DC Characteristics
896
AC Characteristics
899
Clock Timing
900
Control Signal Timing
902
Bus Timing
904
DMAC and EXDMAC Timing
925
Timing of On-Chip Peripheral Modules
929
A/D Conversion Characteristics
934
D/A Conversion Characteristics
934
Flash Memory Characteristics
935
Usage Note
937
Appendix
939
I/O Port States in each Pin State
939
Product Lineup
947
Package Dimensions
948
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