Motorola MPC534 Manuals

Manuals and User Guides for Motorola MPC534. We have 1 Motorola MPC534 manual available for free PDF download: Reference Manual

Motorola MPC534 Reference Manual (1215 pages)

Brand: Motorola | Category: Microcontrollers | Size: 13.97 MB

Table of Contents
3
Paragraph
4
Number Title Number
4
About this Book
65
Audience
65
Organization
65
Suggested Reading
68
Conventions and Nomenclature
69
Notational Conventions
71
Acronyms and Abbreviations
71
References
73
Overview
75
Introduction
75
Block Diagram
76
Key Features
77
High Performance CPU System
77
RISC MCU Central Processing Unit (RCPU)
77
Mpc5Xx System Interface (USIU)
78
Burst Buffer Controller (BBC) Module
78
Flexible Memory Protection Unit
79
Memory Controller
79
512-Kbytes of CDR3 Flash EEPROM Memory (UC3F)
79
32-Kbyte Static RAM (CALRAM)
79
General Purpose I/O Support (GPIO)
80
Nexus Debug Port (Class 3)
80
Integrated I/O System
80
22-Channel Modular I/O System (MIOS14)
80
Enhanced Queued Analog-To-Digital Converter Module (QADC64E)
80
One CAN 2.0B Controller (Toucan) Module
81
Queued Serial Multi-Channel Module (QSMCM)
81
Peripheral Pin Multiplexing (PPM)
82
MPC533 Optional Features
82
Comparison of MPC533 and MPC555
82
Additional MPC533 Differences
83
SRAM Keep-Alive Power Behavior
84
MPC533 Address Map
85
Supporting Documentation List
87
Signal Descriptions
89
Signal Groupings
89
Signal Summary
91
MPC533 Signal Multiplexing
109
READI Port Signal Sharing
109
Pad Module Configuration Register (PDMCR)
110
Pad Module Configuration Register (PDMCR2)
112
MPC533 Development Support Signal Sharing
112
JTAG Mode Selection
113
Reset State
114
Signal Functionality Configuration out of Reset
114
Signal State During Reset
114
Power-On Reset and Hard Reset
115
Pull-Up/Pull-Down
115
Pull-Up/Pull-Down Enable and Disable for 5-V Only and 2.6-V Only Signals
115
Pull-Down Enable and Disable for 5-V/2.6-V Multiplexed Signals
115
Special Pull Resistor Disable Control Functionality (SPRDS)
116
Pull Device Select (PULL_SEL)
116
Signal Reset States
116
Central Processing Unit
117
RCPU Block Diagram
118
RCPU Key Features
119
Instruction Sequencer
119
Independent Execution Units
120
Branch Processing Unit (BPU)
121
Integer Unit (IU)
122
Load/Store Unit (LSU)
122
Floating-Point Unit (FPU)
123
Levels of the MPC500 Architecture
123
RCPU Programming Model
124
User Instruction Set Architecture (UISA) Register Set
129
General-Purpose Registers (Gprs)
129
Floating-Point Registers (Fprs)
129
Floating-Point Status and Control Register (FPSCR)
130
Condition Register (CR)
133
Condition Register CR0 Field Definition
134
Condition Register CR1 Field Definition
134
Condition Register Crn Field - Compare Instruction
135
Integer Exception Register (XER)
135
Link Register (LR)
136
Count Register (CTR)
137
VEA Register Set - Time Base (TB)
137
OEA Register Set
138
Machine State Register (MSR)
138
Dae/Source Instruction Service Register (DSISR)
140
Data Address Register (DAR)
141
Time Base Facility (TB) - OEA
141
Decrementer Register (DEC)
142
Machine Status Save/Restore Register 0 (SRR0)
142
Machine Status Save/Restore Register 1 (SRR1)
143
General Sprs (SPRG0-SPRG3)
143
Processor Version Register (PVR)
144
Implementation-Specific Sprs
145
EIE, EID, and NRI Special-Purpose Registers
145
Additional Implementation-Specific Registers
146
Instruction Set
146
Instruction Set Summary
148
Recommended Simplified Mnemonics
153
Calculating Effective Addresses
153
Exception Model
154
Exception Classes
155
Ordered Exceptions
155
Unordered Exceptions
155
Precise Exceptions
156
Exception Vector Table
156
Instruction Timing
156
User Instruction Set Architecture (UISA)
158
Computation Modes
158
Reserved Fields
158
Classes of Instructions
159
Exceptions
159
Branch Processor
159
Instruction Fetching
159
Branch Instructions
159
Invalid Branch Instruction Forms
159
Branch Prediction
160
Fixed-Point Processor
160
Fixed-Point Instructions
160
Floating-Point Processor
161
General
161
Optional Instructions
161
Load/Store Processor
161
Fixed-Point Load with Update and Store with Update Instructions
161
Fixed-Point Load and Store Multiple Instructions
161
Fixed-Point Load String Instructions
161
Storage Synchronization Instructions
161
Floating-Point Load and Store with Update Instructions
162
Floating-Point Load Single Instructions
162
Floating-Point Store Single Instructions
162
Optional Instructions
162
Virtual Environment Architecture (VEA)
162
Atomic Update Primitives
162
Effect of Operand Placement on Performance
163
Storage Control Instructions
163
Instruction Synchronize (Isync) Instruction
163
Enforce In-Order Execution of I/O (Eieio) Instruction
163
Time Base
163
Operating Environment Architecture (OEA)
163
Branch Processor Registers
164
Machine State Register (MSR)
164
Branch Processors Instructions
164
Fixed-Point Processor
164
Special Purpose Registers
164
Storage Control Instructions
164
Exceptions
164
System Reset Exception and NMI (0X0100)
165
Machine Check Exception (0X0200)
166
Data Storage Exception (0X0300)
167
Instruction Storage Exception (0X0400)
168
External Interrupt (0X0500)
168
Alignment Exception (0X00600)
169
Program Exception (0X0700)
171
Floating-Point Unavailable Exception (0X0800)
172
Decrementer Exception (0X0900)
173
System Call Exception (0X0C00)
174
Trace Exception (0X0D00)
175
Floating-Point Assist Exception (0X0E00)
176
Implementation-Dependent Software Emulation Exception (0X1000)
176
Implementation-Dependent Instruction Protection Exception (0X1300)
177
Implementation-Specific Data Protection Error Exception (0X1400)
178
Implementation-Dependent Debug Exceptions
179
Partially Executed Instructions
180
Timer Facilities
181
Optional Facilities and Instructions
181
Burst Buffer Controller 2 Module
183
Key Features
184
BIU Key Features
184
IMPU Key Features
184
ICDU Key Features
185
DECRAM Key Features
185
Branch Target Buffer Key Features
185
Operation Modes
186
Instruction Fetch
186
Decompression off Mode
186
Decompression on Mode
186
Burst Operation and Access Violation Detection
187
Slave Operation
187
Reset Behavior
187
Debug Operation Mode
187
Exception Table Relocation (ETR)
188
ETR Overview
188
ETR Operation
189
Enhanced External Interrupt Relocation (EEIR)
191
Decompressor RAM (DECRAM) Functionality
193
General-Purpose Memory Operation
193
Memory Protection Violations
194
DECRAM Standby Operation Mode
194
Branch Target Buffer
194
BTB Operation
195
BTB Invalidation
196
BTB Enabling/Disabling
196
BTB Inhibit Regions
196
BBC Programming Model
197

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