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PD17062
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NEC PD17062 manual available for free PDF download: Datasheet
NEC PD17062 Datasheet (296 pages)
MOS INTEGRATED CIRCUIT 4-BIT SINGLE-CHIP MICROCONTROLLER CONTAINING PLL FREQUENCY SYNTHESIZER AND IMAGE DISPLAY CONTROLLER
Brand:
NEC
| Category:
Controller
| Size: 1.57 MB
Table of Contents
Pwm
2
Table of Contents
6
1 Pins
11
Pin Functions
11
Equivalent Circuits of the Pins
14
2 Program Memory (Rom)
18
Configuration of Program Memory
18
Functions of Program Memory
19
Program Flow
19
Branching a Program
20
Table Reference
24
Notes on Using the Branch Instruction and Subroutine Call Instruction
24
3 Program Counter (Pc)
25
4 Stack
26
Components
26
Stack Pointer (Sp)
26
ADDRESS STACK REGISTERS (Asrs)
27
Interrupt Stack Registers
27
5 Data Memory (Ram)
29
Structure of Data Memory
29
Functions of Data Memory
34
Notes on Using Data Memory
38
6 General-Purpose Register (Gr)
40
Structure of the General-Purpose Register
40
Function of the General-Purpose Register
40
Address Generation for General-Purpose Register and Data Memory in Individual Instructions
42
Notes on Using the General-Purpose Register
46
7 Arithmetic Logic Unit (Alu) Block
48
Overview
48
Configuration and Functions of the Components of the Alu Block
49
Alu Operations
50
Notes on Using the Alu
53
8 System Register (Sysreg)
54
Address Register (Ar)
55
Window Register (Wr)
55
Bank Register (Bank)
56
Memory Pointer Enable Flag (Mpe)
56
Index Register (IX) and Data Memory Row Address Pointer (Mp)
57
General-Purpose Register Pointer (Rp)
66
Program Status Word (Psword)
66
9 Register File (Rf)
67
Idcdmaen
75
Sp (01H)
75
CE (07H, B )
76
Serial Interface Mode Register (08H)
76
Btm0Md (09H)
77
INTVSYN (0FH, B 2 )
77
INTNC (0FH, B )
78
Horizontal Synchronizing Signal Counter Control (11H, 12H)
78
Pll Reference Mode Selection Register (13H)
79
Setting of Intnc Pin Acceptance Pulse Width (15H)
79
Timer Carry (17H)
80
Serial Interface Wait Control (18H)
80
Iegnc (1Fh)
80
A/D Convertor Control (21H)
81
Pll Unlock Flip-Flop Judge Register (22H)
81
Port1C I/O Setting (27H)
82
Serial I/O0 Status Register (28H)
82
Interrupt Permission Flag (2Fh)
83
Crom Bank Selection (30H)
83
Idcen (31H)
84
Pll Unlock Flip-Flop Delay Control Register (32H)
84
P1Bbion (35H)
85
P0Bbion (36H)
85
P0Abion (37H)
86
Setting of Interrupt Request Generation Timing in Serial Interface Mode (38H)
86
Shift Clock Frequency Setting (39H)
87
Irqnc (3Fh)
87
10 Data Buffer (Dbf)
88
Data Buffer Structure
88
Functions of Data Buffer
90
Data Buffer and Table Referencing
91
Data Buffer and Peripheral Hardware
93
Data Buffer and Peripheral Registers
97
Precautions When Using Data Buffers
104
11 Interrupt
106
Interrupt Block Configuration
106
Interrupt Function
108
Interrupt Acceptance
111
Operations after Interrupt Acceptance
116
Returning Control from Interrupt Processing Routine
116
Interrupt Processing Routine
119
External Interrupts
121
Nc Pin, Vsync Pin)
121
Internal Interrupt (Timer, Serial Interface)
123
Multiple Interrupts
124
12 Timer
133
Timer Configuration
133
Timer Functions
134
Timer Carry Flip-Flop (Timer Carry Ff)
136
Cautions in Using the Timer Carry Ff
141
Timer Interrupt
147
Cautions in Using the Timer Interrupt
151
13 Standby
153
Standby Block Configuration
153
Standby Function
154
Device Operation Mode Specified at the Ce Pin
155
Halt Function
156
Clock Stop Function
164
Operation of the Device at a Halt or Clock Stop
167
14 Reset
171
Reset Block Configuration
171
Reset Function
172
Ce Reset
173
Power-On Reset
177
Relationship between Ce Reset and Power-On Reset
180
Power Failure Detection
184
15 General-Purpose Port
189
Configuration and Classification of General-Purpose Port
189
Functions of General-Purpose Ports
191
General-Purpose I/O Ports (P0A, P0B, P1B, P1C)
194
General-Purpose Input Port (P0D)
198
General-Purpose Output Ports (P0C, P1A)
199
16 Serial Interface
201
Serial Interface Mode Register
201
Clock Counter
206
Status Register
207
Wait Register
209
Presettable Shift Register (Psr)
214
Serial Interface Interrupt Source Register (Sio0Imd)
215
Shift Clock Frequency Register (Sio0Ck)
216
17 D/A Converter
217
Pwm Pins
217
18 Pll Frequency Synthesizer
219
Pll Frequency Synthesizer Configuration
219
Overview of each Pll Frequency Synthesizer Block
220
Programmable Divider (Pd) and Pll Mode Select Register
221
Reference Frequency Generator (Rfg)
223
Phase Comparator ( -Det), Charge Pump, and Unlock Detection Block
225
Pll Disable Mode
231
Setting Data for the Pll Frequency Synthesizer
232
19 A/D Converter
233
Principle of Operation
233
D/A Converter Configuration
234
Reference Voltage Setting Register (Adcr)
235
Comparison Register (Adccmp)
235
ADC PIN SELECT REGISTER (Adcchn)
236
Example of A/D Conversion Program
237
20 Image Display Controller
240
Specification Overview and Restrictions
240
Direct Memory Access
243
IDC Enable Flag
245
Vram
246
Character Rom
255
Blank, R, G, and B Pins
263
Specifying the Display Start Position
264
Sample Programs
268
21 Horizontal Sync Signal Counter
274
Horizontal Sync Signal Counter Configuration
274
Gate Control Register (Hscgt)
275
Hsync Counter (Hsc)
276
Example of Using the Horizontal Sync Signal
276
22 Instruction Sets
277
Outline of Instruction Sets
277
Instructions
278
List of Instruction Sets
279
Built-In Macro Instructions
281
23 Reserved Symbols for Assembler
282
System Register (Sysreg)
282
Data Buffer (Dbf)
282
Port Register
283
Register Files
284
Peripheral Hardware Register
286
Others
286
24 Electrical Characteristics
287
25 Package Drawings
289
26 Recommended Soldering Conditions
291
Appendix Development Tools
292
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