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NEC uPD98502 User Manual

NEC uPD98502 User Manual (595 pages)

Network Controller

Brand: NEC | Category: Controller | Size: 3.1 MB

Table of Contents

Table of Contents
7
Chapter 1 Introduction

23
- Features
  
  23
- Ordering Information
  
  23
- System Configuration
  
  24
- Block Diagram (Summary)
  
  25
- Block Diagram (Detail)
  
  26
  - R 4120A RISC Processor Core
    26
  - Ibus
    27
  - System Controller
    28
  - Block Diagram of System Controller
    28
  - ATM Cell Processor
    29
  - Block Diagram of ATM Cell Processor
    29
  - Ethernet Controller
    30
  - USB Controller
    31
  - Block Diagram of USB Controller
    31
  - PCI Controller
    32
  - Block Diagram of PCI Bus Controller
    32
- Pin Configuration (Bottom View)
  
  33
- Pin Function
  
  37
  - Power Supply
    37
  - System PLL Power Supply
    37
  - USB PLL Power Supply
    37
  - System Control Interface
    38
  - Memory Interface
    39
  - PCI Interface
    41
  - ATM Interface
    43
  - Ethernet Interface
    45
  - USB Interface
    46
  - UART Interface
    47
  - Micro Wire Interface
    47
  - Parallel Port Interface
    47
  - Boundary Scan Interface
    47
  - Open
    48
  - I.C.- Pull down
    48
  - Pull down with Resistor
    48
  - Pull up
    48
- I/O Register Map
  
  49
- Memory Map
  
  53
- Reset Configuration
  
  54
- Interrupts
  
  55
- Clock Control Unit
  
  56
  - Block Diagram of Clock Control Unit
    56
Chapter 2 4120A

57
- Overview for V R 4120A
  
  57
MIPS III Instruction Set Summary

66
Pipeline

84
Memory Management System

101
- Translation Lookaside Buffer (TLB)
  101
- Virtual Address Space
  102
- Virtual-To-Physical Address Translation
  102
- Bit Mode Virtual Address Translation
  104
- Bit Mode Virtual Address Translation
  105
- User Mode Address Space
  106
- Comparison of Useg and Xuseg
  107
- Supervisor Mode Address Space
  108
- Bit and 64-Bit Supervisor Mode Segments
  109
- Kernel Mode Address Space
  111
- Bit Kernel Mode Segments
  112
- Bit Kernel Mode Segments
  113
- Cacheability and Xkphys Address Space
  114
  - Physical Address Space
    116
  - System Control Coprocessor
    117
  - CP0 Registers and TLB
    117
- Format of a TLB Entry
  118
  - CP0 Registers
    119
- Index Register
  119
- Random Register
  119
- Entrylo0 and Entrylo1 Registers
  120
- Page Mask Register
  121
- Cache Algorithm
  121
- Mask Values and Page Sizes
  121
- Positions Indicated by Wired Register
  122
- Entryhi Register
  123
- Prid Register
  123
- Config Register Format
  124
- Lladdr Register
  125
- Taglo Register
  125
- Taghi Register
  125
- TLB Address Translation
  127
Exception Processing

129
- Exception Processing Operation
  129
- Precision of Exceptions
  130
- Exception Processing Registers
  130
- CP0 Exception Processing Registers
  130
- Context Register Format
  131
- Badvaddr Register Format
  132
- Count Register Format
  132
- Compare Register Format
  133
- Status Register Format
  134
- Status Register Diagnostic Status Field
  135
- Cause Register Format
  136
- Cause Register Exception Code Field
  137
- EPC Register Format
  138
- Watchlo Register Format
  139
- Watchhi Register Format
  139
- Xcontext Register Format
  140
- Parity Error Register Format
  140
- Cache Error Register Format
  141
- Errorepc Register Format
  141
  - Details of Exceptions
    142
- Bit Mode Exception Vector Base Addresses
  142
- Bit Mode Exception Vector Base Addresses
  143
- Exception Priority Order
  144
  - Exception Processing and Servicing Flowcharts
    158
- Common Exception Handling
  159
- TLB/XTLB Refill Exception Handling
  161
- Cold Reset Exception Handling
  163
- Soft Reset and NMI Exception Handling
  164
Initialization Interface

165
- Cold Reset
  165
- Soft Reset
  165
- R 4120A Processor Modes
  165
Cache Memory

168
- Memory Organization
  168
- Logical Hierarchy of Memory
  168
  - Cache Organization
    169
- Cache Support
  169
- Instruction Cache Line Format
  170
- Data Cache Line Format
  170
  - Cache Operations
    171
- Cache Data and Tag Organization
  171
  - Cache States
    172
  - Cache State Transition Diagrams
    173
- Data Cache State Diagram
  173
- Instruction Cache State Diagram
  173
  - Cache Data Integrity
    174
- Data Check Flow on Instruction Fetch
  174
- Data Check Flow on Load Operations
  174
- Data Check Flow on Store Operations
  175
- Data Check Flow on Index_Invalidate Operations
  175
- Data Check Flow on Index_Writeback_Invalidate Operations
  176
- Data Check Flow on Index_Load_Tag Operations
  176
- Data Check Flow on Index_Store_Tag Operations
  177
- Data Check Flow on Create_Dirty Operations
  177
- Data Check Flow on Hit_Invalidate Operations
  178
- Data Check Flow on Hit_Writeback_Invalidate Operations
  178
- Data Check Flow on Fill Operations
  179
- Data Check Flow on Hit_Writeback Operations
  179
- Writeback Flow
  180
- Refill Flow
  180
  - Manipulation of the Caches by an External Agent
    181
  - Writeback & Refill Flow
    181
CPU Core Interrupts

182
- Non-Maskable Interrupt (NMI)
  182
- Ordinary Interrupts
  182
- Software Interrupts Generated in CPU Core
  182
- Timer Interrupt
  182
- Non-Maskable Interrupt Signal
  182
- Asserting Interrupts
  183
- Hardware Interrupt Signals
  183
- Masking of Interrupt Request Signals
  184
Chapter 3 System Controller

185
- Overview
  
  185
  - CPU Interface
    185
  - Memory Interface
    185
  - IBUS Interface
    185
  - Uart
    186
  - Eeprom
    186
  - Timer
    186
  - Interrupt Controller
    186
  - DSU (Deadman's SW Unit)
    186
  - System Block Diagram
    187
  - Data Flow Diagram
    188
- Registers
  
  189
  - Register Map
    189
  - S_GMR (General Mode Register)
    191
  - S_GSR (General Status Register)
    191
  - S_ISR (Interrupt Status Register)
    192
  - S_IMR (Interrupt Mask Register)
    193
  - S_NSR (NMI Status Register)
    194
  - S_NER (NMI Enable Register)
    195
  - S_VER (Version Register)
    195
  - S_IOR (IO Port Register)
    196
  - S_WRCR (Warm Reset Control Register)
    197
  - S_WRSR (Warm Reset Status Register)
    198
  - S_PWCR (Power Control Register)
    199
  - S_PWSR (Power Status Register)
    200
- CPU Interface
  
  201
  - Overview
    201
  - Data Rate Control
    201
  - Burst Size Control
    201
  - Address Decoding
    201
  - Endian Conversion
    201
  - Endian Configuration Table
    202
  - Endian Translation Table in Endian Converter
    202
    
    I/O Performance
    203
- Memory Interface
  
  204
  - Memory Regions
    204
  - Overview
    204
  - External Pin Mapping
    205
    
    Memory Performance
    206
    
    Examples of Memory Performance (4-Word-Burst Access from IBUS Master)
    206
    
    RMMDR (ROM Mode Register)
    207
    
    RMATR (ROM Access Timing Register)
    207
    
    SDMDR (SDRAM Mode Register)
    209
    
    SDTSR (SDRAM Type Selection Register)
    210
    
    SDPTR (SDRAM Precharge Timing Register)
    211
    
    SDRMR (SDRAM Refresh Mode Register)
    211
    
    SDRCR (SDRAM Refresh Timer Count Register)
    212
    
    MBCR (Memory Bus Control Register)
    212
    
    Boot ROM
    213
    
    Boot-ROM Size Configuration at Reset
    213
  - Memory Signal Connections
    205
  - Command Sequence
    214
    
    Sdram
    216
  - SDRAM Word Order for Instruction-Cache Line-Fill
    217
    
    SDRAM Refresh
    219
    
    Memory-To-CPU Prefetch FIFO
    219
    
    CPU-To-Memory Write FIFO
    219
    
    SDRAM Memory Initialization
    220
- IBUS Interface
  
  221
- DSU (Deadman's SW Unit)
  
  224
  - DSUCLRR (DSU Clear Register)
    224
  - DSUCNTR (DSU Control Register)
    224
  - DSUSETR (DSU Time Set Register)
    224
  - Overview
    224
  - DSU Register Setting Flow
    225
  - DSUTIMR (DSU Elapsed Time Register)
    225
- Endian Mode Software Issues
  
  226
  - Overview
    226
  - Endian Modes
    226
  - Bit and Byte Order of Endian Modes
    227
  - Half-Word Data Array Example
    227
  - Word Data Array Example
    228
Chapter 4 Atm Cell Processor

229
- Overview
  
  229
  - Function Features
    229
  - Block Diagram of ATM Cell Processor
    230
  - ATM Cell Processing Operation Overview
    232
  - AAL-5 Sublayer and ATM Layer
    232
  - AAL-5 Sublayer and ATM Layer
    233
  - ATM Cell
    234
  - LLC Encapsulation
    235
- Memory Space
  
  236
- Interruption
  
  237
  - Shared Memory
    237
  - Work RAM and Register Space
    237
- Registers for ATM Cell Processing
  
  238
- Data Structure
  
  247
  - Tx Buffer Structure
    247
  - Tx Packet
    247
  - Tx Buffer Elements
    248
  - List of Tx Packet Attribute
    249
    
    Rx Pool Structure
    250
  - Tx Packet Descriptor
    249
  - Tx Buffer Descriptor/Link Pointer
    250
    
    Rx Pool Structure
    251
    
    Rx Pool Descriptor/Rx Buffer Directory/Rx Buffer Descriptor/Rx Link Pointer
    252
  - List of Rx Pool Attributes
    253
  - Rx Pool Descriptor
    253
  - Rx Buffer Descriptor/ Link Pointer
    254
- Initialization
  
  255
  - Before Starting RISC Core
    255
  - Transfer of F/W
    255
    
    After RISC Core's F/W Is Starting
    256
  - Instruction RAM and Instruction Cache
    256
- Commands
  
  257
  - Open_Channel Command
    258
  - Open_Channel Command and Indication
    258
  - Set_Link_Rate Command
    258
  - Close_Channel Command
    259
  - Tx_Ready Command
    260
  - Add_Buffers Command
    261
  - Indirect_Access Command
    262
- Operations
  
  262
  - Work RAM Usage
    262
  - Transmission Function
    263
  - Work RAM Usage
    263
  - Packet Info Structure
    265
  - Structure of the Transmit Queue
    265
  - Transmit Queue Packet Descriptor
    266
  - Tx VC Table
    267
  - Raw Cell with CRC-10
    269
  - Send Indication Format
    269
    
    Receiving Function
    270
  - LLC Encapsulation Format
    270
  - Receive VC Table
    271
  - Raw Cell Data Format
    273
  - Receive Indication Format
    274
  - Error Reporting Priorities
    275
    
    Mailbox
    276
  - Reception Errors that Can Occur During Packet Reception
    275
Chapter 5 Ethernet Controller

277
- Overview
  
  277
  - Features
    277
  - Block Diagram of Ethernet Controller Block
    277
  - Block Diagram of Ethernet Controller
    278
- Registers
  
  279
- Operation
  
  300
  - Buffer Structure for Ethernet Block
    300
    
    Buffer Descriptor Format
    301
  - Buffer Structure for Ethernet Controller Block
    300
  - Initialization
    300
  - Attribute for Transmit Descriptor
    301
    
    Frame Transmission
    302
  - Receive Descriptor Format
    301
  - Transmit Descriptor Format
    301
  - Attribute for Receive Descriptor
    302
  - Transmit Procedure
    304
    
    Frame Reception
    305
  - Receive Procedure
    306
    
    Address Filtering
    307
Chapter 6 Usb Controller

309
- Overview
  
  309
  - Features
    309
  - Internal Block Diagram
    310
  - USB Controller Internal Configuration
    310
- Registers
  
  311
- USB Attachment Sequence
  
  330
- Initialization
  
  331
  - Receive Pool Settings
    332
  - Transmit/Receive Mailbox Settings
    332
  - Mailbox Configuration
    333
- Data Transmit Function
  
  334
  - Division of Data into USB Packets
    334
  - Overview of Transmit Processing
    334
  - Tx Buffer Configuration
    334
  - Tx Buffer Configuration
    335
  - Configuration of Transmit Buffer Directory
    336
    
    Data Transmit Modes
    337
    
    R 4120A Processing at Data Transmitting
    338
  - Transmit Command Issue
    339
  - Transmit Status Register
    340
    
    USB Controller Processing at Data Transmitting
    341
  - USB Controller Transmit Operation Flow Chart
    341
    
    Tx Indication
    343
  - Transmit Indication Format
    343
- Data Receive Function
  
  344
  - Division of Data into USB Packets
    344
    
    Rx Buffer Configuration
    345
  - Overview of Receive Processing
    344
  - Receive Buffer Configuration
    345
  - Receive Descriptor Configuration
    346
    
    Receive Pool Settings
    347
  - Buffer Directory Addition Command
    347
    
    Data Receive Mode
    348
  - Data Receiving in Endpoint0, Endpoint6
    349
  - Endpoint2, Endpoint4 Receive Normal Mode
    349
  - Endpoint2, Endpoint4 Receive Assemble Mode
    350
  - Endpoint2, Endpoint4 Receive Separate Mode
    350
    
    R 4120A Receive Processing
    351
    
    USB Controller Receive Processing
    352
  - USB Controller Receive Operations (Normal Mode)
    352
  - USB Controller Receive Operations (Assemble Mode)
    354
  - USB Controller Receive Operation Sequence (Separate Mode)
    356
    
    Detection of Errors on USB
    358
  - USB Timing Errors
    358
    
    Rx Data Corruption on Isochronous Endpoint
    360
    
    Rx FIFO Overrun
    361
  - Example of Buffers Including Corrupted Data
    361
    
    Rx Indication
    362
    
    Receive Indication Format
    362
- Power Management
  
  364
  - Suspend
    364
  - Resume
    365
  - Remote Wake up
    366
  - Remote Wake up Sequence
    366
- Receiving SOF Packet
  
  367
- Loopback Mode
  
  368
  - Data Flow in Loopback Mode
    368
- Example of Connection
  
  369
Chapter 7 Pci Controller

370
- Overview
  
  370
  - The PCI Controller Block Diagram
    370
- Bus Bridge Functions
  
  371
- PCI Power Management Interface
  
  383
  - Power Management Event
    383
  - Power State
    383
  - Power Supply
    383
  - Power State Transition
    384
  - The Sequence of the Transition by Issues from PCI-Host
    384
  - The Sequence of the Transition by PME
    385
- Functions in Host-Mode
  
  386
- Registers
  
  390
- Information for Software
  
  411
  - NIC Mode
    411
  - Host Mode
    412
Chapter 8 Uart

414
- Overview
  
  414
- UART Block Diagram
  
  414
- Registers
  
  415
Chapter 9 Timer

424
- Overview
  
  424
- Block Diagram
  
  424
- Registers
  
  425
Chapter 10 Micro Wire

427
- Overview
  
  427
- Operations
  
  428
  - Data Read at the Power up Load
    428
  - Accessing to EEPROM
    428
  - EEPROM Initial Data
    428
  - EEPROM Command List
    428
- Registers
  
  429
  - Register Map
    429
  - ECCR (EEPROM Command Control Register)
    429
  - ERDR (EEPROM Read Data Register)
    429
  - MACAR1 (MAC Address Register 1)
    429
  - MACAR2 (MAC Address Register 2)
    429
  - MACAR3 (MAC Address Register 3)
    430
Appendix A Mips III Instruction Set Details

431
- Instruction Notation Conventions
  
  431
  - A-1 CPU Instruction Operation Notations
    432
- Load and Store Instructions
  
  433
  - A-2 Load and Store Common Functions
    433
- Jump and Branch Instructions
  
  434
  - A-3 Access Type Specifications for Loads/Stores
    434
- System Control Coprocessor (CP0) Instructions
  
  435
- CPU Instruction
  
  435
- CPU Instruction Opcode Bit Encoding
  
  588
Appendix B V R 4120A Coprocessor 0 Hazards

590
- B-2 Calculation Example of CP0 Hazard and Number of Instructions Inserted
  594

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