NEC V850E/IA1 mPD703116 Manuals

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NEC V850E/IA1 mPD703116 User Manual

NEC V850E/IA1 mPD703116 User Manual (832 pages)

32-Bit Single-Chip Microcontrollers

Brand: NEC | Category: Microcontrollers | Size: 4.63 MB

Table of Contents

Table of Contents
10
Chapter 1 Introduction

30
- Outline
  
  30
- Features
  
  32
- Applications
  
  33
- Ordering Information
  
  34
- Pin Configuration (Top View)
  
  35
- Configuration of Function Block
  
  37
  - Internal Block Diagram
    37
  - Internal Units
    38
- Differences between Products
  
  40
Chapter 2 Pin Functions

41
- List of Pin Functions
  
  41
- Pin Status
  
  47
- Description of Pin Functions
  
  48
- Types of Pin I/O Circuit and Connection of Unused Pins
  
  59
- Pin I/O Circuits
  
  61
Chapter 3 Cpu Function

62
- Features
  
  62
- CPU Register Set
  
  63
  - Program Register Set
    64
  - System Register Set
    65
- Operation Modes
  
  67
  - Operation Mode Specification
    68
- Address Space
  
  69
  - CPU Address Space
    69
  - Image
    70
  - Wrap-Around of CPU Address Space
    71
  - Memory Map
    72
  - Area
    73
  - External Memory Expansion
    78
  - Recommended Use of Address Space
    79
  - On-Chip Peripheral I/O Registers
    81
  - Programmable Peripheral I/O Registers
    92
  - Specific Registers
    109
  - System Wait Control Register (VSWC)
    109
  - Cautions
    109
Chapter 4 Bus Control Function

110
- Features
  
  110
- Bus Control Pins
  
  110
  - Pin Status During Internal ROM, Internal RAM, and On-Chip Peripheral I/O Access
    110
- Memory Block Function
  
  111
  - Chip Select Control Function
    112
- Bus Cycle Type Control Function
  
  115
- Bus Access
  
  116
  - Number of Access Clocks
    116
  - Bus Sizing Function
    117
  - Word Data Processing Format
    117
  - Bus Width
    118
- Wait Function
  
  124
- Idle State Insertion Function
  
  127
- Bus Hold Function
  
  128
  - Function Outline
    128
  - Bus Hold Procedure
    128
  - Operation in Power Save Mode
    129
  - Bus Hold Timing
    129
- Bus Priority Order
  
  130
- Boundary Operation Conditions
  
  131
  - Program Space
    131
  - Data Space
    131
Chapter 5 Memory Access Control Function

132
- SRAM, External ROM, External I/O Interface
  
  132
  - Features
    132
  - SRAM, External ROM, External I/O Access
    133
Chapter 6 Dma Functions (Dma Controller)

138
- Features
  
  138
- Configuration
  
  139
- Control Registers
  
  140
- DMA Bus States
  
  152
  - Types of Bus States
    152
  - DMAC Bus Cycle State Transition
    153
- Transfer Mode
  
  154
  - Single Transfer Mode
    154
  - Single-Step Transfer Mode
    156
  - Block Transfer Mode
    156
- Transfer Types
  
  157
  - Two-Cycle Transfer
    157
- Transfer Object
  
  158
  - Transfer Type and Transfer Object
    158
  - External Bus Cycles During DMA Transfer (Two-Cycle Transfer)
    159
- DMA Channel Priorities
  
  159
- Next Address Setting Function
  
  159
- DMA Transfer Start Factors
  
  161
- Forcible Interruption
  
  161
- DMA Transfer End
  
  162
- Forcible Termination
  
  162
- Precautions
  
  162
  - Interrupt Factors
    163
Chapter 7 Interrupt/Exception Processing Function

164
- Features
  
  164
- Non-Maskable Interrupt
  
  167
  - Operation
    168
  - Restore
    170
  - Non-Maskable Interrupt Status Flag (NP)
    171
  - Edge Detection Function
    171
- Maskable Interrupts
  
  172
  - Operation
    172
  - Restore
    174
  - Priorities of Maskable Interrupts
    175
  - Interrupt Control Register (Xxicn)
    179
  - Interrupt Mask Registers 0 to 3 (IMR0 to IMR3)
    182
  - In-Service Priority Register (ISPR)
    183
  - Maskable Interrupt Status Flag (ID)
    184
  - Interrupt Trigger Mode Selection
    185
- Software Exception
  
  194
  - Operation
    194
  - Restore
    195
  - Exception Status Flag (EP)
    196
- Exception Trap
  
  197
  - Illegal Opcode Definition
    197
  - Debug Trap
    199
- Multiple Interrupt Servicing Control
  
  201
- Interrupt Response Time
  
  202
- Periods in Which Interrupts Are Not Acknowledged
  
  204
Chapter 8 Clock Generation Function

205
- Features
  
  205
- Configuration
  
  205
- Input Clock Selection
  
  206
  - Direct Mode
    206
  - PLL Mode
    206
  - Peripheral Command Register (PHCMD)
    207
  - Clock Control Register (CKC)
    208
  - Peripheral Status Register (PHS)
    210
- PLL Lockup
  
  211
- Power Save Control
  
  212
  - Overview
    212
  - Control Registers
    215
  - HALT Mode
    218
  - IDLE Mode
    220
  - Software STOP Mode
    222
- Securing Oscillation Stabilization Time
  
  224
  - Oscillation Stabilization Time Security Specification
    224
  - Time Base Counter (TBC)
    225
Chapter 9 Timer/Counter Function (Real-Time Pulse Unit)

226
- Timer 0
  
  226
  - Features (Timer 0)
    226
  - Function Overview (Timer 0)
    227
  - Basic Configuration
    228
  - Control Registers
    234
  - Operation
    258
  - Operation Timing
    289
- Timer 1
  
  298
  - Features (Timer 1)
    298
  - Function Overview (Timer 1)
    298
  - Basic Configuration
    300
  - Control Registers
    307
  - Operation
    318
  - Supplementary Description of Internal Operation
    330
- Timer 2
  
  334
  - Features (Timer 2)
    334
  - Function Overview (Timer 2)
    334
  - Basic Configuration
    336
  - Control Registers
    343
  - Operation
    359
- Timer 3
  
  377
  - Features (Timer 3)
    377
  - Function Overview (Timer 3)
    377
  - Basic Configuration
    378
  - Control Registers
    383
  - Operation
    389
  - Application Examples
    396
  - Precautions
    402
- Timer 4
  
  403
  - Features (Timer 4)
    403
  - Function Overview (Timer 4)
    403
  - Basic Configuration
    404
  - Control Register
    408
  - Operation
    409
  - Application Example
    411
  - Precautions
    411
- Timer Connection Function
  
  412
  - Overview
    412
  - Control Register
    413
Chapter 10 Serial Interface Function

414
- Features
  
  414
- Asynchronous Serial Interface 0 (UART0)
  
  415
  - Features
    415
  - Configuration
    416
  - Control Registers
    418
  - Interrupt Requests
    425
  - Operation
    426
  - Dedicated Baud Rate Generator 0 (BRG0)
    438
  - Precautions
    445
- Asynchronous Serial Interfaces 1, 2 (UART1, UART2)
  
  446
  - Features
    446
  - Configuration
    447
  - Control Registers
    449
  - Interrupt Requests
    458
  - Operation
    459
  - Synchronous Mode
    469
  - Dedicated Baud Rate Generators 1, 2 (BRG1, BRG2)
    474
- Clocked Serial Interfaces 0, 1 (CSI0, CSI1)
  
  482
  - Features
    482
  - Configuration
    483
  - Control Registers
    486
  - Operation
    500
  - Output Pins
    515
  - Dedicated Baud Rate Generator 3 (BRG3)
    516
Chapter 11 Fcan Controller

520
- Function Overview
  
  520
- Configuration
  
  521
- Configuration of Messages and Buffers
  
  523
- Time Stamp Function
  
  524
- Message Processing
  
  527
- Mask Function
  
  528
- Protocol
  
  530
  - Protocol Mode Function
    530
  - Message Formats
    531
- Functions
  
  540
  - Determination of Bus Priority
    540
  - Bit Stuffing
    540
  - Multi-Master
    540
  - Multi-Cast
    540
  - CAN Sleep Mode/Can Stop Mode Function
    541
  - Error Control Function
    541
  - Baud Rate Control Function
    544
- Cautions on Bit Set/Clear Function
  
  547
- Control Registers
  
  549
- Operations
  
  601
  - Initialization Processing
    601
  - Transmit Setting
    612
  - Receive Setting
    613
  - CAN Sleep Mode
    614
  - CAN Stop Mode
    615
- Rules for Correct Setting of Baud Rate
  
  617
- Prioritization of Message Buffers During Receive Comparison
  
  620
  - Reception of Data Frames
    620
  - Reception of Remote Frames
    621
- Ensuring Data Consistency
  
  622
  - Sequential Data Read
    622
  - Burst Read Mode
    623
- Interrupt Conditions
  
  624
  - Interrupts that Are Generated for FCAN Controller
    624
  - Interrupts that Are Generated for Global CAN Interface
    624
- How to Shut down FCAN Controller
  
  625
- Cautions on Use
  
  626
CHAPTER 12 NBD FUNCTION ( Μ Μ Μ Μ PD70F3116)

627
- Overview
  
  627
- NBD Function Register Map
  
  628
- NBD Function Protocol
  
  629
- NBD Function
  
  632
- Control Registers
  
  637
- Restrictions on NBD
  
  640
- Initialization Required for DMA (2 Channels)
  
  641
Chapter 13 A/D Converter

645
- Features
  
  645
- Configuration
  
  645
- Control Registers
  
  649
- Interrupt Requests
  
  658
- A/D Converter Operation
  
  659
  - A/D Converter Basic Operation
    659
  - Operation Modes and Trigger Modes
    660
- Operation in A/D Trigger Mode
  
  663
  - Operation in Select Mode
    663
  - Operation in Scan Mode
    664
- Operation in A/D Trigger Polling Mode
  
  665
  - Operation in Select Mode
    665
  - Operation in Scan Mode
    666
- Operation in Timer Trigger Mode
  
  667
  - Operation in Select Mode
    667
  - Operation in Scan Mode
    668
- Operation in External Trigger Mode
  
  669
  - Operation in Select Mode
    669
  - Operation in Scan Mode
    670
- Precautions on Operation
  
  671
- How to Read A/D Converter Characteristics Table
  
  673
Chapter 14 Port Functions

677
- Features
  
  677
- Basic Configuration of Ports
  
  677
- Pin Functions of each Port
  
  692
  - Port 0
    692
  - Port 1
    693
  - Port 2
    696
  - Port 3
    699
  - Port 4
    701
  - Port DH
    703
  - Port DL
    705
  - Port CS
    707
  - Port CT
    709
  - Port CM
    711
- Noise Eliminator
  
  713
  - Interrupt Pins
    713
  - Timer 10, Timer 11, Timer 3 Input Pins
    714
  - Timer 2 Input Pins
    718
Chapter 15 Reset Function

721
- Features
  
  721
- Pin Functions
  
  721
- Initialization
  
  723
CHAPTER 16 FLASH MEMORY ( Μ Μ Μ Μ PD70F3116)

729
- Features
  
  729
- Writing by Flash Programmer
  
  729
- Programming Environment
  
  731
- Communication Mode
  
  731
- Pin Connection
  
  733
  - VPP Pin
    733
  - Serial Interface Pin
    733
  - RESET Pin
    735
  - NMI Pin
    735
  - MODE0 to MODE2 Pins
    735
  - Port Pins
    735
  - Other Signal Pins
    735
  - Power Supply
    736
- Programming Method
  
  736
  - Flash Memory Control
    736
  - Flash Memory Programming Mode
    737
  - Selection of Communication Mode
    737
  - Communication Commands
    738
- Flash Memory Programming by Self-Programming
  
  739
  - Outline of Self-Programming
    739
  - Self-Programming Function
    740
  - Outline of Self-Programming Interface
    740
  - Hardware Environment
    741
  - Software Environment
    743
  - Self-Programming Function Number
    744
  - Calling Parameters
    745
  - Contents of RAM Parameters
    746
  - Errors During Self-Programming
    747
  - Flash Information
    747
  - Area Number
    748
  - Flash Programming Mode Control Register (FLPMC)
    749
  - Calling Device Internal Processing
    751
  - Erasing Flash Memory Flow
    754
  - Continuous Writing Flow
    755
  - Internal Verify Flow
    756
  - Acquiring Flash Information Flow
    757
  - Self-Programming Library
    758
- How to Distinguish Flash Memory and Mask ROM Versions
  
  760

Advertisement

NEC V850E/IA1 mPD703116 User Manual

NEC V850E/IA1 mPD703116 User Manual (826 pages)

32-Bit Single-Chip Microcontrollers

Brand: NEC | Category: Microcontrollers | Size: 4.59 MB

Table of Contents

Table of Contents
9
Chapter 1 Introduction

18
- Outline
  18
- Features
  21
- Applications
  23
- Ordering Information
  23
- Pin Configuration (Top View)
  24
- Configuration of Function Block
  26
- Internal Block Diagram
  26
- Internal Units
  27
- Differences between Products
  29
Chapter 2 Pin Functions

30
- List of Pin Functions
  30
- Pin Status
  36
- Description of Pin Functions
  37
- Types of Pin I/O Circuit and Connection of Unused Pins
  45
- Pin I/O Circuits
  47
Chapter 3 Cpu Function

48
- Features
  48
- CPU Register Set
  49
- Program Register Set
  50
- System Register Set
  51
- Operation Modes
  57
- Operation Mode Specification
  58
- Address Space
  59
- CPU Address Space
  59
- Image
  60
- Wrap-Around of CPU Address Space
  61
- Memory Map
  62
- Area
  63
- External Memory Expansion
  67
- Recommended Use of Address Space
  68
- On-Chip Peripheral I/O Registers
  70
- Programmable Peripheral I/O Registers
  81
- Specific Registers
  98
- System Wait Control Register (VSWC)
  98
- Cautions
  98
Chapter 4 Bus Control Function

100
- Features
  100
- Bus Control Pins
  100
- Pin Status During Internal ROM, Internal RAM, and On-Chip Peripheral I/O Access
  100
- Memory Block Function
  101
- Chip Select Control Function
  102
- Bus Cycle Type Control Function
  105
- Bus Access
  106
- Number of Access Clocks
  106
- Bus Sizing Function
  107
- Word Data Processing Format
  107
- Bus Width
  108
- Wait Function
  114
- Programmable Wait Function
  114
- External Wait Function
  116
- Relationship between Programmable Wait and External Wait
  116
- Idle State Insertion Function
  117
- Bus Hold Function
  118
- Function Outline
  118
- Bus Hold Procedure
  118
- Operation in Power Save Mode
  119
- Bus Hold Timing
  119
- Bus Priority Order
  120
- Boundary Operation Conditions
  120
- Program Space
  120
- Data Space
  120
Chapter 5 Memory Access Control Function

121
- SRAM, External ROM, External I/O Interface
  121
- Features
  121
- SRAM, External ROM, External I/O Access
  122
Chapter 6 Dma Functions (Dma Controller)

127
- Features
  127
- Configuration
  128
- Control Registers
  129
- DMA Source Address Registers 0 to 3 (DSA0 to DSA3)
  129
- DMA Destination Address Registers 0 to 3 (DDA0 to DDA3)
  131
- DMA Transfer Count Registers 0 to 3 (DBC0 to DBC3)
  133
- DMA Addressing Control Registers 0 to 3 (DADC0 to DADC3)
  134
- DMA Channel Control Registers 0 to 3 (DCHC0 to DCHC3)
  136
- DMA Disable Status Register (DDIS)
  138
- DMA Restart Register (DRST)
  138
- DMA Trigger Factor Registers 0 to 3 (DTFR0 to DTFR3)
  139
- Transfer Mode
  142
- Single Transfer Mode
  142
- Single-Step Transfer Mode
  144
- Block Transfer Mode
  145
- Transfer Types
  145
- Two-Cycle Transfer
  145
- Transfer Target
  146
- Transfer Type and Transfer Target
  146
- External Bus Cycles During DMA Transfer (Two-Cycle Transfer)
  147
- DMA Channel Priorities
  147
- Next Address Setting Function
  147
- DMA Transfer Start Factors
  149
- Forcible Interruption
  150
- DMA Transfer End
  150
- Forcible Termination
  151
- Restriction Related to DMA Transfer Forcible Termination
  152
- Times Related to DMA Transfer
  153
- Precautions
  154
- Interrupt Factors
  155
Chapter 7 Interrupt/Exception Processing Function

156
- Features
  156
- Non-Maskable Interrupt
  160
- Operation
  161
- Restore
  163
- Non-Maskable Interrupt Status Flag (NP)
  164
- Edge Detection Function
  164
- Maskable Interrupts
  165
- Operation
  165
- Restore
  167
- Priorities of Maskable Interrupts
  168
- Interrupt Control Register (Xxicn)
  172
- Interrupt Mask Registers 0 to 3 (IMR0 to IMR3)
  175
- In-Service Priority Register (ISPR)
  176
- Maskable Interrupt Status Flag (ID)
  177
- Interrupt Trigger Mode Selection
  177
- Software Exception
  186
- Operation
  186
- Restore
  187
- Exception Status Flag (EP)
  188
- Exception Trap
  189
- Illegal Opcode Definition
  189
- Debug Trap
  191
- Multiple Interrupt Servicing Control
  193
- Interrupt Response Time
  194
- Periods in Which CPU Does Not Acknowledge Interrupts
  196
Chapter 8 Clock Generation Function

197
- Features
  197
- Configuration
  197
- Input Clock Selection
  198
- Direct Mode
  198
- PLL Mode
  198
- Peripheral Command Register (PHCMD)
  199
- Clock Control Register (CKC)
  200
- Peripheral Status Register (PHS)
  202
- PLL Lockup
  203
- Power Save Control
  204
- Overview
  204
- Control Registers
  207
- HALT Mode
  210
- IDLE Mode
  212
- Software STOP Mode
  214
- Securing Oscillation Stabilization Time
  216
- Oscillation Stabilization Time Security Specification
  216
- Time Base Counter (TBC)
  217
Chapter 9 Timer/Counter Function

218
- Timer 0
  218
- Features (Timer 0)
  218
- Function Overview (Timer 0)
  219
- Basic Configuration
  220
- Control Registers
  226
- Operation
  250
- Operation Timing
  284
- Timer 1
  293
- Features (Timer 1)
  293
- Function Overview (Timer 1)
  293
- Basic Configuration
  295
- Control Registers
  299
- Operation
  313
- Supplementary Description of Internal Operation
  323
- Timer 2
  326
- Features (Timer 2)
  326
- Function Overview (Timer 2)
  326
- Basic Configuration
  328
- Control Registers
  335
- Operation
  352
- PWM Output Operation When Timer 2 Operates in Compare Mode
  370
- Timer 3
  373
- Features (Timer 3)
  373
- Function Overview (Timer 3)
  373
- Basic Configuration
  374
- Control Registers
  379
- Operation
  385
- Application Examples
  392
- Precautions
  398
- Timer 4
  399
- Features (Timer 4)
  399
- Function Overview (Timer 4)
  399
- Basic Configuration
  400
- Control Register
  404
- Operation
  405
- Application Example
  407
- Precautions
  407
- Timer Connection Function
  408
- Overview
  408
- Control Register
  409
Chapter 10 Serial Interface Function

410
- Features
  410
- Asynchronous Serial Interface 0 (UART0)
  411
- Features
  411
- Configuration
  412
- Control Registers
  414
- Interrupt Requests
  421
- Operation
  422
- Dedicated Baud Rate Generator 0 (BRG0)
  434
- Precautions
  441
- Asynchronous Serial Interfaces 1, 2 (UART1, UART2)
  442
- Features
  442
- Configuration
  443
- Control Registers
  445
- Interrupt Requests
  454
- Operation
  455
- Synchronous Mode
  464
- Dedicated Baud Rate Generators 1, 2 (BRG1, BRG2)
  469
- Clocked Serial Interfaces 0, 1 (CSI0, CSI1)
  477
- Features
  477
- Configuration
  477
- Control Registers
  479
- Operation
  493
- Output Pins
  508
- Dedicated Baud Rate Generator 3 (BRG3)
  509
Chapter 11 Fcan Controller

513
- Function Overview
  513
- Configuration
  514
- Configuration of Messages and Buffers
  516
- Time Stamp Function
  517
- Message Processing
  520
- Message Transmission
  520
- Message Reception
  522
- Mask Function
  523
- Protocol
  525
- Protocol Mode Function
  525
- Message Formats
  526
- Functions
  535
- Determination of Bus Priority
  535
- Bit Stuffing
  535
- Multi-Master
  535
- Multi-Cast
  535
- CAN Sleep Mode/Can Stop Mode Function
  536
- Error Control Function
  536
- Baud Rate Control Function
  539
- Cautions on Bit Set/Clear Function
  542
- Control Registers
  544
- Operations
  596
- Initialization Processing
  596
- Transmit Setting
  609
- Receive Setting
  610
- CAN Sleep Mode
  612
- CAN Stop Mode
  613
- Rules for Correct Setting of Baud Rate
  615
- Ensuring Data Consistency
  619
- Sequential Data Read
  619
- Burst Read Mode
  620
- Interrupt Conditions
  621
- Interrupts that Are Generated for FCAN Controller
  621
- Interrupts that Are Generated for Global CAN Interface
  621
- How to Shut down FCAN Controller
  622
- Cautions on Use
  623
Chapter 12 Nbd Function

625
- Pd70F3116)
  625
- Overview
  625
- NBD Function Register Map
  626
- NBD Function Protocol
  627
- NBD Function
  630
- RAM Monitoring, Accessing NBD Space
  630
- Event Detection Function
  632
- Chip ID Registers (TID0 to TID2)
  633
- Control Registers
  634
- Restrictions on NBD
  637
- General Restrictions
  637
- Restrictions Related to Read or Write of RAM by NBD
  637
- Restrictions Related to NBD Event Trigger Function
  637
- How to Detect Termination of DMA Initialization Via NBD Tool
  637
- Initialization Required for DMA (2 Channels)
  638
Chapter 13 A/D Converter

642
- Features
  642
- Configuration
  642
- Control Registers
  646
- Interrupt Requests
  655
- A/D Converter Operation
  656
- A/D Converter Basic Operation
  656
- Operation Modes and Trigger Modes
  657
- Operation in A/D Trigger Mode
  660
- Operation in Select Mode
  660
- Operation in Scan Mode
  661
- Operation in A/D Trigger Polling Mode
  662
- Operation in Select Mode
  662
- Operation in Scan Mode
  663
- Operation in Timer Trigger Mode
  664
- Operation in Select Mode
  664
- Operation in Scan Mode
  665
- Operation in External Trigger Mode
  666
- Operation in Select Mode
  666
- Operation in Scan Mode
  667
- Precautions on Operation
  668
- Stopping A/D Conversion Operation
  668
- Trigger Input During A/D Conversion Operation
  668
- External or Timer Trigger Interval
  668
- Operation in Standby Modes
  668
- Compare Match Interrupt in Timer Trigger Mode
  669
- Timing that Makes the A/D Conversion Result Undefined
  669
- How to Read A/D Converter Characteristics Table
  670
Chapter 14 Port Functions

674
- Features
  674
- Basic Configuration of Ports
  674
- Pin Functions of each Port
  689
- Port 0
  689
- Port 1
  690
- Port 2
  693
- Port 3
  696
- Port 4
  698
- Port DH
  700
- Port DL
  702
- Port CS
  704
- Port CT
  706
- Port CM
  708
- Operation of Port Function
  710
- Writing to I/O Port
  710
- Reading from I/O Port
  710
- Output Status of Alternate Function in Control Mode
  710
- Noise Eliminator
  711
- Interrupt Pins
  711
- Timer 10, Timer 11, Timer 3 Input Pins
  712
- Timer 2 Input Pins
  716
Chapter 15 Reset Function

719
- Features
  719
- Pin Functions
  719
- Initialization
  721
Chapter 16 Flash Memory

727
- Pd70F3116)
  727
- Features
  727
- Writing by Flash Programmer
  727
- Programming Environment
  729
- Communication Mode
  729
- Pin Connection
  731
- VPP Pin
  731
- Serial Interface Pin
  731
- RESET Pin
  733
- NMI Pin
  733
- MODE0 to MODE2 Pins
  733
- Port Pins
  733
- Other Signal Pins
  733
- Power Supply
  734
- Programming Method
  734
- Flash Memory Control
  734
- Flash Memory Programming Mode
  735
- Selection of Communication Mode
  735
- Communication Commands
  736
- Flash Memory Programming by Self-Programming
  737
- Outline of Self-Programming
  737
- Self-Programming Function
  738
- Outline of Self-Programming Interface
  738
- Hardware Environment
  739
- Software Environment
  741
- Self-Programming Function Number
  742
- Calling Parameters
  743
- Contents of RAM Parameters
  744
- Errors During Self-Programming
  745
- Flash Information
  745
- Area Number
  746
- Flash Programming Mode Control Register (FLPMC)
  747
- Calling Device Internal Processing
  749
- Erasing Flash Memory Flow
  752
- Continuous Writing Flow
  753
- Internal Verify Flow
  754
- Acquiring Flash Information Flow
  755
- Self-Programming Library
  756
- How to Distinguish Flash Memory and Mask ROM Versions
  758

NEC V850E/IA1 mPD703116 User Manual

NEC V850E/IA1 mPD703116 User Manual (692 pages)

V850E/IA2 32-Bit Single-Chip Microcontrollers

Brand: NEC | Category: Microcontrollers | Size: 4.05 MB

Table of Contents

Table of Contents
9
Chapter 1 Introduction

17
- Outline
  17
- Features
  19
- Applications
  21
- Ordering Information
  21
- Pin Configuration (Top View)
  22
- Configuration of Function Block
  25
- Internal Block Diagram
  25
- Internal Units
  26
Chapter 2 Pin Functions

28
- List of Pin Functions
  28
- Pin Status
  33
- Description of Pin Functions
  34
- Types of Pin I/O Circuits and Connection of Unused Pins
  43
- Pin I/O Circuits
  45
Chapter 3 Cpu Function

46
- Features
  46
- CPU Register Set
  47
- Program Register Set
  48
- System Register Set
  49
- Operation Modes
  55
- Operation Mode Specification
  56
- Address Space
  57
- CPU Address Space
  57
- Image
  58
- Wrap-Around of CPU Address Space
  59
- Memory Map
  60
- Area
  61
- External Memory Expansion
  65
- Recommended Use of Address Space
  66
- On-Chip Peripheral I/O Registers
  68
- Specific Registers
  78
- System Wait Control Register (VSWC)
  78
- Cautions
  78
Chapter 4 Bus Control Function

80
- Features
  80
- Bus Control Pins
  80
- Pin Status During Internal ROM, Internal RAM, and On-Chip Peripheral I/O Access
  80
- Memory Block Function
  81
- Chip Select Control Function
  82
- Bus Cycle Type Control Function
  85
- Bus Access
  86
- Number of Access Clocks
  86
- Bus Sizing Function
  87
- Bus Width
  88
- Wait Function
  94
- Programmable Wait Function
  94
- External Wait Function
  96
- Relationship between Programmable Wait and External Wait
  96
- Idle State Insertion Function
  97
- Bus Priority Order
  98
- Boundary Operation Conditions
  99
- Program Space
  99
- Data Space
  99
Chapter 5 Memory Access Control Function

100
- SRAM, External ROM, External I/O Interface
  100
- Features
  100
- SRAM, External ROM, External I/O Access
  101
Chapter 6 Dma Functions (Dma Controller)

105
- Features
  105
- Configuration
  106
- Control Registers
  107
- DMA Source Address Registers 0 to 3 (DSA0 to DSA3)
  107
- DMA Destination Address Registers 0 to 3 (DDA0 to DDA3)
  109
- DMA Transfer Count Registers 0 to 3 (DBC0 to DBC3)
  111
- DMA Addressing Control Registers 0 to 3 (DADC0 to DADC3)
  112
- DMA Channel Control Registers 0 to 3 (DCHC0 to DCHC3)
  114
- DMA Disable Status Register (DDIS)
  116
- DMA Restart Register (DRST)
  116
- DMA Trigger Factor Registers 0 to 3 (DTFR0 to DTFR3)
  117
- Transfer Modes
  120
- Single Transfer Mode
  120
- Single-Step Transfer Mode
  122
- Block Transfer Mode
  123
- Transfer Types
  123
- Two-Cycle Transfer
  123
- Transfer Target
  124
- Transfer Type and Transfer Target
  124
- External Bus Cycles During DMA Transfer (Two-Cycle Transfer)
  125
- DMA Channel Priorities
  125
- Next Address Setting Function
  125
- DMA Transfer Start Factors
  127
- Forcible Suspension
  128
- DMA Transfer End
  128
- Forcible Termination
  129
- Restrictions on Forcible Termination of DMA Transfer
  130
- Time Required for DMA Transfer
  131
- Cautions
  132
Chapter 7 Interrupt/Exception Processing Function

134
- Features
  134
- Non-Maskable Interrupt
  138
- Operation
  139
- Restore
  141
- Non-Maskable Interrupt Status Flag (NP)
  142
- Edge Detection Function
  142
- Maskable Interrupts
  143
- Operation
  143
- Restore
  145
- Priorities of Maskable Interrupts
  146
- Interrupt Control Register (Xxicn)
  150
- Interrupt Mask Registers 0 to 3 (IMR0 to IMR3)
  153
- In-Service Priority Register (ISPR)
  154
- Maskable Interrupt Status Flag (ID)
  155
- Interrupt Trigger Mode Selection
  155
- Software Exception
  163
- Operation
  163
- Restore
  164
- Exception Status Flag (EP)
  165
- Exception Trap
  166
- Illegal Opcode Definition
  166
- Debug Trap
  168
- Multiple Interrupt Servicing Control
  170
- Interrupt Response Time
  172
- Periods in Which CPU Does Not Acknowledge Interrupts
  173
Chapter 8 Clock Generation Function

174
- Features
  174
- Configuration
  174
- Input Clock Selection
  175
- Direct Mode
  175
- PLL Mode
  175
- Peripheral Command Register (PHCMD)
  176
- Clock Control Register (CKC)
  177
- Peripheral Status Register (PHS)
  179
- PLL Lockup
  180
- Power Save Control
  181
- Overview
  181
- Control Registers
  184
- HALT Mode
  187
- IDLE Mode
  189
- Software STOP Mode
  191
- Securing Oscillation Stabilization Time
  193
- Oscillation Stabilization Time Security Specification
  193
- Time Base Counter (TBC)
  194
Chapter 9 Timer/Counter Function

195
- Timer 0
  195
- Features (Timer 0)
  195
- Function Overview (Timer 0)
  196
- Functions Added to V850E/IA2
  197
- Basic Configuration
  198
- Control Registers
  205
- Operation
  229
- Operation Timing
  285
- Timer 1
  294
- Features (Timer 1)
  294
- Function Overview (Timer 1)
  294
- Basic Configuration
  296
- Control Registers
  299
- Operation
  310
- Supplementary Description of Internal Operation
  319
- Timer 2
  322
- Features (Timer 2)
  322
- Function Overview (Timer 2)
  322
- Basic Configuration
  324
- Control Registers
  330
- Operation
  347
- PWM Output Operation in Timer 2 Compare Mode
  365
- Timer 3
  368
- Features (Timer 3)
  368
- Function Overview (Timer 3)
  368
- Function Added to V850E/IA2
  369
- Basic Configuration
  369
- Control Registers
  373
- Operation
  380
- Application Examples
  388
- Cautions
  394
- Timer 4
  395
- Features (Timer 4)
  395
- Function Overview (Timer 4)
  395
- Basic Configuration
  396
- Control Register
  400
- Operation
  401
- Application Example
  403
- Cautions
  403
- Timer Connection Function
  404
- Overview
  404
- Control Register
  405
Chapter 10 Serial Interface Function

406
- Features
  406
- Selecting UART1 or CSI1 Mode
  407
- Asynchronous Serial Interface 0 (UART0)
  408
- Features
  408
- Configuration
  409
- Control Registers
  411
- Interrupt Requests
  418
- Operation
  419
- Dedicated Baud Rate Generator 0 (BRG0)
  431
- Cautions
  438
- Asynchronous Serial Interface 1 (UART1)
  439
- Features
  439
- Configuration
  440
- Control Registers
  442
- Interrupt Requests
  451
- Operation
  452
- Synchronous Mode
  462
- Dedicated Baud Rate Generator 1 (BRG1)
  467
- Clocked Serial Interfaces 0, 1 (CSI0, CSI1)
  474
- Features
  474
- Configuration
  475
- Control Registers
  478
- Operation
  492
- Output Pins
  507
- Dedicated Baud Rate Generator 3 (BRG3)
  508

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