Motorola APX 1000 Detailed Service Manual page 867

Troubleshooting Tables: List of Board and IC Signals
Signal Name
cpld_ver3 CPLD version identifier
bit 3
cpld_ver2 CPLD version identifier
bit 2
cpld_ver1 CPLD version identifier
bit 1
cpld_ver0 CPLD version identifier
bit 0
board_id8 Controller Board ID bit 8
board_id7 Controller Board ID bit 7
board_id6 Controller Board ID bit 6
board_id5 Controller Board ID bit 5
board_id4 Controller Board ID bit 4
board_id3 Controller Board ID bit 3
board_id2 Controller Board ID bit 2
board_id1 Controller Board ID bit 1
board_id0 Controller Board ID bit 0
none OMAP GPIO1 deter-
mines default state of
some EMIFS pins.
Latched on rising edge
of PWR_ON_RESET.
Pulled low on PCB
none "Unused, defaults to
UART2.BCLK in reset
mode 0. Pulldown on
PCB
Table 7-10. Overall GPIO pin functions (Continued)
Pin
Description or
Ball #
(REG)
(REG)
(REG)
(REG)
H12
H13
G13
F13
D13
E13
C14
D14
F14
R19
"Y4
SW Initialized
Active
State
Direction
Register
Register
Register
Register
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
HW Reset
*
PU State Direction
Register
Register
Register
Register
Pul- Input
lup
Pul- Input
lup
Pul- Input
lup
Pul- Input
lup
Pul- Input
lup
Pul- Input
lup
Pul- Input
lup
Pul- Input
lup
Pul- Input
lup
Pull- 0 Input
down
None 0 Output
7-27
*
PU
or
PD
Pul-
lup
Pul-
lup
Pul-
lup
Pul-
lup
Pul-
lup
Pul-
lup
Pul-
lup
Pul-
lup
Pul-
lup
Pull-
down
None