Page 1: Disk Drives
MPF3xxxAH DISK DRIVES PRODUCT MANUAL C141-E106-01EN...
Page 2 5(9,6,215(&25' (GLWLRQ 'DWHSXEOLVKHG 5HYLVHGFRQWHQWV )HE 6SHFLILFDWLRQ1R&( (1 7KHFRQWHQWVRIWKLVPDQXDOLVVXEMHFWWRFKDQJH ZLWKRXWSULRUQRWLFH $OO5LJKWV5HVHUYHG &RS\ULJKW¤)8-,768/,0,7(' &((1...
Page 3 This page is intentionally left blank.
Page 4 MANUAL ORGANIZATION MPF3xxxAH • DEVICE OVERVIEW DISK DRIVES • DEVICE CONFIGURATION PRODUCT • INSTALLATION CONDITIONS MANUAL • THEORY OF DEVICE OPERATION (C141-E106) • INTERFACE <This manual> • OPERATIONS MPF3xxxAH • MAINTENANCE AND DIAGNOSIS DISK DRIVES • REMOVAL AND REPLACEMENT PROCEDURE MAINTENANCE MANUAL (C141-F044)
Page 5 This page is intentionally left blank.
Page 6: Chapter 1 Device Overview
PREFACE This manual describes the MPF3xxxAH series, a 3.5-inch hard disk drive with a BUILT-IN controller that is compatible with the ATA interface. This manual explains, in detail, how to incorporate the hard disk drives into user systems. This manual assumes that users have a basic knowledge of hard disk drives and their application in computer systems.
Page 7 Conventions for Alert Messages This manual uses the following conventions to show the alert messages. An alert message consists of an alert signal and alert statements. The alert signal consists of an alert symbol and a signal word or just a signal word.
Page 8 "Disk drive defects" refers to defects that involve adjustment, repair, or replacement. Fujitsu is not liable for any other disk drive defects, such as those caused by user misoperation or mishandling, inappropriate operating environments, defects in the power supply or cable, problems of the host system, or other causes outside the disk drive.
Page 9 This page is intentionally left blank.
Page 10: Table Of Contents
CONTENTS page CHAPTER 1 DEVICE OVERVIEW ..................1 - 1 Features ...........................1 - 1 1.1.1 Functions and performance ....................1 - 1 1.1.2 Adaptability ........................1 - 2 1.1.3 Interface...........................1 - 2 Device Specifications .......................1 - 4 1.2.1 Specifications summary....................1 - 4 1.2.2 Model and product number ....................1 - 5 Power Requirements......................1 - 5 Environmental Specifications...................1 - 8...
Page 11 3.4.2 Cable connector specifications..................3 - 9 3.4.3 Device connection ......................3 - 9 3.4.4 Power supply connector (CN1) ..................3 - 10 3.4.5 System configuration for Ultra DMA................3 - 10 Jumper Settings........................3 - 13 3.5.1 Location of setting jumpers ....................3 - 13 3.5.2 Factory default setting ......................3 - 14 3.5.3...
Page 12 CHAPTER 5 INTERFACE ....................5 - 1 Physical Interface......................5 - 2 5.1.1 Interface signals .......................5 - 2 5.1.2 Signal assignment on the connector .................5 - 3 Logical Interface ......................5 - 6 5.2.1 I/O registers ........................5 - 6 5.2.2 Command block registers ....................5 - 8 5.2.3 Control block registers .....................5 - 13 Host Commands.......................5 - 13...
Page 13 5.6.3 Ultra DMA data transfer ....................5 - 87 5.6.3.1 Initiating an Ultra DMA data in burst ................5 - 87 5.6.3.2 Ultra DMA data burst timing requirements ..............5 - 88 5.6.3.3 Sustained Ultra DMA data in burst ..................5 - 90 5.6.3.4 Host pausing an Ultra DMA data in burst.................5 - 91 5.6.3.5 Device terminating an Ultra DMA data in burst ...............5 - 92 5.6.3.6 Host terminating an Ultra DMA data in burst..............5 - 93 5.6.3.7 Initiating an Ultra DMA data out burst................5 - 94...
Page 14 FIGURES page Current fluctuation (Typ.) when power is turned on ............1 - 7 Disk drive outerview ......................2 - 1 1 drive system configuration.....................2 - 3 2 drives configuration ......................2 - 3 Dimensions ........................3 - 2 Handling cautions ......................3 - 3 Direction..........................3 - 4 Limitation of side-mounting.....................3 - 5 Mounting frame structure....................3 - 5...
Page 15 Protocol for command abort .....................5 - 69 WRITE SECTOR(S) command protocol ................5 - 70 Protocol for the command execution without data transfer..........5 - 71 Normal DMA data transfer ....................5 - 73 Ultra DMA termination with pull-up or pull-down ............5 - 84 PIO data transfer timing....................5 - 85 Multiword DMA data transfer timing (mode 2)..............5 - 86 5.10...
Page 16 7$%/(6 SDJH 6SHFLILFDWLRQV 0RGHOQDPHVDQGSURGXFWQXPEHUV &XUUHQWDQGSRZHUGLVVLSDWLRQ (QYLURQPHQWDOVSHFLILFDWLRQV $FRXVWLFQRLVHVSHFLILFDWLRQ 6KRFNDQGYLEUDWLRQVSHFLILFDWLRQ 6XUIDFHWHPSHUDWXUHPHDVXUHPHQWSRLQWVDQGVWDQGDUGYDOXHV &DEOHFRQQHFWRUVSHFLILFDWLRQV 6HOIFDOLEUDWLRQH[HFXWLRQWLPHFKDUW 7UDQVIHUUDWHRIHDFK]RQH ,QWHUIDFHVLJQDOV 6LJQDODVVLJQPHQWRQWKHLQWHUIDFHFRQQHFWRU ,2UHJLVWHUV &RPPDQGFRGHDQGSDUDPHWHUV ,QIRUPDWLRQWREHUHDGE\,'(17,)<'(9,&(FRPPDQG )HDWXUHVUHJLVWHUYDOXHVDQGVHWWDEOHPRGHV ...
Page 17 This page is intentionally left blank.
Page 18 &+$37(5 '(9,&(29(59,(: )HDWXUHV 'HYLFH6SHFLILFDWLRQV 3RZHU5HTXLUHPHQWV (QYLURQPHQWDO6SHFLILFDWLRQV $FRXVWLF1RLVH 6KRFNDQG9LEUDWLRQ 5HOLDELOLW\ (UURU5DWH 0HGLD'HIHFWV 2YHUYLHZ DQG IHDWXUHV DUH GHVFULEHG LQ WKLV FKDSWHU DQG VSHFLILFDWLRQV DQG SRZHU UHTXLUHPHQW DUH GHVFULEHG 7KH03)[[[$+ VHULHV DUH D LQFK KDUG GLVN GULYH ZLWK D EXLOWLQ $7$ FRQWUROOHU 7KH GLVN GULYH LV FRPSDFWDQGUHOLDEOH )HDWXUHV ...
Page 19: Adaptability
The disk drive can be used over a wide temperature range (5°C to 55°C). Low noise and vibration In Ready status, the noise of the disk drive is only about 3.7 bels (MPF3204AH, Typical Sound Power per ISO7779 and ISO9296).
Page 20 Error correction and retry by ECC If a recoverable error occurs, the disk drive itself attempts error recovery. The 40 bytes ECC has improved buffer error correction for correctable data errors. Write cache When the disk drive receives a write command, the disk drive posts the command completion at completion of transferring data to the data buffer completion of writing to the disk media.
Page 21 'HYLFH6SHFLILFDWLRQV 6SHFLILFDWLRQVVXPPDU\ 7DEOHVKRZVWKHVSHFLILFDWLRQVRIWKHGLVNGULYH 7DEOH 6SHFLILFDWLRQV 03)$+ 03)$+ 03)$+ )RUPDWWHG&DSDFLW\ *% *% *% 1XPEHURI'LVNV 1XPEHURI+HDGV 1XPEHURI&\OLQGHUV 8VHU$OWHUQDWH 6$ %\WHVSHU6HFWRU 5HFRUGLQJ0HWKRG ((350/ 7UDFN'HQVLW\ 73, %LW'HQVLW\ %3, 5RWDWLRQDO6SHHG USP $YHUDJH/DWHQF\ PV 3RVLWLRQLQJWLPH ‡0LQLPXP PVW\SLFDO ‡$YHUDJH 5HDGPVW\SLFDO:ULWHPVW\SLFDO ‡0D[LPXP 5HDGPVW\SLFDO:ULWHPVW\SLFDO 6WDUW6WRSWLPH ‡6WDUWUSPWR'ULYH5HDG 7\SLFDOVHF 0D[LPXPVHF ‡6WRSDW3RZHU'RZQ 7\SLFDOVHF 0D[LPXPVHF...
Page 22: Model And Product Number
(user area) Screw MPF3102AH 10.24 GB No. 6-32UNC CA05431-B321 — MPF3153AH 15.37 GB No. 6-32UNC CA05431-B331 — MPF3204AH 20.49 GB No. 6-32UNC CA05431-B341 — Power Requirements Input Voltage • + 5 V ±5 % • + 12 V ±8 %...
Page 23 &XUUHQW5HTXLUHPHQWVDQG3RZHU'LVVLSDWLRQ 7DEOHOLVWVWKHFXUUHQWDQGSRZHUGLVVLSDWLRQ 7DEOH &XUUHQWDQGSRZHUGLVVLSDWLRQ 7\SLFDO506FXUUHQW >P$@ 0RGHRI2SHUDWLRQ 7\SLFDO3RZHU >ZDWWV@ 9 9 0RGHO $+ $+ $+ 0RGHOV $+ $+ $+ 6SLQXS WR WR WR WR SHDN SHDN SHDN SHDN ,GOH5HDG\ 5:2Q7UDFN 6HHN5DQGRP 6WDQGE\ 6OHHS (QHUJ\HIILFLHQF\UDQN >ZDWW*%@ $ % % &XUUHQWLVW\SLFDOUPVH[FHSWIRUVSLQXS 3RZHUUHTXLUHPHQWVUHIOHFWQRPLQDOYDOXHVIRU9DQG9SRZHU ,GOHPRGHLVLQHIIHFWZKHQWKHGULYHLVQRWUHDGLQJZULWLQJVHHNLQJRUH[HFXWLQJDQ\FRPPDQGV$SRUWLRQRIWKH5:FLUF XLWU\LVSRZHUHGGRZQ WKHVSLQGOHPRWRULVXSWRVSHHGDQGWKH'ULYHUHDG\FRQGLWLRQH[LVWV...
Page 24 &XUUHQWIOXFWXDWLRQ7\SZKHQSRZHULVWXUQHGRQ )LJXUH &XUUHQWIOXFWXDWLRQ7\SZKHQSRZHULVWXUQHGRQ 3RZHURQRIIVHTXHQFH 7KHYROWDJHGHWHFWRUFLUFXLWPRQLWRUV9DQG97KHFLUFXLWGRHVQRWDOORZDZULWHVLJQDOLI HLWKHUYROWDJHLVDEQRUPDO7KLVSUHYHQWVGDWDIURPEHLQJGHVWUR\HGDQGHOLPLQDWHVWKHQHHGWREH FRQFHUQHGZLWKWKHSRZHURQRIIVHTXHQFH &((1 ...
Page 25: Environmental Specifications
Table 1.5 lists the acoustic noise specification. Table 1.5 Acoustic noise specification MPF3102AH Sound Power MPF3153AH Model per ISO 7779 and ISO9296 MPF3204AH (Typical at 1m) Idle mode (DRIVE READY) 3.7 bels Seek mode (Random) 4.3 bels Sound Pressure Idle mode (DRIVE READY)
Page 26: Shock And Vibration
Shock and Vibration Table 1.6 lists the shock and vibration specification. Table 1.6 Shock and vibration specification Vibration (swept sine, one octave per minute) • Operating 5 to 300 Hz, 0.5G-0-peak (without non-recovered errors) • Non-operating 5 to 400 Hz, 4G-0-peak (no damage) Shock (half-sine pulse, Operating) •...
Page 27: Error Rate
Service life In situations where management and handling are correct, the disk drive requires no overhaul for five years when the DE surface temperature is less than 48°C. When the DE surface temperature exceeds 48°C, the disk drives requires no overhaul for five years or 20,000 hours of operation, whichever occurs first.
Page 28: Chapter 2 Device Configuration
CHAPTER 2 DEVICE CONFIGURATION Device Configuration System Configuration Device Configuration Figure 2.1 shows the disk drive. The disk drive consists of a disk enclosure (DE), read/write preamplifier, and controller PCA. The disk enclosure contains the disk media, heads, spindle motors actuators, and a circulating air filter. Figure 2.1 Disk drive outerview C141-E106-01EN...
Page 29 The disks are rated at over 40,000 start/stop operations. MPF3102AH: 1 disks MPF3153AH: 2 disks MPF3204AH: 2 disks Head The heads are of the contact start/stop (CSS) type. The head touches the disk surface while the disk is not rotating and automatically lifts when the disk starts.
Page 30: System Configuration
System Configuration 2.2.1 ATA interface Figures 2.2 and 2.3 show the ATA interface system configuration. The drive has a 40-pin PC AT interface connector and supports the PIO transfer till 16.7 MB/s (PIO mode 4), the DMA transfer till 16.7 MB/s (Multiword DMA mode 2), and the ultra DMA transfer till 66.6 MB/s (Ultra DMA mode 4).
Page 31 ,03257$17 +$ KRVW DGDSWHU FRQVLVWV RI DGGUHVV GHFRGHU GULYHU DQG UHFHLYHU $7$ LV DQ DEEUHYLDWLRQ RI $7 DWWDFKPHQW 7KH GLVN GULYH LV FRQIRUPHGWRWKH$7$LQWHUIDFH $W KLJK VSHHG GDWD WUDQVIHU 3,2 PRGH PRGH '0$ PRGH RU XOWUD '0$ PRGH RFFXUUHQFH RI ULQJLQJ RU FURVVWDON RI WKH VLJQDO OLQHV$7EXVEHWZHHQWKH+$DQGWKHGLVNGULYHPD\EHDJUHDWFDXVH RI WKH REVWUXFWLRQ RI V\VWHP UHOLDELOLW\ 7KXV LW LV QHFHVVDU\ WKDW WKH FDSDFLWDQFH RI WKH VLJQDO OLQHV LQFOXGLQJ WKH +$ DQG FDEOH GRHV QRW...
Page 32: Chapter 3 Installation Conditions
CHAPTER 3 INSTALLATION CONDITIONS Dimensions Handling Cautions Mounting Cable Connections Jumper Settings Dimensions Figure 3.1 illustrates the dimensions of the disk drive and positions of the mounting screw holes. All dimensions are in mm. C141-E106-01EN 3 - 1...
Page 33 Figure 3.1 Dimensions 3 - 2 C141-E106-01EN...
Page 34 +DQGOLQJ&DXWLRQV 3OHDVHNHHSWKHIROORZLQJFDXWLRQVDQGKDQGOHWKH+''XQGHUWKHVDIHW\HQYLURQPHQW *HQHUDOQRWHV (6'PDW :ULVWVWUDS 8VHWKH:ULVWVWUDS 6KRFNDEVRUELQJPDW 3ODFHWKHVKRFNDEVRUELQJPDWRQWKH RSHUDWLRQWDEOHDQGSODFH(6'PDWRQLW 'RQRWKLW+''HDFKRWKHU 'RQRWVWDFNZKHQFDUU\LQJ 'RQRWSODFH+''YHUWLFDOO\ 'RQRWGURS WRDYRLGIDOOLQJGRZQ )LJXUH +DQGOLQJFDXWLRQV ,QVWDOODWLRQ 3OHDVHXVHWKHGULYHURIDORZLPSDFWZKHQ\RXXVHDQHOHFWULFGULYHU +''LVRFFDVLRQDOO\GDPDJHGE\WKHLPSDFWRIWKHGULYHU 3OHDVHREVHUYHWKHWLJKWHQLQJWRUTXHRIWKHVFUHZVWULFWO\ 81&±±±±±±±0D[1±P.J±FP 5HFRPPHQGHGHTXLSPHQWV &RQWHQWV 0RGHO 0DNHU :ULVWVWUDS -; 680,72020 (6'PDW '(6$6. &20.</( 6KRFN /RZVKRFNGULYHU 66 +,26 &((1 ...
Page 35: Mounting
Mounting Direction Figure 3.3 illustrates normal direction for the disk drive. The disk drives can be mounted in any direction. Horizontal mounting with the PCB facing down Figure 3.3 Direction Frame The disk enclosure (DE) body is connected to signal ground (SG) and the mounting frame is also connected to signal ground.
Page 36: Limitation Of Side-Mounting
Use these screw holes Do not use this screw holes Figure 3.4 Limitation of side-mounting Side surface mounting Bottom surface mounting Frame of system Frame of system cabinet cabinet 4.5 or less Screw Screw 5.0 or less Details of A Details of B Figure 3.5 Mounting frame structure...
Page 37: Surface Temperature Measurement Points
Ambient temperature The temperature conditions for a disk drive mounted in a cabinet refer to the ambient temperature at a point 3 cm from the disk drive. Pay attention to the air flow to prevent the DE surface temperature from exceeding 60°C. Provide air circulation in the cabinet such that the PCA side, in particular, receives sufficient cooling.
Page 38: Service Area
Service area Figure 3.7 shows how the drive must be accessed (service areas) during and after installation. - Mounting screw hole [Q side] - Mounting screw hole [P side] [R side] - Cable connection - Mounting screw hole - Mode setting switches Figure 3.7 Service area External magnetic fields...
Page 39 &DEOH&RQQHFWLRQV 'HYLFHFRQQHFWRU 7KH GLVN GULYH KDV WKH FRQQHFWRUV DQG WHUPLQDOV OLVWHG EHORZ IRU FRQQHFWLQJ H[WHUQDO GHYLFHV )LJXUHVKRZVWKHORFDWLRQVRIWKHVHFRQQHFWRUVDQGWHUPLQDOV 3RZHUVXSSO\FRQQHFWRU&1 $7$LQWHUIDFHFRQQHFWRU&1 3RZHUVXSSO\ FRQQHFWRU&1 0RGH 6HWWLQJ 3LQV LQWHUIDFH FRQQHFWRU )LJXUH &RQQHFWRUORFDWLRQV &((1...
Page 40 &DEOHFRQQHFWRUVSHFLILFDWLRQV 7DEOHOLVWVWKHUHFRPPHQGHGVSHFLILFDWLRQVIRUWKHFDEOHFRQQHFWRUVIRU+RVWV\VWHPWKDWGR QRWVXSSRUW8OWUD'0$PRGHVJUHDWHUWKDQPRGH )RU+RVWV\VWHPWKDWVXSSRUW8OWUD'0$PRGHVJUHDWHUWKDQPRGHLWLVUHFRPPHQGHGWRXVHWKH FRQGXFWRUFDEOHDVVHPEO\7KHFRQGXFWRUFDEOHDVVHPEO\LVPDQXIDFWXUHGE\$03RU0 7DEOH &DEOHFRQQHFWRUVSHFLILFDWLRQV 1DPH 0RGHO 0DQXIDFWXUHU &DEOHVRFNHW )&1%$8% )XMLWVX FORVHGHQGW\SH $7$LQWHUIDFHFDEOH SLQ&1 &DEOHVRFNHW )&1%$82 )XMLWVX WKURXJKHQGW\SH &DEOHVRFNHWKRXVLQJ 3RZHUVXSSO\FDEOH &1 &RQWDFW 1RWH 7KHFDEOHRIWZLVWHGSDLUVDQGQHLJKERULQJOLQHVHSDUDWHGLQGLYLGXDOO\LVQRWDOORZHGWRXVHIRU WKH KRVW LQWHUIDFH FDEOH ,W LV EHFDXVH WKDW WKH ORFDWLRQ RI VLJQDO OLQHV LQ WKHVH FDEOHV LV QRW IL[HGDQGVRWKHSUREOHPRQWKHFURVVWDONDPRQJVLJQDOOLQHVPD\RFFXU ,WLVUHFRPPHQGHGWRXVHWKHULEERQFDEOHIRU$7$LQWHUIDFHWKDWFDEOHOHQJWKLVOHVVWKDQ FPLQFKDQGFDEOHFDSDFLWDQFHLVOHVVWKDQSLFRIDUDG$OVRLWLVUHFRPPHQGHGWRXVH...
Page 41: Power Supply Connector (Cn1)
3.4.4 Power supply connector (CN1) Figure 3.10 shows the pin assignment of the power supply connector (CN1). +12VDC +12V RETURN +5V RETURN +5VDC (Viewed from cable side) Figure 3.10 Power supply connector pins (CN1) 3.4.5 System configuration for Ultra DMA Host system that support Ultra DMA transfer modes greater than mode 2 shall not share I/O ports.
Page 42: Cable Configuration
254.0 to 457.2 mm (10 to 18 inch) 127.0 to 304.8 mm 101.6 to 152.4 mm (5 to 12 inch) (4 to 6 inch) Pin 40 (Ground) open Pin 34 Pin 34 contact Pin 30 (Ground) (PDIAG-:CBLID- signal) Symbolizes Pin 34 Pin 26 (Ground) Conductor being cut Pin 24 (Ground)
Page 43: Cable Type Detection Using Cblid- Signal (Host Sensing The Condition Of The Cblid- Signal)
Host detected CBLID- above V Host detected CBLID- below V open PDIAG-: CBLID- conductor PDIAG-: CBLID- conductor Host Device 1 Device 0 Host Device 1 Device 0 with 40-conductor cable with 80-conductor cable Figure 3.12 Cable type detection using CBLID- signal (Host sensing the condition of the CBLID- signal) IDENTIFY DEVICE information IDENTIFY DEVICE information...
Page 44 -XPSHU6HWWLQJV /RFDWLRQRIVHWWLQJMXPSHUV )LJXUHVKRZVWKHORFDWLRQRIWKHMXPSHUVWRVHOHFWGULYHFRQILJXUDWLRQDQGIXQFWLRQV ,QWHUIDFH&RQQHFWRU '&3RZHU&RQQHFWRU )LJXUH -XPSHUORFDWLRQ &((1 ...
Page 45: Factory Default Setting
3.5.2 Factory default setting Figure 3.15 shows the default setting position at the factory. (Master device setting) DC Power Connector Interface Connector Figure 3.15 Factory default setting 3.5.3 Jumper configuration Device type Master device (device #0) or slave device (device #1) is selected. = shorted (a) Master device (b) Slave device...
Page 46: Jumper Setting Of Cable Select
CSEL connected to the interface cable selection can be done by the special interface cable. Figure 3.17 Jumper setting of Cable Select Figures 3.18 and 3.19 show examples of cable selection using unique interface cables. By connecting the CSEL of the master device to the CSEL Line (conductor) of the cable and connecting it to ground further, the CSEL is set to low level.
Page 47 No. of sectors MPF3102AH 4,092 MPF3153AH 4,092 MPF3204AH 4,092 (b) Slave present If the slave device does not use the Device Active/Slave Present (DASP–) signal to indicate its presence, the device is configured as a Master with slave present when the following jumper settings is applied.
Page 48: Chapter 4 Theory Of Device Operation
The DE contains the disks with an outer diameter of 95 mm. The MPF3102AH has 1 disk, and MPF3153AH and MPF3204AH have 2 disk. The head contacts the disk each time the disk rotation stops; the life of the disk is 40,000 contacts or more.
Page 49 +HDG )LJXUHVKRZVWKHUHDGZULWHKHDGVWUXFWXUHV7KH1XPHUDOVWRLQGLFDWHUHDGZULWHKHDGV 7KHVH KHDGV DUH UDLVHG IURP WKH GLVN VXUIDFH DV WKH VSLQGOH PRWRU DSSURDFKHV WKH UDWHG URWDWLRQ VSHHG 03)$70RGHO 6SLQGOH $FWXDWRU 03)$70RGHO 03)$70RGHO 6SLQGOH $FWXDWRU 6SLQGOH $FWXDWRU )LJXUH +HDGVWUXFWXUH 6SLQGOH 7KH VSLQGOH FRQVLVWV RI D GLVN VWDFN DVVHPEO\ DQG VSLQGOH PRWRU 7KH GLVN VWDFN DVVHPEO\ LV DFWLYDWHGE\WKHGLUHFWGULYHVHQVRUOHVV'&VSLQGOHPRWRUZKLFKKDVDVSHHGRIUSP7KH VSLQGOHLVFRQWUROOHGZLWKGHWHFWLQJD3+$6(VLJQDOJHQHUDWHGE\FRXQWHUHOHFWURPRWLYHYROWDJHRI WKH VSLQGOH PRWRU DW VWDUWLQJ $IWHU WKDW WKH URWDWLRQDO VSHHG LV NHSW ZLWK GHWHFWLQJ D VHUYR...
Page 50: Air Filter
4.2.5 Air filter There are two types of air filters: a breather filter and a circulation filter. The breather filter makes an air in and out of the DE to prevent unnecessary pressure around the spindle when the disk starts or stops rotating. When disk drives are transported under conditions where the air pressure changes a lot, filtered air is circulated in the DE.
Page 51 &LUFXLW&RQILJXUDWLRQ )LJXUHVKRZVWKHGLVNGULYHFLUFXLWFRQILJXUDWLRQ 5HDGZULWHFLUFXLW 7KHUHDGZULWH FLUFXLW FRQVLVWV RI WZR /6,V UHDGZULWH SUHDPSOLILHU 3UH$03 DQG UHDG FKDQQHO 5'& 7KH3UH$03FRQVLVWVRIWKHZULWHFXUUHQWVZLWFKFLUFXLWWKDWIORZVWKHZULWHFXUUHQWWRWKHKHDG FRLODQGWKHYROWDJHDPSOLILHUFLUFXLWWKDWDPSOLWXGHVWKHUHDGRXWSXWIURPWKHKHDG 7KH5'&LVWKHUHDGGHPRGXODWLRQFLUFXLWXVLQJWKH([WHQGHG3DUWLDO5HVSRQVH&ODVV(35 DQGFRQWDLQVWKH9LWHUELGHWHFWRUSURJUDPPDEOHORZSDVVILOWHUWDSDGDSWLYHGLJLWDO),5ILOWHU V\QWKHVL]HUDQGGDWDVHSDUDWRUFLUFXLWV7KH5'&DOVRFRQWDLQVWKHJURXSFRGHGUHFRUGLQJ *&5HQFRGHUDQGGHFRGHUDQGVHUYRGHPRGXODWLRQFLUFXLW 6HUYRFLUFXLW 7KH SRVLWLRQ DQG VSHHG RI WKH YRLFH FRLO PRWRU DUH FRQWUROOHG E\ FORVHGORRS VHUYR XVLQJ WKH VHUYR LQIRUPDWLRQ UHFRUGHG RQ WKH GDWD VXUIDFH 7KH VHUYR LQIRUPDWLRQ LV DQ DQDORJ VLJQDO FRQYHUWHGWRGLJLWDOIRUSURFHVVLQJE\D038DQGWKHQUHFRQYHUWHGWRDQDQDORJVLJQDOIRUFRQWURO RIWKHYRLFHFRLOPRWRU...
Page 52 M B 9 0 2 5 5 B CIRRUS SH3515 S V C HA13627FH SR1756 )LJXUH 03)[[[$+%ORFNGLDJUDP &((1 ...
Page 53: Power-On Sequence
Power-on Sequence Figure 4.3 describes the operation sequence of the disk drive at power-on. The outline is described below. a) After the power is turned on, the disk drive executes the MPU bus test, internal register read/write test, and work RAM read/write test. When the self-diagnosis terminates successfully, the disk drive starts the spindle motor.
Page 54: Power-On Operation Sequence
Power on Start Self-diagnosis 1 • MPU bus test • Inner register write/read test • Work RAM write/read test The spindle motor starts. Self-diagnosis 2 • Data buffer write/read test Confirming spindle motor speed Release heads from actuator lock Initial on-track and read out of system information Execute self-calibration Drive ready state...
Page 55: Self-Calibration
Self-calibration The disk drive occasionally performs self-calibration in order to sense and calibrate mechanical external forces on the actuator, and VCM torque. This enables precise seek and read/write operations. 4.5.1 Self-calibration contents Sensing and compensating for external forces The actuator suffers from torque due to the FPC forces and winds accompanying disk revolution. The torque vary with the disk drive and the cylinder where the head is positioned.
Page 56: Execution Timing Of Self-Calibration
4.5.2 Execution timing of self-calibration Self-calibration is executed when: • The power is turned on. • The self-calibration execution timechart of the disk drive specifies self-calibration. The disk drive performs self-calibration according to the timechart based on the time elapsed from power-on.
Page 57 5HDGZULWH&LUFXLW 7KHUHDGZULWHFLUFXLWFRQVLVWVRIWKHUHDGZULWHSUHDPSOLILHU3UH$03WKHZULWHFLUFXLWWKHUHDG FLUFXLWDQGWKHV\QWKHVL]HULQWKHUHDGFKDQQHO5'& 5HDGZULWHSUHDPSOLILHU3UH$03 2QH 3UH$03 LV PRXQWHG RQ WKH )3& 7KH 3UH$03 FRQVLVWV RI DQ FKDQQHO UHDG SUHDPSOLILHU DQGDZULWHFXUUHQWVZLWFKDQGVHQVHVDZULWHHUURU(DFKFKDQQHOLVFRQQHFWHGWRHDFKGDWDKHDG 7KHKHDG,&VZLWFKHVWKHKHDGVE\WKHVHULDOSRUW6'(16&/.6'$7$7KH,&JHQHUDWHVD ZULWH HUURU VHQVH VLJQDO :86 ZKHQ D ZULWH HUURU RFFXUV GXH WR KHDG VKRUW WR *1' KHDG GLVFRQQHFWLRQ :ULWHFLUFXLW...
Page 58 5HDGFLUFXLW 7KHKHDGUHDGVLJQDOIURPWKH3UH$03LVUHJXODWHGE\WKHYDULDEOHJDLQDPSOLILHU9*$FLUFXLW 7KHQWKHRXWSXWLVFRQYHUWHGLQWRWKHVDPSOHGUHDGGDWDSXOVHE\WKHSURJUDPPDEOHILOWHUFLUFXLW DQGWKHDGDSWLYHHTXDOL]HUFLUFXLW7KLVFORFNVLJQDOLVFRQYHUWHGLQWRWKH15=GDWDE\WKH *&5GHFRGHUFLUFXLWEDVHGRQWKHUHDGGDWDPD[LPXPOLNHOLKRRGGHWHFWHGE\WKH9LWHUELGHWHFWLRQ FLUFXLWWKHQLVVHQWWRWKH+'& 9*$FLUFXLW 7KH9*$FLUFXLWDXWRPDWLFDOO\UHJXODWHVWKHRXWSXWDPSOLWXGHWRDFRQVWDQWYDOXHHYHQZKHQWKH LQSXWDPSOLWXGHOHYHOIOXFWXDWHV7KH9*$RXWSXWLVPDLQWDLQHGDWDFRQVWDQWOHYHOHYHQZKHQWKH KHDGRXWSXWIOXFWXDWHVGXHWRWKHKHDGFKDUDFWHULVWLFVRURXWHULQQHUKHDGSRVLWLRQV 3URJUDPPDEOHILOWHU 7KH SURJUDPPDEOH ILOWHU FLUFXLW KDV D ORZSDVV ILOWHU IXQFWLRQ WKDW HOLPLQDWHV XQQHFHVVDU\ KLJK IUHTXHQF\QRLVHFRPSRQHQWDQGDKLJKIUHTXHQF\ERRVWXSIXQFWLRQWKDWHTXDOL]HVWKHZDYHIRUP RIWKHUHDGVLJQDO &XWRIIIUHTXHQF\RIWKHORZSDVVILOWHUDQGERRVWXSJDLQDUHFRQWUROOHGIURPHDFK'$&FLUFXLWLQ UHDGFKDQQHOE\DQLQVWUXFWLRQRIWKHSDUDOOHOGDWDVLJQDOIURP03807KH038RSWLPL]HV WKHFXWRIIIUHTXHQF\DQGERRVWXSJDLQDFFRUGLQJWRWKHWUDQVIHUIUHTXHQF\RIHDFK]RQH $GDSWLYHHTXDOL]HUFLUFXLW 7KLVFLUFXLWLVWDSDGDSWLYHGLJLWDO),5ILOWHUFLUFXLWWKDWFRVLQHHTXDOL]HVWKHKHDGUHDGVLJQDOWR WKH([WHQGHG3DUWLDO5HVSRQVH&ODVV(35ZDYHIRUP 9LWHUELGHWHFWLRQFLUFXLW 7KHGLJLWDOGDWDRXWSXWIURPWKHDGDSWLYHHTXDOL]HUFLUFXLWLVVHQWWRWKH9LWHUELGHWHFWLRQFLUFXLW 7KH9LWHUELGHWHFWLRQFLUFXLWGHPRGXODWHVGDWDDFFRUGLQJWRWKHVXUYLYRUSDWKVHTXHQFH 'DWDVHSDUDWRUFLUFXLW 7KH GDWD VHSDUDWRU FLUFXLW JHQHUDWHV FORFNV LQ V\QFKURQL]DWLRQ ZLWK WKH RXWSXW RI WKH DGDSWLYH HTXDOL]HU FLUFXLW 7R ZULWH GDWD WKH 9)2 FLUFXLW JHQHUDWHV FORFNV LQ V\QFKURQL]DWLRQ ZLWK WKH FORFNVLJQDOVIURPDV\QWKHVL]HU *&5GHFRGHU...
Page 59 6\QWKHVL]HUFLUFXLW 7KH GULYH XVHV FRQVWDQW GHQVLW\ UHFRUGLQJ WR LQFUHDVH WRWDO FDSDFLW\ 7KLV LV GLIIHUHQW IURP WKH FRQYHQWLRQDO PHWKRG RI UHFRUGLQJ GDWD ZLWK D IL[HG GDWD WUDQVIHU UDWH DW DOO GDWD DUHD ,Q WKH FRQVWDQWGHQVLW\UHFRUGLQJPHWKRGGDWDDUHDLVGLYLGHGLQWR]RQHVE\UDGLXVDQGWKHGDWDWUDQVIHU UDWHLVVHWVRWKDWWKHUHFRUGLQJGHQVLW\RIWKHLQQHUF\OLQGHURIHDFK]RQHLVQHDUO\FRQVWDQW7KH GULYH GLYLGHV GDWD DUHD LQWR ]RQHV WR VHW WKH GDWD WUDQVIHU UDWH 7DEOH GHVFULEHV WKH GDWD WUDQVIHUUDWHDQGUHFRUGLQJGHQVLW\%3,RIHDFK]RQH 7DEOH 7UDQVIHUUDWHRIHDFK]RQH...
Page 60: Servo Control
4.7.1 Servo control circuit Figure 4.4 is the block diagram of the servo control circuit. The following describes the functions of the blocks: VCM current Servo Head burst unit Amp. capture Position Sense Spindle Spindle Driver motor motor CSR: Current Sense Resistor control VCM: Voice Coil Motor Figure 4.4...
Page 61: Physical Sector Servo Configuration On Disk Surface
c. Seek to specified cylinder Drives the VCM to position the head to the specified cylinder. d. Calibration Senses and stores the thermal offset between heads and the mechanical forces on the actuator, and stores the calibration value. Servo frame (72 servo frames per revolution) Figure 4.5 Physical sector servo configuration on disk surface...
Page 62 Servo burst capture circuit The four servo signals can be synchronously detected by the DEMOD signal (internal), full-wave rectified integrated. A/D converter (ADC) The A/D converter (ADC) receives the servo signals are integrated, converts them to digital, and transfers the digital signal to the DSP unit. D/A converter (DAC) The D/A converter (DAC) converts the VCM drive current value (digital value) calculated by the DSP unit into analog values and transfers them to the power amplifier.
Page 63: Data-Surface Servo Format
4.7.2 Data-surface servo format Figure 4.5 describes the physical layout of the servo frame. The three areas indicated by (1) to (3) in Figure 4.6 are described below. Inner guard band The head is in contact with the disk in this space when the spindle starts turning or stops, and the rotational speed of the spindle can be controlled on this cylinder area for head moving.
Page 64 PV PV PV PV PV PV PV PV PV PV PV PV PV PV PV PV PV PV PV PV 6&' & :55HFRYHU\)LHOG PV PV 6HUYR 6HUYR '$7$ '$7$ )UDPH )UDPH PV )LJXUH VHUYRIUDPHVLQHDFKWUDFN :ULWHUHDGUHFRYHU\ 7KLVDUHDLVXVHGWRDEVRUEWKHZULWHUHDGWUDQVLHQWDQGWRVWDELOL]HWKH$*& 6HUYRPDUN$60660 7KLVDUHDJHQHUDWHVDWLPLQJIRUGHPRGXODWLQJWKHJUD\FRGHDQGSRVLWLRQGHPRGXODWLQJ3RV$WR 'E\GHWHFWLQJWKHVHUYRPDUN &((1 ...
Page 65: Actuator Motor Control
Preamble This area is used to synchronize with the PLL, which is used to search the SSM by detecting the ASM. Gray code (including index bit) This area is used as cylinder address. The data in this area is converted into the binary data by the gray code demodulation circuit.
Page 66: Spindle Motor Control
(called SVC hereafter). The firmware operates on the MPU manufactured by Fujitsu. The spindle motor is controlled by sending several signals from the MPU to the SVC. There are three modes for the spindle control;...
Page 67 Acceleration mode In this mode, the MPU stops to send the phase switching signal to the SVC. The SVC starts a phase switching by itself based on the counter electromotive force. Then, rotation of the spindle motor accelerates. The MPU calculates a rotational speed of the spindle motor based on the PHASE signal from the SVC, and accelerates till the rotational speed reaches 7,200 rpm.
Page 68 &+$37(5 ,17(5)$&( 3K\VLFDO,QWHUIDFH /RJLFDO,QWHUIDFH +RVW&RPPDQGV &RPPDQG3URWRFRO 8OWUD'0$IHDWXUHVHW 7LPLQJ &((1 ...
Page 69: Chapter 5 Interface
Physical Interface 5.1.1 Interface signals Table 5.1 shows the interface signals. Table 5.1 Interface signals Description Host Acrorym Cable select see note CSEL → Chip select 0 CS0– → Chip select 1 CS1– ↔ Data bus bit 0 ↔ Data bus bit 1 ↔...
Page 70: Signal Assignment On The Connector
5.1.2 Signal assignment on the connector Table 5.2 shows the signal assignment on the interface connector. Table 5.2 Signal assignment on the interface connector Pin No. Signal Pin No. Signal RESET– DATA7 DATA8 DATA6 DATA9 DATA5 DATA10 DATA4 DATA11 DATA3 DATA12 DATA2 DATA13...
Page 71 [signal] [I/O] [Description] DIOR– DIOR– is the strobe signal asserted by the host to read device registers or the data port. HDMARDY– HDMARDY– is a flow control signal for Ultra DMA data in bursts. This signal is asserted by the host to indicate to the device that the host is ready to receive Ultra DMA data in bursts.
Page 72 [signal] [I/O] [Description] IORDY This signal is negated to extend the host transfer cycle of any host register access (Read or Write) when the device is not ready to respond to a data transfer request. DDMARDY– DDMARDY– is a flow control signal for Ultra DMA data out bursts. This signal is asserted by the device to indicate to the host that the device is ready to receive Ultra DMA data out bursts.
Page 73: Logical Interface
Logical Interface The device can operate for command execution in either address-specified mode; cylinder-head- sector (CHS) or Logical block address (LBA) mode. The IDENTIFY DEVICE information indicates whether the device supports the LBA mode. When the host system specifies the LBA mode by setting bit 6 in the Device/Head register to 1, HS3 to HS0 bits of the Device/Head register indicates the head No.
Page 74: Command Block Registers
Table 5.3 I/O registers I/O registers Host I/O CS0– CS1– address Read operation Write operation Command block registers Data Data X'1F0' Error Register Features X'1F1' Sector Count Sector Count X'1F2' Sector Number Sector Number X'1F3' Cylinder Low Cylinder Low X'1F4' Cylinder High Cylinder High X'1F5'...
Page 75 5.2.2 Command block registers Data register (X'1F0') The Data register is a 16-bit register for data block transfer between the device and the host system. Data transfer mode is PIO or LBA mode. Error register (X'1F1') The Error register indicates the status of the command executed by the device. The contents of this register are valid when the ERR bit of the Status register is 1.
Page 76 [Diagnostic code] X'01': No Error Detected. X'02': HDC Register Compare Error X'03': Data Buffer Compare Error. X'05': ROM Sum Check Error. X'80': Device 1 (slave device) Failed. Error register of the master device is valid under two devices (master and slave) configuration.
Page 77 Cylinder Low register (X'1F4') The contents of this register indicates low-order 8 bits of the starting cylinder address for any disk-access. At the end of a command, the contents of this register are updated to the current cylinder number. Under the LBA mode, this register indicates LBA bits 15 to 8. Cylinder High register (X'1F5') The contents of this register indicates high-order 8 bits of the disk-access start cylinder address.
Page 78 Status register (X'1F7') The contents of this register indicate the status of the device. The contents of this register are updated at the completion of each command. When the BSY bit is cleared, other bits in this register should be validated within 400 ns. When the BSY bit is 1, other bits of this register are invalid.
Page 79 - Bit 3: Data Request (DRQ) bit. This bit indicates that the device is ready to transfer data of word unit or byte unit between the host system and the device. - Bit 2: Always 0. - Bit 1: Always 0. - Bit 0: Error (ERR) bit.
Page 80: Host Commands
5.2.3 Control block registers Alternate Status register (X'3F6') The Alternate Status register contains the same information as the Status register of the command block register. The only difference from the Status register is that a read of this register does not imply Interrupt Acknowledge and INTRQ signal is not reset.
Page 81: Command Code And Parameters
5.3.1 Command code and parameters Table 5.4 lists the supported commands, command code and the registers that needed parameters are written. Table 5.4 Command code and parameters (1 of 2) Command code (Bit) Parameters used Command name FR SC SN CY DH READ SECTOR(S) READ MULTIPLE READ DMA...
Page 82 Table 5.4 Command code and parameters (2 of 2) Command code (Bit) Parameters used Command name FR SC SN CY DH STANDBY IMMEDIATE SLEEP CHECK POWER MODE SMART FLUSH CACHE SECURITY DISABLE PASSWORD SECURITY ERASE PREPARE SECURITY ERASE UNIT SECURITY FREEZE LOCK SECURITY SET PASSWORD SECURITY UNLOCK SET MAX ADDRESS...
Page 83: Command Descriptions
5.3.2 Command descriptions The contents of the I/O registers to be necessary for issuing a command and the example indication of the I/O registers at command completion are shown as following in this subsection. Example: READ SECTOR(S) At command issuance (I/O registers setting contents) (CM) ×...
Page 84 Note: When the L bit is specified to 1, the lower 4 bits of the DH register and all bits of the CH, CL and SN registers indicate the LBA bits (bits of the DH register are the MSB (most significant bit) and bits of the SN register are the LSB (least significant bit). At error occurrence, the SC register indicates the remaining sector count of data transfer.
Page 85 At command completion (I/O registers contents to be read) (ST) Status information × × (DH) End head No. /LBA [MSB] (CH) End cylinder No. [MSB] / LBA (CL) End cylinder No. [LSB] / LBA (SN) End sector No. / LBA [LSB] (SC) 00 (*1) (ER)
Page 86: Execution Example Of Read Multiple Command
Figure 5.1 shows an example of the execution of the READ MULTIPLE command. • Block count specified by SET MULTIPLE MODE command = 4 (number of sectors in a block) • READ MULTIPLE command specifies; Number of requested sectors = 9 (Sector Count register = 9) ↓...
Page 87 READ DMA (X'C8' or X'C9') This command operates similarly to the READ SECTOR(S) command except for following events. • The data transfer starts at the timing of DMARQ signal assertion. • The device controls the assertion or negation timing of the DMARQ signal. •...
Page 88 At command completion (I/O registers contents to be read) (ST) Status information × × (DH) End head No. /LBA [MSB] (CH) End cylinder No. [MSB] / LBA (CL) End cylinder No. [LSB] / LBA (SN) End sector No. / LBA [LSB] (SC) 00 (*1) (ER)
Page 89 At command completion (I/O registers contents to be read) (ST) Status information × × (DH) End head No. /LBA [MSB] (CH) End cylinder No. [MSB] / LBA (CL) End cylinder No. [LSB] / LBA (SN) End sector No. / LBA [LSB] (SC) 00 (*1) (ER)
Page 90 At command completion (I/O registers contents to be read) (ST) Status information × × (DH) End head No. /LBA [MSB] (CH) End cylinder No. [MSB] / LBA (CL) End cylinder No. [LSB] / LBA (SN) End sector No. / LBA [LSB] (SC) 00 (*1) (ER)
Page 91 The contents of the command block registers related to addresses after the transfer of a data block containing an erred sector are undefined. To obtain a valid error information, the host should retry data transfer as an individual requests. At command issuance (I/O registers setting contents) (CM) ×...
Page 92 1) Multiword DMA transfer mode 2: Sets the FR register = X'03' and SC register = X'22' by the SET FEATURES command 2) Ultra DMA transfer mode 2: Sets the FR register = X'03' and SC register = X'42' by the SET FEATURES command At command issuance (I/O registers setting contents) (CM) ×...
Page 93 At command completion (I/O registers contents to be read) (ST) Status information × × (DH) End head No. /LBA [MSB] (CH) End cylinder No. [MSB] / LBA (CL) End cylinder No. [LSB] / LBA (SN) End sector No. / LBA [LSB] (SC) 00 (*1) (ER)
Page 94 (10) SEEK (X'7x', x : X'0' to X'F') This command performs a seek operation to the track and selects the head specified in the command block registers. After completing the seek operation, the device clears the BSY bit in the Status register and generates an interrupt. The IDD always sets the DSC bit (Drive Seek Complete status) of the Status register to 1.
Page 95 (11) INITIALIZE DEVICE PARAMETERS (X'91') The host system can set the number of sectors per track and the maximum head number (maximum head number is "number of heads minus 1") per cylinder with this command. Upon receipt of this command, the device sets the BSY bit of Status register and saves the parameters. Then the device clears the BSY bit and generates an interrupt.
Page 96 $WFRPPDQGLVVXDQFH,2UHJLVWHUVVHWWLQJFRQWHQWV &0 '+ &+ &/ 61 6& )5 $WFRPPDQGFRPSOHWLRQ,2UHJLVWHUVFRQWHQWVWREHUHDG 67 6WDWXVLQIRUPDWLRQ '+ &+ &/ 61 6& (5 (UURULQIRUPDWLRQ 7DEOH ,QIRUPDWLRQWREHUHDGE\,'(17,)<'(9,&(FRPPDQGRI :RUG 9DOXH 'HVFULSWLRQ ;¨$© *HQHUDO&RQILJXUDWLRQ 1XPEHURIF\OLQGHUV ;¨© 5HVHUYHG 1XPEHURI+HDGV ;¨© 5HWLUHG ;¨© 5HWLUHG ;¨)© 1XPEHURIVHFWRUVSHUWUDFN ;¨© 5HWLUHG ¤ 6HULDOQXPEHU$6&,,FRGH ;¨©...
Page 97 7DEOH ,QIRUPDWLRQWREHUHDGE\,'(17,)<'(9,&(FRPPDQGRI :RUG 9DOXH 'HVFULSWLRQ 9DULDEOH 1XPEHURIFXUUHQW&\OLQGHUV 9DULDEOH 1XPEHURIFXUUHQW+HDG 9DULDEOH 1XPEHURIFXUUHQWVHFWRUVSHUWUDFN 9DULDEOH 7RWDOQXPEHURIFXUUHQWVHFWRUV 7UDQVIHUVHFWRUFRXQWFXUUHQWO\VHWE\5($':5,7(08/7,3/(FRPPDQG 7RWDOQXPEHURIXVHUDGGUHVVDEOHVHFWRUV/%$PRGHRQO\ ;¨© 5HWLUHG ;¨[[© 0XOWLZRUG'0$WUDQVIHUPRGH ;¨© $GYDQFH3,2WUDQVIHUPRGHVXSSRUWVWDWXV ;¨© 0LQLPXPPXOWLZRUG'0$WUDQVIHUF\FOHWLPHSHUZRUG>QV@ ;¨© 0DQXIDFWXUHU VUHFRPPHQGHG'0$WUDQVIHUF\FOHWLPH>QV@ ;¨© 0LQLPXP3,2WUDQVIHUF\FOHWLPHZLWKRXWIORZFRQWURO>QV@ ;¨© 0LQLPXP3,2WUDQVIHUF\FOHWLPHZLWK,25'<IORZFRQWURO>QV@ ;¨© 5HVHUYHG ;¨(© 0DMRUYHUVLRQQXPEHU ;¨© 0LQRUYHUVLRQQXPEHUQRWUHSRUWHG ;¨%© 6XSSRUWRIFRPPDQGVHWV ;¨©...
Page 98 7DEOH ,QIRUPDWLRQWREHUHDGE\,'(17,)<'(9,&(FRPPDQGRI :RUG*HQHUDOFRQILJXUDWLRQ %LW $7$GHYLFH %LW9HQGRUVSHFLILF %LW 5HPRYDEOHPHGLDGHYLFH %LW QRWUHPRYDEOHFRQWUROOHUDQGRUGHYLFH %LW9HQGRUVSHFLILF %LW5HVHUYHG 1XPEHURI&\OLQGHUV 1XPEHURI+HDGV 7RWDOQXPEHURIXVHUDGGUHVVDEOHVHFWRUV/%$PRGHRQO\ 03)$+ 03)$+ 03)$+ ;¨)))© ;¨© &'& &$$ '% :RUG6HULDOQXPEHU$6&,,FRGHFKDUDFWHUVULJKWMXVWLILHG :RUG)LUPZDUHUHYLVLRQ$6&,,FRGHFKDUDFWHUV/HIWMXVWLILHG :RUG0RGHOQXPEHU $6&,,FRGHFKDUDFWHUV/HIWMXVWLILHGUHPDLQGHUILOOHGZLWKEODQNFRGH; 2QHRIWKHIROORZLQJPRGHOQXPEHUV 03)$+03)$+03)$+ :RUG&DSDELOLWLHV %LW5HVHUYHG %LW6WDQGE\WLPHUYDOXH 6WDQGE\WLPHUYDOXHVVKDOOEHPDQDJHGE\WKHGHYLFH %LW5HVHUYHG %LW,25'<VXSSRUW 6XSSRUWHG %LW,25'<LQKLELWLRQ 'LVDEOHLQKLELWLRQ %LW/%$VXSSRUW 6XSSRUWHG %LW'0$VXSSRUW 6XSSRUWHG...
Page 99 7DEOH ,QIRUPDWLRQWREHUHDGE\,'(17,)<'(9,&(FRPPDQGRI :RUG0XOWLZRUG'0$WUDQVIHUPRGH %LW&XUUHQWO\XVHGPXOWLZRUG'0$WUDQVIHUPRGH %LW6XSSRUWDEOHPXOWLZRUG'0$WUDQVIHUPRGH %LW 0RGH %LW 0RGH %LW 0RGH :RUG$GYDQFH3,2WUDQVIHUPRGHVXSSRUWVWDWXV %LW5HVHUYHG %LW$GYDQFH3,2WUDQVIHUPRGH %LW 0RGH %LW 0RGH :RUG0DMRUYHUVLRQQXPEHU %LW5HVHUYHG %LW$7$6XSSRUWHG %LW$7$6XSSRUWHG %LW$7$6XSSRUWHG %LW$7$6XSSRUWHG %LW$7$6XSSRUWHG %LW8QGHILQHG :RUG6XSSRUWRIFRPPDQGVHWV %LW5HVHUYHG %LW123FRPPDQGVXSSRUWHG %LW5HDG%XIIHUFRPPDQGVXSSRUWHG %LW:ULWH%XIIHUFRPPDQGVXSSRUWHG %LW:ULWH9HULI\FRPPDQGVXSSRUWHG2OG6SHF %LW+RVW3URWHFWHG$UHDIHDWXUHFRPPDQGVXSSRUWHG ...
Page 100 7DEOH ,QIRUPDWLRQWREHUHDGE\,'(17,)<'(9,&(FRPPDQGRI :RUG(QDEOHGLVDEOH&RPPDQGVHWIHDWXUHHQDEOHG %LW5HVHUYHG %LW123FRPPDQGHQDEOHG %LW5($'%8))(5FRPPDQGHQDEOHG %LW:5,7(%8))(5FRPPDQGHQDEOHG %LW5HVHUYHG %LW+RVW3URWHFWHG$UHDIHDWXUHVHWHQDEOHG %LW'(9,&(5(6(7FRPPDQGHQDEOHG %LW6(59,&(LQWHUUXSWHQDEOHG %LW5HOHDVHLQWHUUXSWHQDEOHG %LW/RRNDKHDGHQDEOHG %LW:ULWHFDFKHHQDEOHG %LW3$&.(7&RPPDQGIHDWXUHVHWHQDEOHG %LW3RZHU0DQDJHPHQWIHDWXUHVHWHQDEOHG %LW5HPRYDEOH0HGLDIHDWXUHVHWHQDEOHG %LW6HFXULW\0RGHIHDWXUHVHWHQDEOHG %LW60$57IHDWXUHVHWHQDEOHG :RUG(QDEOHGLVDEOH&RPPDQGVHWIHDWXUHHQDEOHG %LW5HVHUYHG %LW$XWRPDWLF$FRXVWLF0DQDJHPHQW6ORZ6HHNPRGHVXSSRUWHG %LW5HVHUYHG %LW5HPRYDEOH0HGLD6WDWXV1RWLILFDWLRQIHDWXUHVHWHQDEOHG %LW$GYDQFHG3RZHU0DQDJHPHQWIHDWXUHVHWHQDEOHG %LW&)$IHDWXUHVHWVXSSRUWHG %LW5($':5,7('0$48(8('FRPPDQGVXSSRUWHG %LW'2:1/2$'0,&52&2'(FRPPDQGVXSSRUWHG :RUG8OWUD'0$PRGHV %LW5HVHUYHG %LW&XUUHQWO\XVHG8OWUD'0$WUDQVIHUPRGHV...
Page 101 (13) IDENTIFY DEVICE DMA (X'EE') When this command is not used to transfer data to the host in DMA mode, this command functions in the same way as the Identify Device command. At command issuance (I/O registers setting contents) (CM) ×...
Page 102 7DEOH )HDWXUHVUHJLVWHUYDOXHVDQGVHWWDEOHPRGHV )HDWXUHV5HJLVWHU 'ULYHRSHUDWLRQPRGH ;¨© (QDEOHVWKHZULWHFDFKHIXQFWLRQ ;¨© 6SHFLILHVWKHWUDQVIHUPRGH6XSSRUWV3,2PRGHVLQJOHZRUG'0$PRGH DQGPXOWLZRUG'0$PRGHUHJDUGOHVVRI6HFWRU&RXQWUHJLVWHUFRQWHQWV ;¨© 1RRSHUDWLRQ ;¨© (QDEOHWKHDGYDQFHGSRZHUPDQDJHPHQWIXQFWLRQ ;¨© 1RRSHUDWLRQ ;¨© 1RRSHUDWLRQ ;¨© 'LVDEOHVWKHUHDGFDFKHIXQFWLRQ ;¨© 'LVDEOHVWKHUHYHUWLQJWRSRZHURQGHIDXOWVHWWLQJVDIWHUVRIWZDUHUHVHW ;¨© 1RRSHUDWLRQ ;¨© 1RRSHUDWLRQ ;¨© 'LVDEOHVWKHZULWHFDFKHIXQFWLRQ ;¨© 1RRSHUDWLRQ ;¨© 'LVDEOHWKHDGYDQFHGSRZHUPDQDJHPHQWIXQFWLRQ ;¨© 1RRSHUDWLRQ ;¨© 1RRSHUDWLRQ ;¨$$© (QDEOHVWKHUHDGFDFKHIXQFWLRQ ;¨$%© 1RRSHUDWLRQ ;¨%%© 6SHFLILHVWKHWUDQVIHURIE\WH(&&IRU5($'/21*DQG:5,7(/21* FRPPDQGV ;¨&&©...
Page 103 At command issuance (I/O registers setting contents) (CM) × × × (DH) (CH) (CL) (SN) (SC) xx or transfer mode (FR) [See Table 5.6] At command completion (I/O registers contents to be read) (ST) Status information × × × (DH) (CH) (CL) (SN)
Page 104 (15) SET MULTIPLE MODE (X'C6') This command enables the device to perform the READ MULTIPLE and WRITE MULTIPLE commands. The block count (number of sectors in a block) for these commands are also specified by the SET MULTIPLE MODE command. The number of sectors per block is written into the Sector Count register.
Page 105 Regarding software reset, the mode set prior to software reset is retained after software reset. The parameters for the multiple commands which are posted to the host system when the IDENTIFY DEVICE command is issued are listed below. See Subsection 5.3.2 for the IDENTIFY DEVICE command.
Page 106 Table 5.7 Diagnostic code Code Result of diagnostic X‘01’ No error detected. X‘03’ Data buffer compare error X‘05’ ROM sum check error X‘8x’ Failure of device 1 At command issuance (I/O registers setting contents) (CM) × × × (DH) (CH) (CL) (SN) (SC)
Page 107 The READ LONG command supports only single sector operation. At command issuance (I/O registers setting contents) (CM) × × (DH) Head No. /LBA [MSB] (CH) Cylinder No. [MSB] / LBA (CL) Cylinder No. [LSB] / LBA (SN) Sector No. / LBA [LSB] (SC) Number of sectors to be transferred (FR)
Page 108 At command issuance (I/O registers setting contents) (CM) × × (DH) Head No. /LBA [MSB] (CH) Cylinder No. [MSB] / LBA (CL) Cylinder No. [LSB] / LBA (SN) Sector No. / LBA [LSB] (SC) Number of sectors to be transferred (FR) R = 0 or 1 At command completion (I/O registers contents to be read)
Page 109 At command completion (I/O registers contents to be read) (ST) Status information × × × (DH) (CH) (CL) (SN) (SC) (ER) Error information (21) WRITE BUFFER (X'E8') The host system can overwrite the contents of the sector buffer of the device with a desired data pattern by issuing this command.
Page 110 (22) IDLE (X'97' or X'E3') Upon receipt of this command, the device sets the BSY bit of the Status register, and enters the idle mode. Then, the device clears the BSY bit, and generates an interrupt. The device generates an interrupt even if the device has not fully entered the idle mode. If the spindle of the device is already rotating, the spin-up sequence shall not be implemented.
Page 111 At command completion (I/O registers contents to be read) (ST) Status information × × × (DH) (CH) (CL) (SN) (SC) (ER) Error information (23) IDLE IMMEDIATE (X'95' or X'E1') Upon receipt of this command, the device sets the BSY bit of the Status register, and enters the idle mode.
Page 112 (24) STANDBY (X'96' or X'E2') Upon receipt of this command, the device sets the BSY bit of the Status register and enters the standby mode. The device then clears the BSY bit and generates an interrupt. The device generates an interrupt even if the device has not fully entered the standby mode. If the device has already spun down, the spin-down sequence is not implemented.
Page 113 At command issuance (I/O registers setting contents) (CM) X'94' or X'E0' × × × (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) Status information × × × (DH) (CH) (CL) (SN) (SC) (ER) Error information (26)
Page 114 At command completion (I/O registers contents to be read) (ST) Status information × × × (DH) (CH) (CL) (SN) (SC) (ER) Error information (27) CHECK POWER MODE (X'98' or X'E5') The host checks the power mode of the device with this command. The host system can confirm the power save mode of the device by analyzing the contents of the Sector Count and Sector Number registers.
Page 115 At command issuance (I/O registers setting contents) (CM) X'98' or X'E5' × × × (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) Status information × × × (DH) (CH) (CL) (SN) (SC) X'00' or X'FF' (ER) Error information...
Page 116 7DEOH)HDWXUHV5HJLVWHUYDOXHVVXEFRPPDQGVDQGIXQFWLRQV )HDWXUHV5HVLVWHU )XQFWLRQ ;©'© 60$575HDG$WWULEXWH9DOXHV $GHYLFHWKDWUHFHLYHGWKLVVXEFRPPDQGDVVHUWVWKH%6<ELWDQGVDYHVDOOWKH XSGDWHGDWWULEXWHYDOXHV7KHGHYLFHWKHQFOHDUVWKH%6<ELWDQGWUDQVIHUVE\WH DWWULEXWHYDOXHLQIRUPDWLRQWRWKHKRVW )RULQIRUPDWLRQDERXWWKHIRUPDWRIWKHDWWULEXWHYDOXHLQIRUPDWLRQVHH7DEOH ;©'© 60$575HDG$WWULEXWH7KUHVKROGV 7KLVVXEFRPPDQGLVXVHGWRWUDQVIHUE\WHLQVXUDQFHIDLOXUHWKUHVKROGYDOXHGDWD WRWKHKRVW )RULQIRUPDWLRQDERXWWKHIRUPDWRIWKHLQVXUDQFHIDLOXUHWKUHVKROGYDOXHGDWDVHH 7DEOH ;©'© 60$57(QDEOH'LVDEOH$WWULEXWH$XWR6DYH 7KLVVXEFRPPDQGLVXVHGWRHQDEOH6&UHJLVWHUzKRUGLVDEOH6&UHJLVWHU KWKHVHWWLQJRIWKHDXWRPDWLFVDYLQJIHDWXUHIRUWKHGHYLFHDWWULEXWHGDWD7KH VHWWLQJLVPDLQWDLQHGHYHU\WLPHWKHGHYLFHLVWXUQHGRIIDQGWKHQRQ:KHQWKH DXWRPDWLFVDYLQJIHDWXUHLVHQDEOHGWKHDWWULEXWHYDOXHVDUHVDYHGDIWHUPLQXWHV SDVVHGVLQFHWKHSUHYLRXVVDYLQJRIWKHDWWULEXWHYDOXHV+RZHYHULIWKHIDLOXUH SUHGLFWLRQIHDWXUHLVGLVDEOHGWKHDWWULEXWHYDOXHVDUHQRWDXWRPDWLFDOO\VDYHG :KHQWKHGHYLFHUHFHLYHVWKLVVXEFRPPDQGLWDVVHUWVWKH%6<ELWHQDEOHVRU GLVDEOHVWKHDXWRPDWLFVDYLQJIHDWXUHWKHQFOHDUVWKH%6<ELW ;©'© 60$576DYH$WWULEXWH9DOXHV :KHQWKHGHYLFHUHFHLYHVWKLVVXEFRPPDQGLWDVVHUWVWKH%6<ELWVDYHVGHYLFH DWWULEXWHYDOXHGDWDWKHQFOHDUVWKH%6<ELW ;©'© 60$57(QDEOH2SHUDWLRQV 7KLVVXEFRPPDQGHQDEOHVWKHIDLOXUHSUHGLFWLRQIHDWXUH7KHVHWWLQJLVPDLQWDLQHG HYHQZKHQWKHGHYLFHLVWXUQHGRIIDQGWKHQRQ :KHQWKHGHYLFHUHFHLYHVWKLVVXEFRPPDQGLWDVVHUWVWKH%6<ELWHQDEOHVWKH IDLOXUHSUHGLFWLRQIHDWXUHWKHQFOHDUVWKH%6<ELW ;©'© 60$57'LVDEOH2SHUDWLRQV 7KLVVXEFRPPDQGGLVDEOHVWKHIDLOXUHSUHGLFWLRQIHDWXUH7KHVHWWLQJLVPDLQWDLQHG HYHQZKHQWKHGHYLFHLVWXUQHGRIIDQGWKHQRQ :KHQWKHGHYLFHUHFHLYHVWKLVVXEFRPPDQGLWDVVHUWVWKH%6<ELWGLVDEOHVWKH IDLOXUHSUHGLFWLRQIHDWXUHWKHQFOHDUVWKH%6<ELW ;©'$©...
Page 117 The host can predict failures in the device by periodically issuing the SMART Return Status subcommand (FR register = DAh) to reference the CL and CH registers. If an attribute value is below the insurance failure threshold value, the device is about to fail or the device is nearing the end of it life .
Page 118 The attribute value information is 512-byte data; the format of this data is shown below. The host can access this data using the SMART Read Attribute Values subcommand (FR register = D0h). The insurance failure threshold value data is 512-byte data; the format of this data is shown below.
Page 119 Table 5.10 Format of insurance failure threshold value data Byte Item Data format version number Attribute 1 Attribute ID Insurance failure threshold Threshold 1 (Threshold of Reserved attribute 1) Threshold 2 to (The format of each threshold value is the same as threshold 30 that of bytes 02 to 0D.) Reserved...
Page 120 • Attribute ID The attribute ID is defined as follows: Attribute ID Attribute name (Indicates unused attribute data.) Read error rate Throughput performance Spin up time Number of times the spindle motor is activated Number of alternative sectors Seek error rate Seek time performance Power-on time Number of retries made to activate the spindle motor...
Page 121 • Raw attribute value Raw attributes data is retained. • Failure prediction capability flag Bit 0: The attribute value data is saved to a medium before the device enters power saving mode. Bit 1: The device automatically saves the attribute value data to a medium after the previously set operation.
Page 122 )/86+&$&+(;¨(© 7KLVFRPPDQGLVXVHE\WKHKRVWWRUHTXHVWWKHGHYLFHWRIOXVKWKHZULWHFDFKH,IWKHZULWHFDFKH LVWREHIOXVKHGDOOGDWDFDFKHGVKDOOEHZULWWHQWRWKHPHGLD7KH%6<ELWVKDOOUHPDLQVHWWRRQH XQWLO DOO GDWD KDV EHHQ VXFFHVVIXOO\ ZULWWHQ RU DQ HUURU RFFXUV 7KH GHYLFH VKRXOG XVH DOO HUURU UHFRYHU\PHWKRGVDYDLODEOHWRHQVXUHWKHGDWDLVZULWWHQVXFFHVVIXOO\7KHIOXVKLQJRIZULWHFDFKH PD\WDNHVHYHUDOVHFRQGVWRFRPSOHWHGHSHQGLQJXSRQWKHDPRXQWRIGDWDWREHIOXVKHGDQGWKH VXFFHVVRIWKHRSHUDWLRQ 127(7KLVFRPPDQGPD\WDNHORQJHUWKDQVWRFRPSOHWH ,I WKH FRPPDQG LV QRW VXSSRUWHG WKH GHYLFH VKDOO VHW WKH $%57 ELW WR RQH $Q XQUHFRYHUDEOH HUURUHQFRXQWHUHGGXULQJH[HFXWLRQRIZULWLQJGDWDUHVXOWVLQWKHWHUPLQDWLRQRIWKHFRPPDQGDQG WKH &RPPDQG %ORFN UHJLVWHUV FRQWDLQ WKH VHFWRU DGGUHVV RI WKH VHFWRU ZKHUH WKH ILUVW XQUHFRYHUDEOH HUURU RFFXUUHG 7KH VHFWRU LV UHPRYHG IURP WKH FDFKH 6XEVHTXHQW )/86+...
Page 123 (30) SECURITY DISABLE PASSWORD (F6h) This command invalidates the user password already set and releases the lock function. The host transfers the 512-byte data shown in Table 1.1 to the device. The device compares the user password or master password in the transferred data with the user password or master password already set, and releases the lock function if the passwords are the same.
Page 124 At command issuance (I-O registers setting contents) (CM) × × × (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I-O registers setting contents) (ST) Status information × × × (DH) (CH) (CL) (SN) (SC) (ER) Error information (31) SECURITY ERASE PREPARE (F3h) The SECURITY ERASE UNIT command feature is enabled by issuing the SECURITY ERASE PREPARE command and then the SECURITY ERASE UNIT command.
Page 125 At command issuance (I-O registers setting contents) (CM) × × × (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I-O registers setting contents) (ST) Status information × × × (DH) (CH) (CL) (SN) (SC) (ER) Error information (32) SECURITY ERASE UNIT (F4h) This command erases all user data.
Page 126 $WFRPPDQGLVVXDQFH,2UHJLVWHUVVHWWLQJFRQWHQWV &0 '+ &+ &/ 61 6& )5 $WFRPPDQGFRPSOHWLRQ,2UHJLVWHUVVHWWLQJFRQWHQWV 67 6WDWXVLQIRUPDWLRQ '+ &+ &/ 61 6& (5 (UURULQIRUPDWLRQ 6(&85,7<)5((=(/2&.)K 7KLVFRPPDQGSXWVWKHGHYLFHLQWR)52=(102'(7KHIROORZLQJFRPPDQGVXVHGWRFKDQJH WKHORFNIXQFWLRQUHWXUQWKH$ERUWHG&RPPDQGHUURULIWKHGHYLFHLVLQ)52=(102'( 6(&85,7<6(73$66:25' 6(&85,7<81/2&. 6(&85,7<',6$%/(3$66:25' 6(&85,7<(5$6(35(3$5( 6(&85,7<(5$6(81,7 )52=(1 02'( LV FDQFHOHG ZKHQ WKH SRZHU LV WXUQHG RII ,I WKLV FRPPDQG LV UHLVVXHG LQ )52=(102'(WKHFRPPDQGLVFRPSOHWHGDQG)52=(102'(UHPDLQVXQFKDQJHG ,VVXLQJWKLVFRPPDQGGXULQJ/2&.('02'(UHWXUQVWKH$ERUWHG&RPPDQGHUURU 7KHIROORZLQJPHGLXPDFFHVVFRPPDQGVUHWXUQWKH$ERUWHG&RPPDQGHUURUZKHQWKHGHYLFHLV...
Page 127 x 5($''0$ x :5,7(/21* x 6(&85,7<',6$%/(3$66:25' x 5($'/21* x :5,7(08/7,3/( x 6(&85,7<)5((=(/2&. x 5($'08/7,3/( x :5,7(6(&7256 x 6(&85,7<6(73$66:25' x 5($'6(&7256 x :5,7(9(5,)< x )250$775$&. x 5($'9(5,)< x 6(70$;$''5(66 x )/$6+&$&+( x :5,7('0$ $WFRPPDQGLVVXDQFH,2UHJLVWHUVVHWWLQJFRQWHQWV &0 '+ &+ &/ 61 6& )5 $WFRPPDQGFRPSOHWLRQ,2UHJLVWHUVVHWWLQJFRQWHQWV 67 6WDWXVLQIRUPDWLRQ...
Page 128 Table 5.12 Contents of SECURITY SET PASSWORD data Word Contents Control word Bit 0 Identifier 0 = Sets a user password. 1 = Sets a master password. Bits 1 to 7 Reserved Bit 8 Security level 0 = High 1 = Maximum Bits 9 to 15 Reserved 1 to 16 Password (32 bytes)
Page 129 At command issuance (I-O registers setting contents) (CM) × × × (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I-O registers setting contents) (ST) Status information × × × (DH) (CH) (CL) (SN) (SC) (ER) Error information (35) SECURITY UNLOCK (F2h) This command cancels LOCKED MODE.
Page 130 At command issuance (I-O registers setting contents) (CM) × × × (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I-O registers setting contents) (ST) Status information × × × (DH) (CH) (CL) (SN) (SC) (ER) Error information (36) SET MAX ADDRESS (F9) This command allows the maximum address accessible by the user to be set in LBA or CHS mode.
Page 131 At command issuance (I/O registers setting contents) (CM) × × (DH) Max head/LBA [MSB] (CH) Max. cylinder [MSB]/Max. LBA (CL) Max. cylinder [LSB]/Max. LBA (SN) Max. sector/Max. LBA [LSB] (SC) (FR) At command completion (I/O registers contents to be read) (ST) Status information ×...
Page 132 At command completion (I/O registers contents to be read) (ST) Status information × × × (DH) Max head/LBA [MSB] (CH) Max. cylinder [MSB]/Max. LBA (CL) Max. cylinder [LSB]/Max. LBA (SN) Max. sector/Max. LBA [LSB] (SC) (ER) Error information C141-E106-01EN 5 - 65...
Page 133: Error Posting
5.3.3 Error posting Table 5.14 lists the defined errors that are valid for each command. Table 5.14 Command code and parameters Command name Error register (X'1F1') Status register (X'1F7') ICRC INDF ABRT TR0NF DRDY READ SECTOR(S) WRITE SECTOR(S) READ MULTIPLE WRITE MULTIPLE READ DMA WRITE DMA...
Page 134: Command Protocol
Command Protocol The host should confirm that the BSY bit of the Status register of the device is 0 prior to issue a command. If BSY bit is 1, the host should wait for issuing a command until BSY bit is cleared to Commands can be executed only when the DRDY bit of the Status register is 1.
Page 135: Read Sector(S) Command Protocol
Command Parameter write Status read Status read • • • • DRDY • • • • INTRQ Data transfer Expanded Command Min. 30 µs (*1) • • • INTRQ Data Reg. Selection • • • • Data • • • • •...
Page 136: Protocol For Command Abort
Note: For transfer of a sector of data, the host needs to read Status register (X'1F7') in order to clear INTRQ (interrupt) signal. The Status register should be read within a period from the DRQ setting by the device to 5 µs after the completion of the sector data transfer. Note that the host does not need to read the Status register for the reading of a single sector or the last sector in multiple-sector reading.
Page 137 D 7KH KRVW ZULWHV DQ\ UHTXLUHG SDUDPHWHUV WR WKH )HDWXUHV 6HFWRU &RXQW 6HFWRU 1XPEHU &\OLQGHUDQG'HYLFH+HDGUHJLVWHUV E 7KHKRVWZULWHVDFRPPDQGFRGHLQWKH&RPPDQGUHJLVWHU7KHGULYHVHWVWKH%6<ELWRIWKH 6WDWXVUHJLVWHU F :KHQWKHGHYLFHLVUHDG\WRUHFHLYHWKHGDWDRIWKHILUVWVHFWRUWKHGHYLFHVHWV'54ELWDQG FOHDUV%6<ELW G 7KHKRVWZULWHVRQHVHFWRURIGDWDWKURXJKWKH'DWDUHJLVWHU H 7KHGHYLFHFOHDUVWKH'54ELWDQGVHWVWKH%6<ELW I :KHQ WKH GULYH FRPSOHWHV WUDQVIHUULQJ WKH GDWD RI WKH VHFWRU WKH GHYLFH FOHDUV %6< ELW DQG DVVHUWV,1754VLJQDO,IWUDQVIHURIDQRWKHUVHFWRULVUHTXHVWHGWKHGULYHVHWVWKH'54ELW J $IWHUGHWHFWLQJWKH,1754VLJQDODVVHUWLRQWKHKRVWUHDGVWKH6WDWXVUHJLVWHU K 7KHGHYLFHUHVHWV,1754WKHLQWHUUXSWVLJQDO...
Page 138: Protocol For The Command Execution Without Data Transfer
Note: For transfer of a sector of data, the host needs to read Status register (X'1F7') in order to clear INTRQ (interrupt) signal. The Status register should be read within a period from the DRQ setting by the device to 5 µs after the completion of the sector data transfer. Note that the host does not need to read the Status register for the first and the last sector to be transferred.
Page 139: Other Commands
5.4.4 Other commands • READ MULTIPLE • SLEEP • WRITE MULTIPLE See the description of each command. 5.4.5 DMA data transfer commands • READ DMA • WRITE DMA Starting the DMA transfer command is the same as the READ SECTOR(S) or WRITE SECTOR(S) command except the point that the host initializes the DMA channel preceding the command issuance.
Page 140: Normal Dma Data Transfer
Command Status read Parameter write c, d • • DRDY INTRQ • • • • Data transfer Expanded [Multiword DMA transfer] • • • • • • • • DMARQ DMACK- • • • • IOR- or • • • • IOW- Word Figure 5.6...
Page 141: Ultra Dma Feature Set
Ultra DMA feature set 5.5.1 Overview Ultra DMA is a data transfer protocol used with the READ DMA and WRITE DMA commands. When this protocol is enabled it shall be used instead of the Multiword DMA protocol when these commands are issued by the host. This protocol applies to the Ultra DMA data burst only. When this protocol is used there are no changes to other elements of the ATA protocol (e.g.: Command Block Register access).
Page 142: Phases Of Operation
5.5.2 Phases of operation An Ultra DMA data transfer is accomplished through a series of Ultra DMA data in or data out bursts. Each Ultra DMA burst has three mandatory phases of operation: the initiation phase, the data transfer phase, and the Ultra DMA burst termination phase. In addition, an Ultra DMA burst may be paused during the data transfer phase (see 5.5.3 and 5.5.4 for the detailed protocol descriptions for each of these phases, 5.6 defines the specific timing requirements).
Page 143: The Data In Transfer
11) The device shall drive the first word of the data transfer onto DD (15:0). This step may occur when the device first drives DD (15:0) in step (10). 12) To transfer the first word of data the device shall negate DSTROBE within t after the host has negated STOP and asserted HDMARDY-.
Page 144: Terminating An Ultra Dma Data In Burst
The device shall stop generating DSTROBE edges within t of the host negating HDMARDY-. If the host negates HDMARDY- within t after the device has generated a DSTROBE edge, then the host shall be prepared to receive zero or one additional data words. If the host negates HDMARDY- greater than t after the device has generated a DSTROBE edge, then the host shall be prepared to receive zero, one or two additional data words.
Page 145 10) The device shall latch the host's CRC data from DD (15:0) on the negating edge of DMACK-. 11) The device shall compare the CRC data received from the host with the results of its own CRC calculation. If a miscompare error occurs during one or more Ultra DMA bursts for any one command, at the end of the command the device shall report the first error that occurred (see 5.5.5).
Page 146: Ultra Dma Data Out Commands
10) If the host has not placed the result of its CRC calculation on DD (15:0) since first driving DD (15:0) during (9), the host shall place the result of its CRC calculation on DD (15:0) (see 5.5.5). 11) The host shall negate DMACK- no sooner than t after the device has asserted DSTROBE and negated DMARQ and the host has asserted STOP and negated HDMARDY-, and no sooner than t...
Page 147: The Data Out Transfer
9) The device shall assert DDMARDY- within t after the host has negated STOP. After asserting DMARQ and DDMARDY- the device shall not negate either signal until after the first negation of HSTROBE by the host. 10) The host shall drive the first word of the data transfer onto DD (15:0). This step may occur any time during Ultra DMA burst initiation.
Page 148: Terminating An Ultra Dma Data Out Burst
b) Device pausing an Ultra DMA data out burst The device shall not pause an Ultra DMA burst until at least one data word of an Ultra DMA burst has been transferred. The device shall pause an Ultra DMA burst by negating DDMARDY-. The host shall stop generating HSTROBE edges within t of the device negating DDMARDY-.
Page 149 The device shall compare the CRC data received from the host with the results of its own CRC calculation. If a miscompare error occurs during one or more Ultra DMA bursts for any one command, at the end of the command, the device shall report the first error that occurred (see 5.5.5).
Page 150: Ultra Dma Crc Rules
11) The device shall compare the CRC data received from the host with the results of its own CRC calculation. If a miscompare error occurs during one or more Ultra DMA bursts for any one command, at the end of the command, the device shall report the first error that occurred (see 5.5.5).
Page 151 L 7KH&5&JHQHUDWRUSRO\QRPLDOLV*; ;;; 1RWH6LQFHQRELWFORFNLVDYDLODEOHWKHUHFRPPHQGHGDSSURDFKIRUFDOFXODWLQJ&5&LVWR XVH D ZRUG FORFN GHULYHG IURP WKH EXV VWUREH 7KH FRPELQDWLRQDO ORJLF VKDOO WKHQ EH HTXLYDOHQW WR VKLIWLQJ VL[WHHQ ELWV VHULDOO\ WKURXJK WKH JHQHUDWRU SRO\QRPLDO ZKHUH '' LV VKLIWHGLQILUVWDQG''LVVKLIWHGLQODVW 6HULHVWHUPLQDWLRQUHTXLUHGIRU8OWUD'0$ 6HULHVWHUPLQDWLRQUHVLVWRUVDUHUHTXLUHGDWERWKWKHKRVWDQGWKHGHYLFHIRURSHUDWLRQLQDQ\RIWKH 8OWUD'0$0RGHV7KHIROORZLQJWDEOHGHVFULEHVUHFRPPHQGHGYDOXHVIRUVHULHVWHUPLQDWLRQDW WKHKRVWDQGWKHGHYLFH 7DEOH 5HFRPPHQGHGVHULHVWHUPLQDWLRQIRU8OWUD'0$ 6LJQDO +RVW7HUPLQDWLRQ 'HYLFH7HUPLQDWLRQ...
Page 152: Pio Data Transfer Timing
Timing 5.6.1 PIO data transfer Figure 5.8 shows of the data transfer timing between the device and the host system. Addresses DIOR-/DIOW- Write data DD0-DD15 Read data DD0-DD15 IORDY Symbol Timing parameter Min. Max. Unit Cycle time — Data register selection setup time for DIOR-/DIOW- —...
Page 153: Multiword Dma Data Transfer Timing (Mode 2)
5.6.2 Multiword data transfer Figure 5.9 shows the multiword DMA data transfer timing between the device and the host system. DMARQ DMACK- DIOR-/DIOW- Write data DD0-DD15 Read data DD0-DD15 Symbol Timing parameter Min. Max. Unit Cycle time — Delay time from DMACK assertion to DMARQ negation —...
Page 154: Initiating An Ultra Dma Data In Burst
5.6.3 Ultra DMA data transfer Figures 5.10 through 5.19 define the timings associated with all phases of Ultra DMA bursts. Table 5.16 contains the values for the timings for each of the Ultra DMA Modes. 5.6.3.1 Initiating an Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.
Page 155: Ultra Dma Data Burst Timing Requirements
5.6.3.2 Ultra DMA data burst timing requirements Table 5.16 Ultra DMA data burst timing requirements (1 of 2) NAME MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 COMMENT (in ns) (in ns) (in ns) (in ns) (in ns) MAX (see Notes 1 and 2) Typical sustained average two cycle 2CYCTYP...
Page 156 Table 5.16 Ultra DMA data burst timing requirements (2 of 2) NAME MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 COMMENT (in ns) (in ns) (in ns) (in ns) (in ns) MAX (see Notes 1 and 2) Minimum time before driving ZIORDY IORDY Setup and hold times for DMACK-...
Page 157: Sustained Ultra Dma Data In Burst
5.6.3.3 Sustained Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. Note: DD (15:0) and DSTROBE are shown at both the host and the device to emphasize that cable setting time as well as cable propagation delay shall not allow the data signals to be considered stable at the host until some time after they are driven by the device.
Page 158: Host Pausing An Ultra Dma Data In Burst
5.6.3.4 Host pausing an Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. Notes: The host may assert STOP to request termination of the Ultra DMA burst no sooner than t after HDMARDY- is negated.
Page 159: Device Terminating An Ultra Dma Data In Burst
5.6.3.5 Device terminating an Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. Note: The definitions for the STOP, HDMARDY- and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. Figure 5.13 Device terminating an Ultra DMA data in burst 5 - 92 C141-E106-01EN...
Page 160: Host Terminating An Ultra Dma Data In Burst
5.6.3.6 Host terminating an Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. Note: The definitions for the STOP, HDMARDY- and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. Figure 5.14 Host terminating an Ultra DMA data in burst C141-E106-01EN 5 - 93...
Page 161: Initiating An Ultra Dma Data Out Burst
5.6.3.7 Initiating an Ultra DMA data out burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. Note: The definitions for the STOP, DDMARDY- and HSTROBE signal lines are not in effect until DMARQ and DMACK are asserted. Figure 5.15 Initiating an Ultra DMA data out burst 5 - 94 C141-E106-01EN...
Page 162: Sustained Ultra Dma Data Out Burst
5.6.3.8 Sustained Ultra DMA data out burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. Note: DD (15:0) and HSTROBE signals are shown at both the device and the host to emphasize that cable setting time as well as cable propagation delay shall not allow the data signals to be considered stable at the device until some time after they are driven by the host.
Page 163: Device Pausing An Ultra Dma Data Out Burst
5.6.3.9 Device pausing an Ultra DMA data out burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. Notes: The device may negate DMARQ to request termination of the Ultra DMA burst no sooner than t after DDMARDY- is negated.
Page 164: Host Terminating An Ultra Dma Data Out Burst
5.6.3.10 Host terminating an Ultra DMA data out burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. Note: The definitions for the STOP, DDMARDY- and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. Figure 5.18 Host terminating an Ultra DMA data out burst C141-E106-01EN 5 - 97...
Page 165: Device Terminating An Ultra Dma Data Out Burst
5.6.3.11 Device terminating an Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. Note: The definitions for the STOP, DDMARDY- and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. Figure 5.19 Device terminating an Ultra DMA data out burst 5 - 98 C141-E106-01EN...
Page 166: Power-On Reset Timing
5.6.4 Power-on and reset Figure 5.20 shows power-on and reset (hardware and software reset) timing. Only master device is present Clear Reset *1 Power-on RESET- Software reset DASP- *1: Reset means including Power-on-Reset, Hardware Reset (RESET-), and Software Reset. Master and slave devices are present (2-drives configuration) Clear Reset [Master device] DASP-...
Page 167 This page is intentionally left blank.
Page 168: Chapter 6 Operations
CHAPTER 6 OPERATIONS Device Response to the Reset Address Translation Power Save Defect Management Read-Ahead Cache Write Cache Device Response to the Reset This section describes how the PDIAG- and DASP- signals responds when the power of the IDD is turned on or the IDD receives a reset or diagnostic command. C141-E106-01EN 6 - 1...
Page 169: Response To Power-On
6.1.1 Response to power-on After the master device (device 0) releases its own power-on reset state, the master device shall check a DASP- signal for up to 450 ms to confirm presence of a slave device (device 1). The master device recognizes presence of the slave device when it confirms assertion of the DASP- signal.
Page 170: Response To Hardware Reset
6.1.2 Response to hardware reset Response to RESET- (hardware reset through the interface) is similar to the power-on reset. Upon receipt of hardware reset, the master device checks a DASP- signal for up to 450 ms to confirm presence of a slave device. The master device recognizes the presence of the slave device when it confirms assertion of the DASP- signal.
Page 171: Response To Software Reset
6.1.3 Response to software reset The master device does not check the DASP- signal for a software reset. If a slave device is present, the master device checks the PDIAG- signal for up to 31 seconds to see if the slave device has completed the self-diagnosis successfully.
Page 172: Response To Diagnostic Command
6.1.4 Response to diagnostic command When the master device receives an EXECUTE DEVICE DIAGNOSTIC command and the slave device is present, the master device checks the PDIAG- signal for up to 6 seconds to see if the slave device has completed the self-diagnosis successfully. The master device does not check the DASP- signal.
Page 173: Address Translation (Example In Chs Mode)
PARAMETERS command, the default values listed in Table 6.1 are used. This is called as the default translation mode. The parameters in Table 6.1 are called BIOS specification. Table 6.1 Default parameters MPF3102AH MPF3153AH MPF3204AH Number of cylinders 16,383 Parameters Number of head (logical)
Page 174 /RJLFDODGGUHVV &+6PRGH /RJLFDO DGGUHVV DVVLJQPHQW VWDUWV IURP SK\VLFDO F\OLQGHU 3& SK\VLFDO KHDG 3+ DQG SK\VLFDO VHFWRU 36 DQG LV DVVLJQHG E\ FDOFXODWLQJ WKH QXPEHU RI VHFWRUV SHU WUDFN ZKLFK LV VSHFLILHGE\WKH,1,7,$/,=('(9,&(3$5$0(7(56FRPPDQG7KHKHDGDGGUHVVLVDGYDQFHG DW WKH VXEVHTXHQW VHFWRU IURP WKH ODVW VHFWRU RI WKH FXUUHQW SK\VLFDO KHDG DGGUHVV 7KH ILUVW SK\VLFDO VHFWRU RI WKH VXEVHTXHQW SK\VLFDO VHFWRU LV WKH FRQVHFXWLYH ORJLFDO VHFWRU IURP WKH ODVW VHFWRURIWKHFXUUHQWSK\VLFDOVHFWRU )LJXUHVKRZVDQH[DPSOHDVVXPLQJWKHUHLVQRWUDFNVNHZ...
Page 175 /%$PRGH /RJLFDODGGUHVVDVVLJQPHQWLQWKH/%$PRGHVWDUWVIURPSK\VLFDOF\OLQGHUSK\VLFDOKHDGDQG SK\VLFDOVHFWRU7KHORJLFDODGGUHVVLVDGYDQFHGDWWKHVXEVHTXHQWVHFWRUIURPWKHODVWVHFWRURI WKH FXUUHQW WUDFN 7KH ILUVW SK\VLFDO VHFWRU RI WKH VXEVHTXHQW SK\VLFDO WUDFN LV WKH FRQVHFXWLYH ORJLFDOVHFWRUIURPWKHODVWVHFWRURIWKHFXUUHQWSK\VLFDOWUDFN )LJXUHVKRZVDQH[DPSOHRIDVVXPLQJWKHUHLVQRWUDFNVNHZ 3K\VLFDOVHFWRU 3K\VLFDOF\OLQGHU 3K\VLFDOKHDG...
Page 176 $FWLYHPRGH ,QWKLVPRGHDOOWKHHOHFWULFFLUFXLWLQWKHGHYLFHDUHDFWLYHRU WKH GHYLFH LV XQGHU VHHN UHDG RU ZULWHRSHUDWLRQ $GHYLFHHQWHUVWKHDFWLYHPRGHXQGHUWKHIROORZLQJFRQGLWLRQV $FRPPDQGZLWK6HHNRU:ULWHRU5HDGLVLVVXHG ,GOHPRGH ,QWKLVPRGHFLUFXLWVRQWKHGHYLFHLVVHWWRSRZHUVDYHPRGH 7KHGHYLFHHQWHUVWKH,GOHPRGHXQGHUWKHIROORZLQJFRQGLWLRQV $,'/(RU,'/(,00(',$7(FRPPDQGLVLVVXHGLQWKHDFWLYHRUVWDQGE\PRGH :KHQRQHRIWKH IROORZLQJ FRPPDQG LV LVVXHG WKH FRPPDQG LV H[HFXWHG QRUPDOO\ DQG WKH GHYLFHLVVWLOOVWD\HGLQWKHLGOHPRGH 5HVHWKDUGZDUHRUVRIWZDUH ,'/(FRPPDQG ,'/(,00(',$7(FRPPDQG $FRPPDQGZLWKRXW6HHNRU:ULWHRU5HDGLVLVVXHG 6WDQGE\PRGH ,QWKLVPRGHWKH9&0FLUFXLWLVWXUQHGRIIDQGWKHVSLQGOHPRWRULVVWRSSHG 7KHGHYLFHFDQUHFHLYHFRPPDQGVWKURXJKWKHLQWHUIDFH+RZHYHULIDFRPPDQGZLWKGLVNDFFHVV LVLVVXHGUHVSRQVHWLPHWRWKHFRPPDQGXQGHUWKHVWDQGE\PRGHWDNHVORQJHUWKDQWKHDFWLYHRU ,GOHPRGHEHFDXVHWKHDFFHVVWRWKHGLVNPHGLXPFDQQRWEHPDGHLPPHGLDWHO\ 7KHGULYHHQWHUVWKHVWDQGE\PRGHXQGHUWKHIROORZLQJFRQGLWLRQV $67$1'%<RU67$1'%<,00(',$7(FRPPDQGLVLVVXHGLQWKHDFWLYHRULGOHPRGH :KHQDXWRPDWLFSRZHUGRZQVHTXHQFHLVHQDEOHGWKHWLPHUKDVHODSVHG $UHVHWLVLVVXHGLQWKHVOHHSPRGH :KHQRQHRIIROORZLQJFRPPDQGVLVLVVXHGWKHFRPPDQGLVH[HFXWHGQRUPDOO\DQGWKHGHYLFHLV...
Page 177: Power Commands
• CHECK POWER MODE command Sleep mode The power consumption of the drive is minimal in this mode. The drive enters only the standby mode from the sleep mode. The only method to return from the standby mode is to execute a software or hardware reset.
Page 178 6SDUHDUHD )ROORZLQJWZRW\SHVRIVSDUHDUHDDUHSURYLGHGLQWKHXVHUVSDFH 6SDUHVHFWRUIRUVHFWRUVOLS XVHG IRU DOWHUQDWLQJ GHIHFWLYH VHFWRUV DW IRUPDWWLQJ LQ VKLSPHQW LQ FDVH WKDW D SK\VLFDO WUDFN FRQWDLQVRQHRUWZRGHIHFWLYHVHFWRUVVHFWRUVWUDFN 6SDUHF\OLQGHUIRUDOWHUQDWLYHDVVLJQPHQW XVHG IRU DOWHUQDWLYH DVVLJQPHQW IRU WKH WKLUG DQG VXEVHTXHQW GHIHFWLYH VHFWRUV LQ FDVH WKDW D SK\VLFDOWUDFNFRQWDLQVWKUHHRUPRUHGHIHFWLYHVHFWRUVDQGDOVRXVHGE\DXWRPDWLFDOWHUQDWLYH DVVLJQPHQWF\OLQGHUVGULYH $OWHUQDWLQJGHIHFWLYHVHFWRUV 7KHWZRDOWHUQDWLQJPHWKRGVGHVFULEHGEHORZDUHDYDLODEOH...
Page 179 $OWHUQDWHF\OLQGHUDVVLJQPHQW $GHIHFWLYHVHFWRULVDVVLJQHGWRWKHVSDUHVHFWRULQWKHDOWHUQDWHF\OLQGHU 7KLVSURFHVVLQJLVSHUIRUPHGZKHQDSK\VLFDOWUDFNFRQWDLQVWKUHHRUPRUHGHIHFWLYHVHFWRUVDQG ZKHQWKHDXWRPDWLFDOWHUQDWHSURFHVVLQJLVSHUIRUPHG )LJXUHVKRZVDQH[DPSOHZKHUHSK\VLFDOVHFWRULVGHWHFWLYHRQKHDGLQF\OLQGHU ,QGH[ 6HFWRUSK\VLFDO &\OLQGHU 'HIHFWLYH VHFWRU +HDG XQXVHG 6HFWRUORJLFDO $OWHUQDWH F\OLQGHU $OUHDG\ DVVLJQHG +HDG 'HIHFWLYHVHFWRULVDVVLJQHGWRXQDVVLJQHGVHFWRU DOWHUQDWHF\OLQGHUVDUHSURYLGHGIRUHDFKKHDGLQ]RQHLQQHUVLGH DOWHUQDWHF\OLQGHULVSURYLGHGLQRXWHUVLGH :KHQDQDFFHVVUHTXHVWWRVHFWRULVVSHFLILHGWKHGHYLFHDFFHVVHVWKHDOWHUQDWHGVHFWRULQWKH DOWHUQDWHF\OLQGHULQVWHDGRIVHFWRU:KHQDQDFFHVVUHTXHVWWRVHFWRUVQH[WWRVHFWRULV VSHFLILHGWKHGHYLFHVHHNVWRF\OLQGHUKHDGDQGFRQWLQXHVWKHSURFHVVLQJ )LJXUH $OWHUQDWHF\OLQGHUDVVLJQPHQW $XWRPDWLFDOWHUQDWHDVVLJQPHQW 7KHGHYLFHSHUIRUPVWKHDXWRPDWLFDVVLJQPHQWDWIROORZLQJFDVH :KHQ (&& FRUUHFWLRQ SHUIRUPDQFH LV LQFUHDVHG GXULQJ UHDG HUURU UHWU\ D UHDG HUURU LV UHFRYHUHG %HIRUHDXWRPDWLFDOWHUQDWHDVVLJQPHQWWKHGHYLFHSHUIRUPVUHZULWLQJWKHFRUUHFWHGGDWDWRWKH HUUHGVHFWRUDQGUHUHDGLQJ,IQRHUURURFFXUVDWUHUHDGLQJWKHDXWRPDWLFDOWHUQDWHDVVLJQPHQW...
Page 180 5HDG$KHDG&DFKH $IWHUDUHDGFRPPDQGZKLFKUHDGVWKHGDWDIURPWKHGLVNPHGLXPLVFRPSOHWHGWKHUHDGDKHDG FDFKH IXQFWLRQ UHDGV WKH VXEVHTXHQW GDWD EORFNV DXWRPDWLFDOO\ DQG VWRUHV WKH GDWD LQ WKH GDWD EXIIHU :KHQWKHQH[WFRPPDQGUHTXHVWVWRUHDGWKHUHDGDKHDGGDWDWKHGDWDFDQEHWUDQVIHUUHGIURPWKH GDWDEXIIHUZLWKRXWDFFHVVLQJWKHGLVNPHGLXP7KHKRVWFDQDFFHVVWKHGDWDDWKLJKHUVSHHG 'DWDEXIIHUFRQILJXUDWLRQ 7KHGHYLFHKDVD0%GDWDEXIIHU7KHEXIIHULVXVHGE\GLYLGHGLQWRWZRDQGRWKHUFRPPDQGV SDUWVIRU038ZRUNIRUUHDGFDFKHRIUHDGFRPPDQGVDQGRWKHUFRPPDQGVVHH)LJXUH 0%E\WHV IRU038ZRUN IRU5($'FRPPDQG IRU:5,7(FRPPDQG .% .% .% E\WHV E\WHV E\WHV )LJXUH 'DWDEXIIHUFRQILJXUDWLRQ 7KH UHDGDKHDG RSHUDWLRQ LV SHUIRUPHG DW H[HFXWLRQ RI WKH 5($' 6(&7256 5($' 08/7,3/( RU 5($' '0$ FRPPDQG DQG UHDGDKHDG GDWD DUH VWRUHG LQ WKH EXIIHU IRU UHDG FDFKH &((1...
Page 181: Caching Operation
6.5.2 Caching operation The caching operation is performed only at receipt of the following commands. The device transfers data from the data buffer to the host system if the following data exist in the data buffer. • All sector data to be processed by the command •...
Page 182: Usage Of Read Segment
6.5.3 Usage of read segment This subsection explains the usage of the read segment buffer at following cases. Miss-hit (no hit) A lead block of the read-requested data is not stored in the data buffer. The requested data is read from the disk media. 1) Sets the host address pointer (HAP) and the disk address pointer (DAP) to the sequential address to the last read segment.
Page 183 Sequential read When the disk drive receives the read command that targets the sequential address to the previous read command, the disk drive tries to fill the buffer space with the read ahead data. a. Sequential command just after non-sequential command At receiving the sequential read command, the disk drive sets the DAP and HAP to the sequential address of the last read command and reads the requested data.
Page 184 b. Sequential hit When the last sector address of the previous read command is sequential to the lead sector address of the received read command, the disk drive transfers the hit data in the buffer to the host system. The disk drive performs the read-ahead operation of the new continuous data to the empty area that becomes vacant by data transfer at the same time as the disk drive starts transferring data to the host system.
Page 185 Full hit (hit all) All requested data are stored in the data buffer. The disk drive starts transferring the requested data from the address of which the requested data is stored. After completion of command, a previously existed cache data before the full hit reading are still kept in the buffer, and the disk drive does not perform the read-ahead operation.
Page 186 1) The disk drive sets the HAP to the address where the partially hit data is stored, and sets the DAP to the address just after the partially hit data. Partially hit data Lack data 2) The disk drive starts transferring partially hit data and reads lack data from the disk media at the same time.
Page 187: Write Cache
Write Cache The write cache function of the drive makes a high speed processing in the case that data to be written by a write command is logically sequent the data of previous command and random write operation is performed. When the drive receives a write command, the drive starts transferring data of sectors requested by the host system and writing on the disk medium.
Page 188 At the time that the drive has stopped the command execution after the error recovery has failed, the write cache function is disabled automatically. The releasing the disable state can be done by the SET FEATURES command. When the power of the drive is turned on after the power is turned off once, the status of the write cache function returns to the default state.
Page 189 &RPPHQWVFRQFHUQLQJWKLVPDQXDOFDQEHGLUHFWHGWRRQHRIWKHIROORZLQJDGGUHVVHV )8-,768/,0,7(' )8-,768,&/(63$f$6$ %XVLQHVV3ODQQLQJ $OPDJUR0DGULG63$,1 6ROLG6TXDUH(DVW7RZHU 7(/ +RULNDZDFKR6DLZDLNX.DZDVDNL )$; -DSDQ 7(/ )8-,768$8675$/,$/,0,7(' )$; -XOLXV$YHQXH&QU'HOKL5RDG1RUWK5\GH16: $8675$/,$ )8-,768&20387(5352'8&762)$0(5,&$,1& 7(/ 2UFKDUG3DUNZD\6DQ-RVH )$; &DOLIRUQLD86$ 7(/ )8-,768+21*.21*/7' )$; )/LQFROQ+RXVH.LQJ¶V5RDG7DLNRR3ODFH,VODQG(DVW +21*.21* )8-,768&$1$'$,1& 7(/ 0DWKHVRQ%OYG(DVW0LVVLVVDXJD7RURQWR )$; 2QWDULR/:;&$1$'$ 7(/ )8-,768.25($/7'...
Page 190 )8-,768 /,0,7(' #0,/07 422039 472 :H ZRXOG DSSUHFLDWH \RXU FRPPHQWV DQG VXJJHVWLRQV IRU LPSURYLQJ WKLV SXEOLFDWLRQ 3XEOLFDWLRQ 1R 5HY /HWWHU 7LWOH &XUUHQW 'DWH +RZ GLG \RX XVH WKLV SXEOLFDWLRQ" ,V WKH PDWHULDO SUHVHQWHG HIIHFWLYHO\" /HDUQLQJ 6DOHV ,QVWDOOLQJ )XOO\ :HOO :HOO &OHDQ FRYHUHG ,OOXVWUDWHG...

Fujitsu MPF3204AH Product Manual

Chapter 1 Device Overview

Chapter 2 Device Configuration

Chapter 3 Installation Conditions

Chapter 4 Theory of Device Operation

Chapter 5 Interface

Chapter 6 Operations

Quick Links

DISK DRIVES

Related Manuals for Fujitsu MPF3204AH

Summary of Contents for Fujitsu MPF3204AH

Table of Contents