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Fujitsu MPG3XXXAH-E Product Manual

Fujitsu computer drive user manual
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MPG3xxxAH-E

DISK DRIVES

PRODUCT MANUAL
C141-E116-01EN

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Summary of Contents for Fujitsu MPG3XXXAH-E

  • Page 1: Disk Drives

    MPG3xxxAH-E DISK DRIVES PRODUCT MANUAL C141-E116-01EN...
  • Page 2 REVISION RECORD Edition Date published Revised contents Oct., 2000 Specification No.: C141-E116-**EN The contents of this manual is subject to change without prior notice. All Rights Reserved. Copyright 2000 FUJITSU LIMITED C141-E116-01EN...
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  • Page 4 MANUAL ORGANIZATION MPG3xxxAH-E • DEVICE OVERVIEW DISK DRIVES • DEVICE CONFIGURATION PRODUCT • INSTALLATION CONDITIONS MANUAL • THEORY OF DEVICE OPERATION (C141-E116) • INTERFACE <This manual> • OPERATIONS MPG3xxxAH-E • MAINTENANCE AND DIAGNOSIS DISK DRIVES • REMOVAL AND REPLACEMENT PROCEDURE...
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  • Page 6 This manual describes the MPG3xxxAH-E series, a 3.5-inch hard disk drive with a BUILT-IN controller that is compatible with the ATA interface. This manual explains, in detail, how to incorporate the hard disk drives into user systems. This manual assumes that users have a basic knowledge of hard disk drives and their application in computer systems.
  • Page 7 Conventions for Alert Messages This manual uses the following conventions to show the alert messages. An alert message consists of an alert signal and alert statements. The alert signal consists of an alert symbol and a signal word or just a signal word.
  • Page 8 "Disk drive defects" refers to defects that involve adjustment, repair, or replacement. Fujitsu is not liable for any other disk drive defects, such as those caused by user misoperation or mishandling, inappropriate operating environments, defects in the power supply or cable, problems of the host system, or other causes outside the disk drive.
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  • Page 10: Table Of Contents

    CHAPTER 1 DEVICE OVERVIEW...1 - 1 Features ...1 - 1 1.1.1 Functions and performance ...1 - 1 1.1.2 Adaptability...1 - 2 1.1.3 Interface...1 - 2 Device Specifications ...1 - 4 1.2.1 Specifications summary...1 - 4 1.2.2 Model and product number ...1 - 5 Power Requirements...1 - 5 Environmental Specifications...1 - 8 Acoustic Noise ...1 - 8...
  • Page 11 3.4.2 Cable connector specifications ...3 - 9 3.4.3 Device connection ...3 - 9 3.4.4 Power supply connector (CN1) ...3 - 10 3.4.5 System configuration for Ultra DMA...3 - 10 Jumper Settings ...3 - 13 3.5.1 Location of setting jumpers ...3 - 13 3.5.2 Factory default setting ...3 - 14 3.5.3...
  • Page 12 CHAPTER 5 INTERFACE ...5 - 1 Physical Interface ...5 - 2 5.1.1 Interface signals...5 - 2 5.1.2 Signal assignment on the connector...5 - 3 Logical Interface ...5 - 6 5.2.1 I/O registers...5 - 6 5.2.2 Command block registers ...5 - 8 5.2.3 Control block registers ...5 - 13 Host Commands ...5 - 13...
  • Page 13 5.6.3 Ultra DMA data transfer...5 - 97 5.6.3.1 Initiating an Ultra DMA data in burst...5 - 97 5.6.3.2 Ultra DMA data burst timing requirements ...5 - 98 5.6.3.3 Sustained Ultra DMA data in burst ...5 - 101 5.6.3.4 Host pausing an Ultra DMA data in burst ...5 - 102 5.6.3.5 Device terminating an Ultra DMA data in burst...5 - 103 5.6.3.6 Host terminating an Ultra DMA data in burst ...5 - 104 5.6.3.7 Initiating an Ultra DMA data out burst...5 - 105...
  • Page 14 3.19 Example (2) of Cable Select...3 - 15 Head structure ...4 - 2 MPG3xxxAH-E Block diagram ...4 - 5 Power-on operation sequence...4 - 7 Block diagram of servo control circuit ...4 - 13 Physical sector servo configuration on disk surface ...4 - 15 96 servo frames in each track ...4 - 17...
  • Page 15 Protocol for command abort...5 - 79 WRITE SECTOR(S) command protocol ...5 - 80 Protocol for the command execution without data transfer ...5 - 81 Normal DMA data transfer...5 - 83 Ultra DMA termination with pull-up or pull-down ...5 - 94 PIO data transfer timing ...5 - 95 Multiword DMA data transfer timing (mode 2) ...5 - 96 5.10...
  • Page 16 Specifications ...1 - 4 Model names and product numbers...1 - 5 Current and power dissipation...1 - 6 Environmental specifications ...1 - 8 Acoustic noise specification ...1 - 8 Shock and vibration specification...1 - 9 Surface temperature measurement points and standard values...3 - 6 Cable connector specifications ...3 - 9 Transfer rate of each zone ...4 - 12 Interface signals...5 - 2...
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  • Page 18: Chapter 1 Device Overview

    DEVICE OVERVIEW Overview and features are described in this chapter, and specifications and power requirement are described. The MPG3xxxAH-E series are a 3.5-inch hard disk drive with a built-in ATA controller. The disk drive is compact and reliable. Features 1.1.1...

  • Page 19: Adaptability

    Average positioning time Use of a rotary voice coil motor in the head positioning mechanism greatly increases the positioning speed. The average positioning time is 8.5 ms (at read). 1.1.2 Adaptability Power save mode The power save mode feature for idle operation, stand by and sleep modes makes the disk drive ideal for applications where power consumption is a factor.
  • Page 20 Error correction and retry by ECC If a recoverable error occurs, the disk drive itself attempts error recovery. The 40 bytes ECC has improved buffer error correction for correctable data errors. Write cache When the disk drive receives a write command, the disk drive posts the command completion at completion of transferring data to the data buffer completion of writing to the disk media.

  • Page 21: Device Specifications

    Device Specifications 1.2.1 Specifications summary Table 1.1 shows the specifications of the disk drive. MPG3204AH-E Formatted Capacity (*1) Number of Disks Number of Heads Number of Cylinders (User + Alternate & SA) Bytes per Sector Recording Method Track Density Bit Density Rotational Speed Average Latency Positioning time (Fast)

  • Page 22: Model And Product Number

    Model Formatted Capacity MPG3204AH-E 20,496 MB MPG3307AH-E 30,743 MB MPG3409AH-E 40,992 MB 1.2.2 Model and product number Table 1.2 lists the model names and product numbers. Table 1.2 Capacity Model Name (user area) MPG3204AH-E 20.49 GB MPG3307AH-E 30.74 GB MPG3409AH-E 40.99 GB Power Requirements Input Voltage...

  • Page 23: Current And Power Dissipation

    Current Requirements and Power Dissipation Table 1.3 lists the current and power dissipation. Table 1.3 Typical RMS current (*1) [mA] Mode of Operation Model 3204AH-E 3307AH-E Spin up 1950 peak Idle (Ready) (*3) R/W (On Track) (*4) Seek (Random) (*5) Standby Sleep Energy efficiency (rank) (*6)

  • Page 24: Current Fluctuation (Typ.) When Power Is Turned On

    Current fluctuation (Typ.) when power is turned on Note: Maximum current is 1.95A. Figure 1.1 Current fluctuation (Typ.) when power is turned on Power on/off sequence The voltage detector circuit monitors +5 V and +12 V. The circuit does not allow a write signal if either voltage is abnormal.

  • Page 25: Environmental Specifications

    Environmental Specifications Table 1.4 lists the environmental specifications. Table 1.4 Temperature • Operating • Non-operating • Thermal Gradient Humidity • Operating • Non-operating • Maximum Wet Bulb Altitude (relative to sea level) • Operating • Non-operating Acoustic Noise Table 1.5 lists the acoustic noise specification. Table 1.5 Sound Power per ISO 7779 and ISO9296...

  • Page 26: Shock And Vibration

    Shock and Vibration Table 1.6 lists the shock and vibration specification. Table 1.6 Vibration (swept sine, one octave per minute) • Operating • Non-operating Shock (half-sine pulse, Operating) • 2 ms duration Shock (half-sine pulse, Non-operating) • 2 ms duration Reliability Mean time between failures (MTBF) The mean time between failures (MTBF) is 500,000 POH (power on hours) or more (operation: 24...

  • Page 27: Error Rate

    Service life In situations where management and handling are correct, the disk drive requires no overhaul for five years when the DE surface temperature is less than 48°C. When the DE surface temperature exceeds 48°C, the disk drives requires no overhaul for five years or 20,000 hours of operation, whichever occurs first.

  • Page 28: Chapter 2 Device Configuration

    CHAPTER 2 DEVICE CONFIGURATION Device Configuration Figure 2.1 shows the disk drive. The disk drive consists of a disk enclosure (DE), read/write preamplifier, and controller PCA. The disk enclosure contains the disk media, heads, spindle motors actuators, and a circulating air filter. Figure 2.1 Device Configuration System Configuration...
  • Page 29 Disk The outer diameter of the disk is 95 mm. The inner diameter is 25 mm. The number of disks used varies with the model, as described below. operations. MPG3204AH-E: 1 disks MPG3307AH-E: 2 disks MPG3409AH-E: 2 disks Head The heads are of the contact start/stop (CSS) type. The head touches the disk surface while the disk is not rotating and automatically lifts when the disk starts.

  • Page 30: System Configuration

    System Configuration 2.2.1 ATA interface Figures 2.2 and 2.3 show the ATA interface system configuration. The drive has a 40-pin PC AT interface connector and supports the PIO transfer till 16.7 MB/s (PIO mode 4), the DMA transfer till 16.7 MB/s (Multiword DMA mode 2), the ultra DMA transfer till 66.6 MB/s (Ultra DMA mode 4), and the ultra DMA transfer till 100 MB/s (Ultra mode 5).
  • Page 31 IMPORTANT HA (host adapter) consists of address decoder, driver, and receiver. ATA is an abbreviation of "AT attachment". The disk drive is conformed to the ATA-5 interface. At high speed data transfer (PIO mode 3, mode 4, DMA mode 2, ultra DMA mode 4 or ultra DMA mode 5), occurrence of ringing or crosstalk of the signal lines (AT bus) between the HA and the disk drive may be a great cause of the obstruction of system reliability.

  • Page 32: Chapter 3 Installation Conditions

    CHAPTER 3 INSTALLATION CONDITIONS Dimensions Figure 3.1 illustrates the dimensions of the disk drive and positions of the mounting screw holes. All dimensions are in mm. Dimensions Handling Cautions Mounting Cable Connections Jumper Settings C141-E116-01EN 3 - 1...

  • Page 33: Dimensions

    Figure 3.1 Dimensions 3 - 2 C141-E116-01EN...

  • Page 34: Handling Cautions

    Handling Cautions Please keep the following cautions, and handle the HDD under the safety environment. 3.2.1 General notes Wrist strap Use the Wrist strap. Do not hit HDD each other. Do not place HDD vertically to avoid falling down. 3.2.2 Installation Please use the driver of a low impact when you use an electric driver.

  • Page 35: Mounting

    Mounting Direction Figure 3.3 illustrates normal direction for the disk drive. The disk drives can be mounted in any direction. Horizontal mounting with the PCB facing down Frame The disk enclosure (DE) body is connected to signal ground (SG) and the mounting frame is also connected to signal ground.

  • Page 36: Limitation Of Side-Mounting

    Figure 3.4 Bottom surface mounting Frame of system cabinet 4.5 or less Details of A Figure 3.5 Do not use this screw holes Limitation of side-mounting Side surface mounting Frame of system cabinet Screw 5.0 or less Details of B Mounting frame structure C141-E116-01EN Use these screw...

  • Page 37: Surface Temperature Measurement Points

    Ambient temperature The temperature conditions for a disk drive mounted in a cabinet refer to the ambient temperature at a point 3 cm from the disk drive. Pay attention to the air flow to prevent the DE surface temperature from exceeding 60°C. Provide air circulation in the cabinet such that the PCA side, in particular, receives sufficient cooling.

  • Page 38: Service Area

    Service area Figure 3.7 shows how the drive must be accessed (service areas) during and after installation. - Mounting screw hole [P side] - Cable connection - Mode setting switches External magnetic fields Avoid mounting the disk drive near strong magnetic sources such as loud speakers. Ensure that the disk drive is not affected by external magnetic fields.

  • Page 39: Cable Connections

    Cable Connections 3.4.1 Device connector The disk drive has the connectors and terminals listed below for connecting external devices. Figure 3.8 shows the locations of these connectors and terminals. Power supply connector (CN1) ATA interface connector (CN1) Power supply connector (CN1) Mode Setting Pins...

  • Page 40: Cable Connector Specifications

    Figure 3.9 shows how to connect the devices. ATA interface cable Host system Cable connector specifications Name Model FCN-707B040-AU/B FCN-707B040-AU/O 1-480424-0 60617-4 Power supply cable Disk Drive #0 Disk Drive #1 Figure 3.9 Cable connections C141-E116-01EN Manufacturer Fujitsu Fujitsu power supply 3 - 9...

  • Page 41: Power Supply Connector (Cn1)

    3.4.4 Power supply connector (CN1) Figure 3.10 shows the pin assignment of the power supply connector (CN1). (Viewed from cable side) Figure 3.10 Power supply connector pins (CN1) 3.4.5 System configuration for Ultra DMA Host system that support Ultra DMA transfer modes greater than mode 2 shall not share I/O ports. They shall provide separate drivers and separate receivers for each cable.

  • Page 42: Cable Configuration

    127.0 to 304.8 mm (5 to 12 inch) Pin 40 (Ground) open Pin 34 Pin 30 (Ground) Symbolizes Pin 34 Pin 26 (Ground) Conductor being cut Pin 24 (Ground) Pin 22 (Ground) Pin 19 (Ground) Pin 2 (Ground) System Board Connector Figure 3.11 Cable configuration b) Host system that do support Ultra DMA modes greater than mode 2 shall either connect...

  • Page 43: Cable Type Detection Using Cblid- Signal

    Host detected CBLID- above V PDIAG-: CBLID- conductor Host Device 1 with 40-conductor cable Figure 3.12 Cable type detection using CBLID- signal IDENTIFY DEVICE information word 93 bit13:0 Device detected CBLID- below V PDIAG-:CBLID- conductor 0.047 F ±10% or ±20% Host Device 1 with 40-conductor cable...

  • Page 44: Jumper Settings

    Jumper Settings 3.5.1 Location of setting jumpers Figure 3.14 shows the location of the jumpers to select drive configuration and functions. DC Power Connector Interface Connector Figure 3.14 Jumper location C141-E116-01EN 3 - 13...

  • Page 45: Factory Default Setting

    3.5.2 Factory default setting Figure 3.15 shows the default setting position at the factory. (Master device setting) DC Power Connector Figure 3.15 Factory default setting 3.5.3 Jumper configuration Device type Master device (device #0) or slave device (device #1) is selected. (a) Master device Figure 3.16 Jumper setting of master or slave device Note:...

  • Page 46: Jumper Setting Of Cable Select

    CSEL connected to the interface cable selection can be done by the special interface cable. Figure 3.17 Jumper setting of Cable Select Figures 3.18 and 3.19 show examples of cable selection using unique interface cables. By connecting the CSEL of the master device to the CSEL Line (conductor) of the cable and connecting it to ground further, the CSEL is set to low level.
  • Page 47 Special jumper settings (a) 2.1 GB clip (Limit capacity to 2.1 GB) / 33.8 GB clip (Limit capacity to 33.8 GB) If the drive cannot be recognized by system with legacy BIOS’s which do not allow single volume sizes greater than approximately 2.1 GB, the following jumper settings should be applied.

  • Page 48: Chapter 4 Theory Of Device Operation

    CHAPTER 4 THEORY OF DEVICE OPERATION This chapter explains basic design concepts of the disk drive. Also, this chapter explains subassemblies of the disk drive, each sequence, servo control, and electrical circuit blocks. Outline This chapter consists of two parts. First part (Section 4.2) explains mechanical assemblies of the disk drive.

  • Page 49: Head

    4.2.2 Head Figure 4.1 shows the read/write head structures. The Numerals 0 to 3 indicate read/write heads. These heads are raised from the disk surface as the spindle motor approaches the rated rotation speed. MPG3204AH-E S p i n d l e MPG3307AH-E / MPG3409AH-E S p i n d l e 4.2.3...

  • Page 50: Actuator

    4.2.4 Actuator The actuator consists of a voice coil motor (VCM) and a head carriage. The VCM moves the head carriage along the inner or outer edge of the disk. The head carriage position is controlled by feeding back the difference of the target position that is detected and reproduced from the servo information read by the read/write head.

  • Page 51: Circuit Configuration

    Circuit Configuration Figure 4.2 shows the disk drive circuit configuration. Read/write circuit The read/write circuit consists of two LSIs; read/write preamplifier (PreAMP) and read channel (RDC). The PreAMP consists of the write current switch circuit, that flows the write current to the head coil, and the voltage amplifier circuit, that amplitudes the read output from the head.

  • Page 52: Mpg3Xxxah-E Block Diagram

    ATA Interface HDC & MCU & RDC Data Buffer CL-SH8671 (Himalaya-2) SDRAM ARM7TDMI CL-SH7660 Flash ROM FROM Number-B Resonator HA13627 20MHz Temp. SP Motor Sensor R/W Pre-Amp HEAD Media SR1756 or M61850 Figure 4.2 MPG3xxxAH Block diagram C141-E116-01EN 4 - 5...

  • Page 53: Power-On Sequence

    Power-on Sequence Figure 4.3 describes the operation sequence of the disk drive at power-on. The outline is described below. a) After the power is turned on, the disk drive executes the MPU bus test, internal register read/write test, and work RAM read/write test. successfully, the disk drive starts the spindle motor.

  • Page 54: Power-On Operation Sequence

    Power on Start Self-diagnosis 1 • MPU bus test • Inner register write/read test • Work RAM write/read test The spindle motor starts. Self-diagnosis 2 • Data buffer write/read test Confirming spindle motor speed Release heads from actuator lock Initial on-track and read out of system information Execute self-calibration Drive ready state...

  • Page 55: Self-Calibration

    Self-calibration The disk drive occasionally performs self-calibration in order to sense and calibrate mechanical external forces on the actuator, and VCM torque. This enables precise seek and read/write operations. 4.5.1 Self-calibration contents Sensing and compensating for external forces The actuator suffers from torque due to the FPC forces and winds accompanying disk revolution. The torque vary with the disk drive and the cylinder where the head is positioned.

  • Page 56: Execution Timing Of Self-Calibration

    4.5.2 Execution timing of self-calibration Self-calibration is executed when: The power is turned on. The self-calibration execution timechart of the disk drive specifies self-calibration. The disk drive performs self-calibration according to the timechart based on the time elapsed from power-on. After power-on, self-calibration is performed about every 30 minutes, when the host command is not issued for 15 seconds.

  • Page 57: Read/Write Circuit

    Read/write Circuit The read/write circuit consists of the read/write preamplifier (PreAMP), the write circuit, the read circuit, and the synthesizer in the read channel (RDC). 4.6.1 Read/write preamplifier (PreAMP) One PreAMP is mounted on the FPC. The PreAMP consists of a 4-channel read preamplifier and a write current switch and senses a write error.

  • Page 58: Read Circuit

    4.6.3 Read circuit The head read signal from the PreAMP is regulated by the variable gain amplifier (VGA) circuit. Then the output is converted into the sampled read data pulse by the programmable filter circuit and the adaptive equalizer circuit. This clock signal is converted into the NRZ data by the 48/52 GCR decoder circuit based on the read data maximum-likelihood-detected by the Viterbi detection circuit, then is sent to the HDC.

  • Page 59: Synthesizer Circuit

    4.6.4 Synthesizer circuit The drive uses constant density recording to increase total capacity. This is different from the conventional method of recording data with a fixed data transfer rate at all data area. In the constant density recording method, data area is divided into zones by radius and the data transfer rate is set so that the recording density of the inner cylinder of each zone is nearly constant.

  • Page 60: Servo Control

    Servo Control The actuator motor and the spindle motor are submitted to servo control. The actuator motor is controlled for moving and positioning the head to the track containing the desired data. To turn the disk at a constant velocity, the actuator motor is controlled according to the servo data that is written on the data side beforehand.
  • Page 61 b. Move head to reference cylinder Drives the VCM to position the head at the any cylinder in the data area. The logical initial cylinder is at the outermost circumference (cylinder 0). c. Seek to specified cylinder Drives the VCM to position the head to the specified cylinder. d.

  • Page 62: Physical Sector Servo Configuration On Disk Surface

    Figure 4.5 Physical sector servo configuration on disk surface Servo burst capture circuit The four servo signals can be synchronously detected by the DEMOD signal (internal), full-wave rectified integrated. A/D converter (ADC) The A/D converter (ADC) receives the servo signals are integrated, converts them to digital, and transfers the digital signal to the DSP unit.

  • Page 63: Data-Surface Servo Format

    D/A converter (DAC) The D/A converter (DAC) converts the VCM drive current value (digital value) calculated by the DSP unit into analog values and transfers them to the power amplifier. Power amplifier The power amplifier feeds currents, corresponding to the DAC output signal voltage to the VCM. Spindle motor control circuit The spindle motor control circuit controls the sensor-less spindle motor.

  • Page 64: Servo Frame Format

    4.7.3 Servo frame format As the servo information, the drive uses the two-phase servo generated from the gray code and Pos A to D. This servo information is used for positioning operation of radius direction and position detection of circumstance direction. The servo frame consists of 5 blocks;...

  • Page 65: Actuator Motor Control

    Write/read recovery This area is used to absorb the write/read transient and to stabilize the AGC. Servo mark (ASM, SSM) This area generates a timing for demodulating the gray code and position-demodulating Pos A to D by detecting the servo mark. Preamble This area is used to synchronize with the PLL, which is used to search the SSM by detecting the ASM.

  • Page 66: Spindle Motor Control

    (called SVC hereafter). The firmware operates on the MPU manufactured by Fujitsu. The spindle motor is controlled by sending several signals from the MPU to the SVC. There are three modes for the spindle control;...
  • Page 67 d) During phase switching, the spindle motor starts rotating in low speed, and generates a counter electromotive force. The SVC detects this counter electromotive force and reports to the MPU using a PHASE signal for speed detection. e) The MPU is waiting for a PHASE signal. When no phase signal is sent for a specific period, the MPU resets the SVC and starts from the beginning.

  • Page 68: Chapter 5 Interface

    CHAPTER 5 INTERFACE Physical Interface Logical Interface Host Commands Command Protocol Ultra DMA feature set Timing C141-E116-01EN 5 - 1...

  • Page 69: Physical Interface

    Physical Interface 5.1.1 Interface signals Table 5.1 shows the interface signals. Description Cable select Chip select 0 Chip select 1 Data bus bit 0 Data bus bit 1 Data bus bit 2 Data bus bit 3 Data bus bit 4 Data bus bit 5 Data bus bit 6 Data bus bit 7...

  • Page 70: Signal Assignment On The Connector

    5.1.2 Signal assignment on the connector Table 5.2 shows the signal assignment on the interface connector. Table 5.2 Pin No. RESET– DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 DMARQ DIOW–, STOP DIOR–, HDMARDY–, HSTROBE IORDY, DDMARDY–, DSTROBE DMACK– INTRQ CS0–...
  • Page 71 [signal] [I/O] DIOR– HDMARDY– HSTROBE INTRQ CS0– CS1– DA 0-2 – PIDAG– CBLID– DASP– 5 - 4 [Description] DIOR– is the strobe signal asserted by the host to read device registers or the data port. HDMARDY– is a flow control signal for Ultra DMA data in bursts. This signal is asserted by the host to indicate to the device that the host is ready to receive Ultra DMA data in bursts.
  • Page 72 [signal] [I/O] IORDY This signal is negated to extend the host transfer cycle of any host register access (Read or Write) when the device is not ready to respond to a data transfer request. DDMARDY– DDMARDY– is a flow control signal for Ultra DMA data out bursts. This signal is asserted by the device to indicate to the host that the device is ready to receive Ultra DMA data out bursts.

  • Page 73: Logical Interface

    Logical Interface The device can operate for command execution in either address-specified mode; cylinder-head- sector (CHS) or Logical block address (LBA) mode. The IDENTIFY DEVICE information indicates whether the device supports the LBA mode. When the host system specifies the LBA mode by setting bit 6 in the Device/Head register to 1, HS3 to HS0 bits of the Device/Head register indicates the head No.

  • Page 74: Command Block Registers

    CS0– CS1– Command block registers Control block registers Notes: The Data register for read or write operation can be accessed by 16 bit data bus (DATA0 to DATA15). The registers for read or write operation other than the Data registers can be accessed by 8 bit data bus (DATA0 to DATA7).
  • Page 75 5.2.2 Command block registers Data register (X'1F0') The Data register is a 16-bit register for data block transfer between the device and the host system. Data transfer mode is PIO or LBA mode. Error register (X'1F1') The Error register indicates the status of the command executed by the device. The contents of this register are valid when the ERR bit of the Status register is 1.

  • Page 76: Diagnostic Code

    [Diagnostic code] X'01': No Error Detected. X'02': HDC Register Compare Error X'03': Data Buffer Compare Error. X'05': ROM Sum Check Error. X'80': Device 1 (slave device) Failed. Error register of the master device is valid under two devices (master and slave) configuration.
  • Page 77 Cylinder Low register (X'1F4') The contents of this register indicates low-order 8 bits of the starting cylinder address for any disk- access. At the end of a command, the contents of this register are updated to the current cylinder number. Under the LBA mode, this register indicates LBA bits 15 to 8.
  • Page 78 Status register (X'1F7') The contents of this register indicate the status of the device. The contents of this register are updated at the completion of each command. When the BSY bit is cleared, other bits in this register should be validated within 400 ns. When the BSY bit is 1, other bits of this register are invalid.
  • Page 79 - Bit 3: Data Request (DRQ) bit. This bit indicates that the device is ready to transfer data of word unit or byte unit between the host system and the device. - Bit 2: Always 0. - Bit 1: Always 0. - Bit 0: Error (ERR) bit.

  • Page 80: Host Commands

    5.2.3 Control block registers Alternate Status register (X'3F6') The Alternate Status register contains the same information as the Status register of the command block register. The only difference from the Status register is that a read of this register does not imply Interrupt Acknowledge and INTRQ signal is not reset.

  • Page 81: Command Code And Parameters

    5.3.1 Command code and parameters Table 5.4 lists the supported commands, command code and the registers that needed parameters are written. Table 5.4 Command name READ SECTOR(S) READ MULTIPLE READ DMA READ VERIFY SECTOR(S) WRITE MULTIPLE WRITE DMA WRITE VERIFY WRITE SECTOR(S) RECALIBRATE SEEK...
  • Page 82 Table 5.4 Command name STANDBY IMMEDIATE SLEEP CHECK POWER MODE SMART FLUSH CACHE SECURITY DISABLE PASSWORD SECURITY ERASE PREPARE SECURITY ERASE UNIT SECURITY FREEZE LOCK SECURITY SET PASSWORD SECURITY UNLOCK SET MAX ADDRESS READ NATIVE MAX ADDRESS Notes: FR : Features Register SC : Sector Count Register SN : Sector Number Register R: R = 0 or 1...

  • Page 83: Command Descriptions

    5.3.2 Command descriptions The contents of the I/O registers to be necessary for issuing a command and the example indication of the I/O registers at command completion are shown as following in this subsection. Example: READ SECTOR(S) At command issuance (I/O registers setting contents) (CM) (DH) (CH)
  • Page 84 Note: When the L bit is specified to 1, the lower 4 bits of the DH register and all bits of the CH, CL and SN registers indicate the LBA bits (bits of the DH register are the MSB (most significant bit) and bits of the SN register are the LSB (least significant bit).
  • Page 85 At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) *1 If the command is terminated due to an error, the remaining number of sectors of which data was not transferred is set in this register. READ MULTIPLE (X'C4') This command operates similarly to the READ SECTOR(S) command.

  • Page 86: Execution Example Of Read Multiple Command

    Figure 5.1 shows an example of the execution of the READ MULTIPLE command. Block count specified by SET MULTIPLE MODE command = 4 (number of sectors in a block) READ MULTIPLE command specifies; Number of requested sectors = 9 (Sector Count register = 9) Number of sectors in incomplete block = remainder of 9/4 =1 Command Issue Parameter...
  • Page 87 READ DMA (X'C8' or X'C9') This command operates similarly to the READ SECTOR(S) command except for following events. The data transfer starts at the timing of DMARQ signal assertion. The device controls the assertion or negation timing of the DMARQ signal. The device posts a status as the result of command execution only once at completion of the data transfer.
  • Page 88 At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) *1 If the command is terminated due to an error, the remaining number of sectors of which data was not transferred is set in this register. READ VERIFY SECTOR(S) (X'40' or X'41') This command operates similarly to the READ SECTOR(S) command except that the data is not transferred to the host system.
  • Page 89 At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) *1 If the command is terminated due to an error, the remaining number of sectors of which data was not transferred is set in this register. WRITE SECTOR(S) (X'30' or X'31') This command writes data of sectors from the address specified in the Device/Head, Cylinder High, Cylinder Low, and Sector Number registers to the address specified in the Sector Count...
  • Page 90 At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) *1 If the command is terminated due to an error, the remaining number of sectors of which data was not transferred is set in this register. WRITE MULTIPLE (X'C5') This command is similar to the WRITE SECTOR(S) command.
  • Page 91 The contents of the command block registers related to addresses after the transfer of a data block containing an erred sector are undefined. To obtain a valid error information, the host should retry data transfer as an individual requests. At command issuance (I/O registers setting contents) (CM) (DH) (CH)
  • Page 92 1) Multiword DMA transfer mode 2: Sets the FR register = X'03' and SC register = X'22' by the SET FEATURES command 2) Ultra DMA transfer mode 2: Sets the FR register = X'03' and SC register = X'42' by the SET FEATURES command At command issuance (I/O registers setting contents) (CM) (DH)
  • Page 93 At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) *1 If the command is terminated due to an error, the remaining number of sectors of which data was not transferred is set in this register. RECALIBRATE (X'1x', x: X'0' to X'F') This command performs the calibration.
  • Page 94 (10) SEEK (X'7x', x : X'0' to X'F') This command performs a seek operation to the track and selects the head specified in the command block registers. After completing the seek operation, the device clears the BSY bit in the Status register and generates an interrupt. The IDD always sets the DSC bit (Drive Seek Complete status) of the Status register to 1.
  • Page 95 (11) INITIALIZE DEVICE PARAMETERS (X'91') The host system can set the number of sectors per track and the maximum head number (maximum head number is "number of heads minus 1") per cylinder with this command. Upon receipt of this command, the device sets the BSY bit of Status register and saves the parameters. Then the device clears the BSY bit and generates an interrupt.

  • Page 96: Information To Be Read By Identify Device Command

    At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) Table 5.5 Information to be read by IDENTIFY DEVICE command (1 of 6) Word Value X‘045A’...
  • Page 97 Table 5.5 Information to be read by IDENTIFY DEVICE command (2 of 6) Word Value (Variable) Number of current Cylinders (Variable) Number of current Head (Variable) Number of current sectors per track 57-58 (Variable) Total number of current sectors Transfer sector count currently set by READ/WRITE MULTIPLE command 60-61 Total number of user addressable sectors (LBA mode only) X‘0000’...
  • Page 98 Word 23-26: Firmware revision; ASCII code (8 characters, Left-justified) Word 27-46: Model number; ASCII code (40 characters, Left-justified), remainder filled with blank code (X'20') One of the following model numbers; Fujitsu MPG3204AH-E Fujitsu MPG3307AH-E Fujitsu MPG3409AH-E Word 49: Capabilities Bit 15-14:...
  • Page 99 Table 5.5 Information to be read by IDENTIFY DEVICE command (4 of 6) *12 Word 63: Multiword DMA transfer mode Bit 15-11: Reserved Bit 10: 1 = Multiword DMA mode 2 is selected 0 = Multiword DMA mode 2 is not selected Bit 9: 1 = Multiword DMA mode 1 is selected 0 = Multiword DMA mode 1 is not selected...
  • Page 100 Table 5.5 Information to be read by IDENTIFY DEVICE command (5 of 6) Bit 4: Removable Media Status Notification feature set supported = 0 Bit 3: Advanced Power Management feature set supported = 1 Bit 2: CFA feature set supported = 0 Bit 1: READ/WRITE DMA QUEUED supported = 0 Bit 0:...
  • Page 101 Table 5.5 Information to be read by IDENTIFY DEVICE command (6 of 6) *20 Word 89: Time required for SECURITY ERASE UNIT command to complete. MPG3204AH-E = 0004H: 8 minutes MPG3307AH-E = 0006H: 12minutes MPG3409AH-E = 0008H: 16 minutes *21 Word 93: Hardware reset result. The contents of bits 12-0 of this word shall change only during the execution of a hardware reset.
  • Page 102 (13) IDENTIFY DEVICE DMA (X'EE') When this command is not used to transfer data to the host in DMA mode, this command functions in the same way as the Identify Device command. At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL)

  • Page 103: Features Register Values And Settable Modes

    Table 5.6 Features Register X‘02’ Enables the write cache function. X‘03’ Specifies the transfer mode. Supports PIO mode 4, single word DMA mode 2, and multiword DMA mode regardless of Sector Count register contents. X‘04’ No operation. X‘05’ Enable the advanced power management function. X‘33’...
  • Page 104 At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) The host sets X'03' to the Features register. By issuing this command with setting a value to the Sector Count register, the transfer mode can be selected.
  • Page 105 Subcommand code 42h allows the host to enable the Automatic Acoustic Management feature set. To enable the Automatic Acoustic Management feature set, the host writes the Sector Count register with the requested automatic acoustic management level and executes a SET FEATURES command with subcommand code 42h.
  • Page 106 At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) After power-on or after hardware reset, the READ MULTIPLE and WRITE MULTIPLE command operation are disabled as the default mode.
  • Page 107 Both devices shall execute self-diagnosis. The device 0 waits for up to 5 seconds until device 1 asserts the PDIAG- signal. If the device 1 does not assert the PDIAG- signal but indicates an error, the device 0 shall append X‘80’ to its own diagnostic status. The device 0 clears the BSY bit of the Status register and generates an interrupt.
  • Page 108 (17) FORMAT TRACK (X'50') Upon receipt of this command, the device sets the DRQ bit and waits the completion of 512-byte format parameter transfer from the host system. After completion of transfer, the device clears the DRQ bits, sets the BSY bit. However the device does not perform format operation, but the drive clears the BYS bit and generates an interrupt soon.
  • Page 109 The command is issued in a sequence of the READ LONG or WRITE LONG (to the same address) command issuance. (WRITE LONG command can be continuously issued after the READ LONG command.) If above condition is not satisfied, the command operation is not guaranteed. At command issuance (I/O registers setting contents) (CM) (DH)
  • Page 110 At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) (21) WRITE BUFFER (X'E8') The host system can overwrite the contents of the sector buffer of the device with a desired data pattern by issuing this command. Upon receipt of this command, the device sets the BSY bit of the Status register.
  • Page 111 (22) IDLE (X'97' or X'E3') Upon receipt of this command, the device sets the BSY bit of the Status register, and enters the idle mode. Then, the device clears the BSY bit, and generates an interrupt. The device generates an interrupt even if the device has not fully entered the idle mode.
  • Page 112 At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) (23) IDLE IMMEDIATE (X'95' or X'E1') Upon receipt of this command, the device sets the BSY bit of the Status register, and enters the idle mode.
  • Page 113 (24) STANDBY (X'96' or X'E2') Upon receipt of this command, the device sets the BSY bit of the Status register and enters the standby mode. The device then clears the BSY bit and generates an interrupt. The device generates an interrupt even if the device has not fully entered the standby mode. If the device has already spun down, the spin-down sequence is not implemented.
  • Page 114 At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) (26) SLEEP (X'99' or X'E6') This command is the only way to make the device enter the sleep mode. Upon receipt of this command, the device sets the BSY bit of the Status register and enters the sleep mode.
  • Page 115 At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) (27) CHECK POWER MODE (X'98' or X'E5') The host checks the power mode of the device with this command. The host system can confirm the power save mode of the device by analyzing the contents of the Sector Count and Sector Number registers.
  • Page 116 At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) (28) SMART (X'B0) This command performs operations for device failure predictions according to a subcommand specified in the FR register.

  • Page 117: Features Register Values (Subcommands) And Functions

    Table 5.8 Features Register values (subcommands) and functions (1/2) Features Resister X’D0’ SMART Read Attribute Values: A device that received this subcommand asserts the BSY bit and saves all the updated attribute values. The device then clears the BSY bit and transfers 512-byte attribute value information to the host.
  • Page 118 Table 5.8 Features Register values (subcommands) and functions (2/2) X’D5’ SMART Read Logging Data: This subcommand is used to transfer logging data that transfer length specified in SC register is to the host. The setting of SN register is described Log Sector Address below. When SN register is set 00h, 01h, or 06h, SC register should be set to 01h.
  • Page 119 The host must regularly issue the SMART Read Attribute Values subcommand (FR register = D0h), SMART Save Attribute Values subcommand (FR register = D3h), or SMART Return Status subcommand (FR register = DAh) to save the device attribute value data on a medium. Alternative, the device must issue the SMART Enable-Disable Attribute AutoSave subcommand (FR register = D2h) to use a feature which regularly save the device attribute value data to a medium.

  • Page 120: Device Attribute Data Structure

    Table 5.9 Device attribute data structure Byte (Hex) Data structure revision number *1 attribute to 30 attribute Off-line data collection status *7 Off-line data collection Self Test execution status byte *8 Off-line data collection executing times (sec) Reserved Off-line data collection capability *9 SMART capability flag *10 Drive error logging capability *11 Self Test failure checkpoint...

  • Page 121: Warranty Failure Threshold Data Structure

    Table 5.10 Warranty failure threshold data structure Byte (Hex) Data structure revision number *1 drive threshold to 30 threshold Reserved Vendor unique Check sum *1 Data structure revision number It indicates the revision number of device attribute and warranty failure threshold. They will have the same “Data structure revision number”.
  • Page 122 *2 Attribute ID The attribute ID is defined as follows: Attribute ID (Dec) (Indicates unused attribute data) Read error rate Throughput performance Spin up time Number of times the spindle motor is activated Number of alternative sectors Read channel margin (Not supported) Seek error rate Seek time performance Power-on time...
  • Page 123 *3 Status flag 6 to 15 *4 Normalized attribute value The current attribute value is the normalized raw attribute data. The value varies between 01h and 64h. The closer the value gets to 01h, the higher the possibility of a failure. The device compares the attribute values with thresholds.
  • Page 124 *7 Off-line data collection status Values 00h or 80h Off-line data collection is not started. 01h or 81h Reserved 02h or 82h Off-line data collection has been completed without error. 03h or 83h Reserved 04h or 84h Off-line data collection has been suspended by an interrupt command from the host.
  • Page 125 *9 Off-line data collection capability [16Fh] 5 to 7 SMART capability flag [170-171h] 2-15 Drive error logging capability [172h] 1 to 15 Quick Test completion time [minutes] This value indicates the processing time of the Quick Test (off-line mode). Comprehensive Test completion time [minutes] This value indicates the processing time of the Comprehensive Test (off-line mode).

  • Page 126: Log Directory Data Structure

    Attribute threshold The limit of a varying attribute value. The host compares the attribute values with the thresholds to identify a failure. Table 5.11 Log directory data structure Address (Hex) 00 to 01 SMART logging version Number of sectors for Log Sector Address 01h 03 to 0B Reserved Number of sectors for Log Sector Address 06h...

  • Page 127: Error Logging Data Structure

    Table 5.12 Error logging data structure Address (Hex) SMART error logging version 01h Index pointer of latest error data structure 02 to 31 Error log data stucture 1 3A to 3D 46 to 58 5C to 1C3 Error log data structure 2-5 Total error count 1C6 to 1FE...

  • Page 128: Self Test Log Data Structure

    Table 5.13 Self Test log data structure Byte 0 to 1 Data Structure Revision Number = 0x0001 1st Descriptor Entry Self Test Number Self Test Execution Status 4 to 5 Life time power on hours Self Test Error No. 7 to 10 Error LBA 11 to 25 Vender Specific bytes...
  • Page 129 (29) FLUSH CACHE (X ‘E7’) This command is use by the host to request the device to flush the write cache. If the write cache is to be flushed, all data cached shall be written to the media. The BSY bit shall remain set to one until all data has been successfully written or an error occurs.

  • Page 130: Contents Of Security Password

    (30) SECURITY DISABLE PASSWORD (F6h) This command invalidates the user password already set and releases the lock function. The host transfers the 512-byte data shown in Table5.14 to the device. The device compares the user password or master password in the transferred data with the user password or master password already set, and releases the lock function if the passwords are the same.
  • Page 131 At command issuance (I-O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I-O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) (31) SECURITY ERASE PREPARE (F3h) The SECURITY ERASE UNIT command feature is enabled by issuing the SECURITY ERASE PREPARE command and then the SECURITY ERASE UNIT command.
  • Page 132 At command issuance (I-O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I-O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) (32) SECURITY ERASE UNIT (F4h) This command erases all user data. This command also invalidates the user password and releases the lock function.
  • Page 133 At command issuance (I-O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I-O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) (33) SECURITY FREEZE LOCK (F5h) This command puts the device into FROZEN MODE. The following commands used to change the lock function return the Aborted Command error if the device is in FROZEN MODE.
  • Page 134 READ DMA READ LONG READ MULTIPLE READ SECTORS READ VERIFY WRITE DMA At command issuance (I-O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I-O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) (34)

  • Page 135: Contents Of Security Set Password Data

    Table 5.15 Contents of SECURITY SET PASSWORD data Word 1 to 16 17 to 255 Table 5.16 Relationship between combination of Identifier and Security level, and operation of the lock function Indentifier Level User High Master High User Maximum Master Maximum 5 - 68 Contents...
  • Page 136 At command issuance (I-O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I-O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) (35) SECURITY UNLOCK (F2h) This command cancels LOCKED MODE. The host transfers the 512-byte data shown in Table 5.14 to the device. Operation of the device varies as follows depending on whether the host specifies the master password or user password.
  • Page 137 At command issuance (I-O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I-O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) (36-1) SET MAX ADDRESS (F9) This command allows the maximum address accessible by the user to be set in LBA or CHS mode. Upon receipt of the command, the device sets the BSY bit and saves the maximum address specified in the DH, CH, CL and SN registers.
  • Page 138 At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) (36-2) SET MAX SET PASSWORD (F9) This command requests a transfer of single sector of data from the host, and defines the content of this sector of information.
  • Page 139 At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) SET MAX SET PASSWORD data content Word 1 - 16 17 - 255 (36-3) SET MAX LOCK (F9) After this command is completed any other Set Max commands except SET MAX UNLOCK and SET MAX FREEZE LOCK are rejected.
  • Page 140 (36-4) SET MAX UNLOCK (F9) This command requests a transfer of a single sector of data from the host. The password supplied in the sector of data transferred shall be compared with the stored SET MAX password. If the password compare fails, then the device returns command aborted and decrements the unlock counter.
  • Page 141 SET MAX ADDRESS SET MAX SET PASSWORD SET MAX LOCK SET MAX UNLOCK At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER)
  • Page 142 At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH) Max. cylinder [MSB]/Max. LBA (CL) Max. cylinder [LSB]/Max. LBA (SN) Max. sector/Max. LBA [LSB] (SC) (ER) Error information C141-E116-01EN Max head/LBA [MSB] 5 - 75...

  • Page 143: Error Posting

    5.3.3 Error posting Table 5.17 lists the defined errors that are valid for each command. Table 5.17 Command code and parameters Command name READ SECTOR(S) WRITE SECTOR(S) READ MULTIPLE WRITE MULTIPLE READ DMA WRITE DMA WRITE VERIFY READ VERIFY SECTOR(S) RECALIBRATE SEEK INITIALIZE DEVICE PARAMETERS...

  • Page 144: Command Protocol

    Command Protocol The host should confirm that the BSY bit of the Status register of the device is 0 prior to issue a command. If BSY bit is 1, the host should wait for issuing a command until BSY bit is cleared to Commands can be executed only when the DRDY bit of the Status register is 1.

  • Page 145: Read Sector(S) Command Protocol

    Command Parameter write DRDY INTRQ Data transfer Expanded Command Min. 30 s (*1) INTRQ Data Reg. Selection Data IOR- Word IOCS16- *1 When the IDD receives a command that hits the cache data during read-ahead, and transfers data from the buffer without reading from the disk medium. Figure 5.2 Even if the error status exists, the drive makes a preparation (setting the DRQ bit) of data transfer.

  • Page 146: Data Transferring Commands From Host To Device

    Note: For transfer of a sector of data, the host needs to read Status register (X'1F7') in order to clear INTRQ (interrupt) signal. The Status register should be read within a period from the DRQ setting by the device to 5 s after the completion of the sector data transfer. Note that the host does not need to read the Status register for the reading of a single sector or the last sector in multiple-sector reading.

  • Page 147: Write Sector(S) Command Protocol

    a) The host writes any required parameters to the Features, Sector Count, Sector Number, Cylinder, and Device/Head registers. b) The host writes a command code in the Command register. The drive sets the BSY bit of the Status register. c) When the device is ready to receive the data of the first sector, the device sets DRQ bit and clears BSY bit.

  • Page 148: Commands Without Data Transfer

    Note: For transfer of a sector of data, the host needs to read Status register (X'1F7') in order to clear INTRQ (interrupt) signal. The Status register should be read within a period from the DRQ setting by the device to 5 s after the completion of the sector data transfer. Note that the host does not need to read the Status register for the first and the last sector to be transferred.

  • Page 149: Other Commands

    5.4.4 Other commands READ MULTIPLE SLEEP WRITE MULTIPLE See the description of each command. 5.4.5 DMA data transfer commands READ DMA WRITE DMA Starting the DMA transfer command is the same as the READ SECTOR(S) or WRITE SECTOR(S) command except the point that the host initializes the DMA channel preceding the command issuance.

  • Page 150: Normal Dma Data Transfer

    Command Parameter write c, d DRDY INTRQ Data transfer Expanded [Multiword DMA transfer] DMARQ DMACK- IOR- or IOW- Word Figure 5.6 • • • • • • • • • • • • • • • • • • • • • • Normal DMA data transfer C141-E116-01EN Status read...

  • Page 151: Ultra Dma Feature Set

    Ultra DMA feature set 5.5.1 Overview Ultra DMA is a data transfer protocol used with the READ DMA and WRITE DMA commands. When this protocol is enabled it shall be used instead of the Multiword DMA protocol when these commands are issued by the host. This protocol applies to the Ultra DMA data burst only. When this protocol is used there are no changes to other elements of the ATA protocol (e.g.: Command Block Register access).

  • Page 152: Phases Of Operation

    5.5.2 Phases of operation An Ultra DMA data transfer is accomplished through a series of Ultra DMA data in or data out bursts. Each Ultra DMA burst has three mandatory phases of operation: the initiation phase, the data transfer phase, and the Ultra DMA burst termination phase. In addition, an Ultra DMA burst may be paused during the data transfer phase (see 5.5.3 and 5.5.4 for the detailed protocol descriptions for each of these phases, 5.6 defines the specific timing requirements).

  • Page 153: The Data In Transfer

    11) The device shall drive the first word of the data transfer onto DD (15:0). This step may occur when the device first drives DD (15:0) in step (10). 12) To transfer the first word of data the device shall negate DSTROBE within t has negated STOP and asserted HDMARDY-.

  • Page 154: Terminating An Ultra Dma Data In Burst

    The device shall stop generating DSTROBE edges within t HDMARDY-. If the host negates HDMARDY- within t edge, then the host shall be prepared to receive zero or one additional data words. If the host negates HDMARDY- greater than t edge, then the host shall be prepared to receive zero, one or two additional data words.
  • Page 155 10) The device shall latch the host's CRC data from DD (15:0) on the negating edge of DMACK-. 11) The device shall compare the CRC data received from the host with the results of its own CRC calculation. If a miscompare error occurs during one or more Ultra DMA bursts for any one command, at the end of the command the device shall report the first error that occurred (see 5.5.5).

  • Page 156: Ultra Dma Data Out Commands

    10) If the host has not placed the result of its CRC calculation on DD (15:0) since first driving DD (15:0) during (9), the host shall place the result of its CRC calculation on DD (15:0) (see 5.5.5). 11) The host shall negate DMACK- no sooner than t DSTROBE and negated DMARQ and the host has asserted STOP and negated HDMARDY-, and no sooner than t calculation on DD (15:0).

  • Page 157: The Data Out Transfer

    9) The device shall assert DDMARDY- within t asserting DMARQ and DDMARDY- the device shall not negate either signal until after the first negation of HSTROBE by the host. 10) The host shall drive the first word of the data transfer onto DD (15:0). This step may occur any time during Ultra DMA burst initiation.

  • Page 158: Terminating An Ultra Dma Data Out Burst

    b) Device pausing an Ultra DMA data out burst The device shall not pause an Ultra DMA burst until at least one data word of an Ultra DMA burst has been transferred. The device shall pause an Ultra DMA burst by negating DDMARDY-. The host shall stop generating HSTROBE edges within t DDMARDY-.
  • Page 159 The device shall compare the CRC data received from the host with the results of its own CRC calculation. If a miscompare error occurs during one or more Ultra DMA bursts for any one command, at the end of the command, the device shall report the first error that occurred (see 5.5.5).

  • Page 160: Ultra Dma Crc Rules

    11) The device shall compare the CRC data received from the host with the results of its own CRC calculation. If a miscompare error occurs during one or more Ultra DMA bursts for any one command, at the end of the command, the device shall report the first error that occurred (see 5.5.5).

  • Page 161: Series Termination Required For Ultra Dma

    i) The CRC generator polynomial is : G (X) = X16 + X12 + X5 + 1. Note: Since no bit clock is available, the recommended approach for calculating CRC is to use a word clock derived from the bus strobe. The combinational logic shall then be equivalent to shifting sixteen bits serially through the generator polynomial where DD0 is shifted in first and DD15 is shifted in last.

  • Page 162: Pio Data Transfer Timing

    Timing 5.6.1 PIO data transfer Figure 5.8 shows of the data transfer timing between the device and the host system. Addresses DIOR-/DIOW- Write data DD0-DD15 Read data DD0-DD15 IORDY Symbol Timing parameter Cycle time Data register selection setup time for DIOR-/DIOW- Pulse width of DIOR-/DIOW- Recovery time of DIOR-/DIOW- Data setup time for DIOW-...

  • Page 163: Multiword Data Transfer

    5.6.2 Multiword data transfer Figure 5.9 shows the multiword DMA data transfer timing between the device and the host system. DMARQ DMACK- DIOR-/DIOW- Write data DD0-DD15 Read data DD0-DD15 Symbol Timing parameter Cycle time Delay time from DMACK assertion to DMARQ negation Pulse width of DIOR-/DIOW- Data setup time for DIOR- Data hold time for DIOR-...

  • Page 164: Ultra Dma Data Transfer

    5.6.3 Ultra DMA data transfer Figures 5.10 through 5.19 define the timings associated with all phases of Ultra DMA bursts. Table 5.19 contains the values for the timings for each of the Ultra DMA Modes. 5.6.3.1 Initiating an Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.

  • Page 165: 5.6.3.2 Ultra Dma Data Burst Timing Requirements

    5.6.3.2 Ultra DMA data burst timing requirements Table 5.19 Ultra DMA data burst timing requirements (1 of 2) MODE 0 MODE 1 MODE 2 (in ns) (in ns) (in ns) NAME MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX 2CYCTYP 2CYC DZFS...
  • Page 166 Table 5.19 Ultra DMA data burst timing requirements (2 of 2) MODE 0 MODE 1 MODE 2 (in ns) (in ns) (in ns) NAME MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN IORDYZ ZIORDY *1: Except for some instances of t that apply to host signals only, the parameters t recipient-to-sender interlocks, i.e., one agent (either sender or recipient) is waiting for the other agent to respond with a signal before proceeding.

  • Page 167: Ultra Dma Sender And Recipient Timing Requirements

    Table 5.20 Ultra DMA sender and recipient timing requirements MODE 0 MODE 1 MODE 2 (in ns) (in ns) (in ns) NAME MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX 14.7 DSIC DHIC 72.9 50.9 33.9 DVSIC DVHIC *1: The correct data value shall be captured by the recipient given input data with a slew rate of 0.4 V/ns rising and falling and the...

  • Page 168: Sustained Ultra Dma Data In Burst

    5.6.3.3 Sustained Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. DSTROBE at device DVHIC DD(15:0) at device DSTROBE at host DHIC DD(15:0) at host Note: DD (15:0) and DSTROBE signals are shown at both the host and the device to emphasize that cable setting time as well as cable propagation delay shall not allow the data signals to be considered stable at the host until some time after they are driven by the device.

  • Page 169: Host Pausing An Ultra Dma Data In Burst

    5.6.3.4 Host pausing an Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. DMARQ (device) DMACK- (host) STOP (host) HDMARDY- (host) DSTROBE (device) DD(15:0) (device) Notes: The host may assert STOP to request termination of the Ultra DMA burst no sooner than after HDMARDY- is negated.

  • Page 170: 5.6.3.5 Device Terminating An Ultra Dma Data In Burst

    5.6.3.5 Device terminating an Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. DMARQ (device) DMACK- (host) STOP (host) HDMARDY- (host) DSTROBE (device) DD(15:0) DA0, DA1, DA2, CS0-, CS1- Note: The definitions for the STOP, HDMARDY- and DSTROBE signal lines are no longer in effect after DMARQ and DMACK- are negated.

  • Page 171: Host Terminating An Ultra Dma Data In Burst

    5.6.3.6 Host terminating an Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. DMARQ (device) DMACK- (host) STOP (host) HDMARDY- (host) DSTROBE (device) DD(15:0) DA0, DA1, DA2, CS0, CS1 Note: The definitions for the STOP, HDMARDY- and DSTROBE signal lines are no longer in effect after DMARQ and DMACK- are negated.

  • Page 172: 5.6.3.7 Initiating An Ultra Dma Data Out Burst

    5.6.3.7 Initiating an Ultra DMA data out burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. DMARQ (device) DMACK- (host) STOP (host) DDMARDY- (device) HSTROBE (host) DD(15:0) (host) DA0, DA1, DA2 CS0-, CS1- Note: The definitions for the STOP, DDMARDY- and HSTROBE signal lines are not in effect until DMARQ and DMACK- are asserted.

  • Page 173: Sustained Ultra Dma Data Out Burst

    5.6.3.8 Sustained Ultra DMA data out burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. HSTROBE at host DVHIC DD(15:0) at host HSTROBE at device DHIC DD(15:0) at device Note: DD (15:0) and HSTROBE signals are shown at both the device and the host to emphasize that cable setting time as well as cable propagation delay shall not allow the data signals to be considered stable at the device until some time after they are driven by the host.

  • Page 174: Device Pausing An Ultra Dma Data Out Burst

    5.6.3.9 Device pausing an Ultra DMA data out burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. DMARQ (device) DMACK- (host) STOP (host) DDMARDY- (device) HSTROBE (host) DD(15:0) (host) Notes: The device may negate DMARQ to request termination of the Ultra DMA burst no sooner than t after DDMARDY- is negated.

  • Page 175: Host Terminating An Ultra Dma Data Out Burst

    5.6.3.10 Host terminating an Ultra DMA data out burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. DMARQ (device) DMACK- (host) STOP (host) DDMARDY- (device) HSTROBE (host) DD(15:0) (host) DA0, DA1, DA2 CS0-, CS1- Note: The definitions for the STOP, DDMARDY- and HSTROBE signal lines are no longer in effect after DMARQ and DMACK- are negated.

  • Page 176: Device Terminating An Ultra Dma Data Out Burst

    5.6.3.11 Device terminating an Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. DMARQ (device) DMACK- (host) STOP (host) DDMARDY- (device) HSTROBE (host) DD(15:0) (host) DA0, DA1, DA2, CS0-, CS1- Note: The definitions for the STOP, DDMARDY- and HSTROBE signal lines are no longer in effect after DMARQ and DMACK- are negated.

  • Page 177: Power-On And Reset

    5.6.4 Power-on and reset Figure 5.20 shows power-on and reset (hardware and software reset) timing. Only master device is present Power-on RESET- Software reset DASP- *1: Reset means including Power-on-Reset, Hardware Reset (RESET-), and Software Reset. Master and slave devices are present (2-drives configuration) [Master device] DASP- [Slave device]...

  • Page 178: Chapter 6 Operations

    CHAPTER 6 OPERATIONS Device Response to the Reset This section describes how the PDIAG- and DASP- signals responds when the power of the IDD is turned on or the IDD receives a reset or diagnostic command. Device Response to the Reset Address Translation Power Save Defect Management...

  • Page 179: Response To Power-On

    6.1.1 Response to power-on After the master device (device 0) releases its own power-on reset state, the master device shall check a DASP- signal for up to 450 ms to confirm presence of a slave device (device 1). The master device recognizes presence of the slave device when it confirms assertion of the DASP- signal.

  • Page 180: Response To Hardware Reset

    6.1.2 Response to hardware reset Response to RESET- (hardware reset through the interface) is similar to the power-on reset. Upon receipt of hardware reset, the master device checks a DASP- signal for up to 450 ms to confirm presence of a slave device. The master device recognizes the presence of the slave device when it confirms assertion of the DASP- signal.

  • Page 181: Response To Software Reset

    6.1.3 Response to software reset The master device does not check the DASP- signal for a software reset. If a slave device is present, the master device checks the PDIAG- signal for up to 31 seconds to see if the slave device has completed the self-diagnosis successfully.

  • Page 182: Response To Diagnostic Command

    6.1.4 Response to diagnostic command When the master device receives an EXECUTE DEVICE DIAGNOSTIC command and the slave device is present, the master device checks the PDIAG- signal for up to 6 seconds to see if the slave device has completed the self-diagnosis successfully. The master device does not check the DASP- signal.

  • Page 183: Address Translation

    Address Translation When the IDD receives any command which involves access to the disk medium, the IDD always implements the address translation from the logical address (a host-specified address) to the physical address (logical to physical address translation). Following subsections explains the CHS translation mode. 6.2.1 Default parameters In the logical to physical address translation, the logical cylinder, head, and sector addresses are...

  • Page 184: Logical Address

    6.2.2 Logical address CHS mode Logical address assignment starts from physical cylinder (PC) 0, physical head (PH) 0, and physical sector (PS) 1 and is assigned by calculating the number of sectors per track which is specified by the INITIALIZE DEVICE PARAMETERS command. The head address is advanced at the subsequent sector from the last sector of the current physical head address.

  • Page 185: Power Save

    LBA mode Logical address assignment in the LBA mode starts from physical cylinder 0, physical head 0, and physical sector 1. The logical address is advanced at the subsequent sector from the last sector of the current track. The first physical sector of the subsequent physical track is the consecutive logical sector from the last sector of the current physical track.
  • Page 186 Active mode In this mode, all the electric circuit in the device are active or the device is under seek, read or write operation. A device enters the active mode under the following conditions: A command with Seek or Write or Read is issued. Idle mode In this mode, circuits on the device is set to power save mode.

  • Page 187: Power Commands

    CHECK POWER MODE command Sleep mode The power consumption of the drive is minimal in this mode. The drive enters only the standby mode from the sleep mode. The only method to return from the standby mode is to execute a software or hardware reset.

  • Page 188: Spare Area

    6.4.1 Spare area Following two types of spare area are provided in the user space. 1) Spare sector for sector slip: used for alternating defective sectors at formatting in shipment (128 sectors/32 cylinders) 2) Spare cylinder for alternative assignment: used by automatic alternative assignment. (4 cylinders/drive) 6.4.2 Alternating defective sectors The two alternating methods described below are available:...

  • Page 189: Alternate Cylinder Assignment

    Alternate cylinder assignment A defective sector is assigned to the spare sector in the alternate cylinder. This processing is performed when a physical track contains three or more defective sectors, and when the automatic alternate processing is performed. Figure 6.8 shows an example where (physical) sector 5 is detective on head 0 in cylinder 0. Index Sector (physical) Cylinder 0...

  • Page 190: Read-Ahead Cache

    Read-Ahead Cache After a read command which reads the data from the disk medium is completed, the read-ahead cache function reads the subsequent data blocks automatically and stores the data in the data buffer. When the next command requests to read the read-ahead data, the data can be transferred from the data buffer without accessing the disk medium.

  • Page 191: Caching Operation

    6.5.2 Caching operation The caching operation is performed only at receipt of the following commands. The device transfers data from the data buffer to the host system if the following data exist in the data buffer. All sector data to be processed by the command A part of data including the starting sector to be processed by the command When a part of data to be processed exist in the data buffer, the remaining data are read from the disk medium and are transferred to the host system.

  • Page 192: Usage Of Read Segment

    6.5.3 Usage of read segment This subsection explains the usage of the read segment buffer at following cases. Miss-hit (no hit) A lead block of the read-requested data is not stored in the data buffer. The requested data is read from the disk media.
  • Page 193 Sequential read When the disk drive receives the read command that targets the sequential address to the previous read command, the disk drive tries to fill the buffer space with the read ahead data. a. Sequential command just after non-sequential command At receiving the sequential read command, the disk drive sets the DAP and HAP to the sequential address of the last read command and reads the requested data.
  • Page 194 b. Sequential hit When the last sector address of the previous read command is sequential to the lead sector address of the received read command, the disk drive transfers the hit data in the buffer to the host system. The disk drive performs the read-ahead operation of the new continuous data to the empty area that becomes vacant by data transfer at the same time as the disk drive starts transferring data to the host system.
  • Page 195 Full hit (hit all) All requested data are stored in the data buffer. The disk drive starts transferring the requested data from the address of which the requested data is stored. After completion of command, a previously existed cache data before the full hit reading are still kept in the buffer, and the disk drive does not perform the read-ahead operation.
  • Page 196 1) The disk drive sets the HAP to the address where the partially hit data is stored, and sets the DAP to the address just after the partially hit data. Partially hit data 2) The disk drive starts transferring partially hit data and reads lack data from the disk media at the same time.

  • Page 197: Write Cache

    Write Cache The write cache function of the drive makes a high speed processing in the case that data to be written by a write command is logically sequent the data of previous command and random write operation is performed. When the drive receives a write command, the drive starts transferring data of sectors requested by the host system and writing on the disk medium.
  • Page 198 At the time that the drive has stopped the command execution after the error recovery has failed, the write cache function is disabled automatically. The releasing the disable state can be done by the SET FEATURES command. When the power of the drive is turned on after the power is turned off once, the status of the write cache function returns to the default state.
  • Page 199 8F, Hun Tai Center, 168-170, Tun Hwa North Road, 1st Sec., Taipei, TAIWAN TEL: 886-2-545-7700 FAX: 886-2-717-4644 FUJITSU SYSTEMS BUSINESS (MALAYSIA) SDN. BHD. Fujitsu Plaza, 1A, Jalan Tandang 204, P.O. Box 636 Pejabat Pos Jalan Sultan 46770 Petaling Jaya, Selangor Darul Ehsan, Malaysia TEL: 60-3-793-3888 FAX: 60-3-793-0888 FUJITSU SYSTEMS BUSINESS (THAILAND) LTD.
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