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MVME2300-Series VME Processor Module Installation and Use V2300A/IH2...
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Motorola, Inc. assumes no liability resulting from any omissions in this document, or from the use of the information obtained therein. Motorola reserves the right to revise this document and to make changes from time to time in the content hereof without obligation of Motorola to notify any person of such revision or changes.
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MPC603 or MPC604 PowerPC microprocessor, and features dual PCI Mezzanine Card (PMC) slots with front panel and/or P2 I/O. The MVME2300 is currently available in the following conÞgurations: Model Memory MVME2301 MPC603 16MB ECC DRAM @ 200 MHz MVME2302 32MB ECC DRAM...
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This manual is intended for anyone who wants to design OEM systems, supply additional capability to an existing compatible system, or work in a lab environment for experimental purposes. A basic knowledge of computers and digital logic is assumed. Document Terminology Throughout this manual, a convention is used which precedes data and address parameters by a character identifying the numeric format as follows: Dollar...
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Motorola, Inc. assumes no liability for the customer's failure to comply with these requirements. The safety precautions listed below represent warnings of certain dangers of which Motorola is aware. You, as the user of the product, should follow these warnings and all other safety precautions necessary for the safe operation of the equipment in your operating environment.
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ßammability rating of 94V-0. The computer programs stored in the Read Only Memory of this device contain material copyrighted by Motorola Inc., 1995, and may be used only under a license such as those contained in MotorolaÕs software licenses.
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¨ Motorola and the Motorola symbol are registered trademarks of Motorola, Inc. PowerPCª is a trademark of International Business Machines Corporation and is used by Motorola with permission. All other products mentioned in this document are trademarks or registered trademarks of their respective holders.
1Preparing and Installing the MVME2300-Series Module Introduction This chapter provides a brief description of the MVME2300-Series VME Processor Module, and instructions for preparing and installing the hardware. In this manual, the name MVME230x refers to all models of the MVME2300-series boards, unless otherwise specified. MVME230x Description The MVME2300-series VME processor module is a PCI Mezzanine Card (PMC) carrier board.
PCI expansion mezzanine modules that each support up to two PMCs. It occupies a single VMEmodule slot, except when optional PCI expansion mezzanine modules are also used: Table 1-1. MVME230x Models MVME230x Type MVME2301 MPC603 16MB ECC DRAM @ 200 MHz MVME2302 32MB ECC DRAM...
MVME230x Description In addition, there are 64 pins of I/O from PMC slot 1 and 46 pins of I/O from PMC slot 2 that are routed to P2. The two PMC slots may contain two single-wide PMCs or one double-wide PMC. PMCspan Expansion Mezzanine An optional PCI expansion mezzanine module or PMC carrier board, PMCspan, provides the capability of adding two additional...
Preparing and Installing the MVME2300-Series Module VMEsystem Enclosure Your MVME230x board must be installed in a VMEsystem chassis with both P1 and P2 backplane connections. It requires a single slot, except when PMCspan carrier boards are used. Allow one extra slot for each PMCspan.
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Overview of Start-Up Procedures Table 1-3. Start-Up Overview (Continued) What you need to do ... Refer to ... On page ... Prepare the PMCspan PMCspan 1-14 module(s). For additional information on PMCspan, refer to the PMCspan PMC Adapter Carrier Module Installation and Use manual, listed in Appendix A, Ordering Related Documentation.
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Preparing and Installing the MVME2300-Series Module Table 1-3. Start-Up Overview (Continued) What you need to do ... Refer to ... On page ... Connect any other optional Connector Pin Assignments devices or equipment you will For more information on optional be using.
The MVME230x control registers are briefly described in Chapter 4, with additional information in the MVME2300-Series VME Processor Module Programmer's Reference Guide as listed in the table Motorola Computer Group Documents in Appendix A, Ordering Related Documents.
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Preparing and Installing the MVME2300-Series Module Some options, however, are not software-programmable. Such options are controlled through manual installation or removal of header jumpers or interface modules on the MVME230x or the associated modules. Figure 1-1 illustrates the placement of the switches, jumper headers, connectors, and LED indicators on the MVME230x.
Preparing and Installing the MVME2300-Series Module Setting the Flash Memory Bank A/Bank B Reset Vector Header (J15) Bank B consists of 1 MB of 8-bit Flash memory in two 32-pin PLCC 8-bit sockets. Bank A consists of four 16-bit Smart Voltage SMT devices that can be populated with 8Mbit Flash devices (4 MB) or 4Mbit Flash devices (2 MB).
Preparing the MVME230x Hardware Automatic System Controller System Controller Enabled System Controller Disabled (factory configuration) Setting the General-Purpose Software-Readable Header (J17) Header J17 provides eight readable jumpers. These jumpers can be read as a register at ISA I/O address $801 (hexadecimal). Bit 0 is associated with header pins 1 and 2;...
Preparing and Installing the MVME2300-Series Module PPCBug INSTALLED Bit 0 (SRH0) Reserved for future use Bit 1 (SRH1) Setup parameter source (In=Flash; Out=NVRAM) Bit 2 (SRH2) Reserved for future use Bit 3 (SRH3) Reserved for future use Bit 4 (SRH4) Reserved for future use Bit 5 (SRH5) Reserved for future use...
MVME230x into a VME chassis, and connecting an optional system console terminal. Taking ESD Precautions Motorola strongly recommends that you use an antistatic wrist Use ESD strap and a conductive foam pad when installing or upgrading a system. Electronic components, such as disk drives, computer boards, and memory modules, can be extremely sensitive to Electro-Static Discharge (ESD).
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Preparing and Installing the MVME2300-Series Module 1. Attach an ESD strap to your wrist. Attach the other end of the ESD strap to the chassis as a ground. The ESD strap must be secured to your wrist and to ground throughout the procedure.
Installing the MVME230x Hardware 2064 9708 Figure 1-3. Typical Single-width PMC Module Placement on MVME230x 5. Slide the edge connector(s) of the PMC module into the front panel opening(s) from behind and place the PMC module on top of the MVME230x. The four connectors on the underside of the PMC module should then connect smoothly with the corresponding connectors for a single-width PMC (J11/J12/J13/J14 or J21/J22/J23/J24, all eight for a double-...
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Preparing and Installing the MVME2300-Series Module was furnished with the PMCspan, and that you have installed the selected PMCs on the PMCspan according to the instructions given in the PMCspan and PMC manuals. 1. Attach an ESD strap to your wrist. Attach the other end of the ESD strap to the chassis as a ground.
Preparing and Installing the MVME2300-Series Module 4. Attach the four standoffs to the MVME230x module. For each standoff: Ð Insert the threaded end into the standoff hole at each corner of the VME processor module. Ð Thread the locking nuts onto the standoff tips. Ð...
Installing the MVME230x Hardware 2065 9708 Figure 1-5. PMCspan-010 Installation onto a PMCspan-002/MVME230x 1-19...
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Preparing and Installing the MVME2300-Series Module 2. Perform an operating system shutdown. Turn the AC or DC power off and remove the AC cord or DC power lines from the system. Remove chassis or system cover(s) as necessary for access to the VME module card cage. Inserting or removing modules with power applied may result in damage to module components.
Installing the MVME230x Hardware MVME230 x Before installing the MVME230x into your VME chassis, ensure that the jumpers on the MVME230x J15, J16, and J17 headers are configured, as previously described. This procedure assumes that you have already installed the PMCspan(s) if desired, and any PMCs that you have selected.
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5. Secure the MVME230x (and PMCspans if used) in the chassis with the screws provided, making good contact with the transverse mounting rails to minimize RF emissions. Some VME backplanes (e.g., those used in Motorola Note ÒModular ChassisÓ systems) have an auto-jumpering feature for automatic propagation of the IACK and BG signals.
Installing the MVME230x Hardware 8. Replace the chassis or system cover(s), cable peripherals to the panel connectors as appropriate, reconnect the system to the AC or DC power source, and turn the equipment power 9. The MVME230xÕs green LED indicates activity as a set of confidence tests is run, and the debugger prompt PPC1-Bug>...
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Preparing and Installing the MVME2300-Series Module Multiple MVME230x boards may be installed in a single VME chassis. Each must have a unique Universe address, selected by setting jumpers on its J17 header, as described in Preparing the MVME230x. In general, hardware multiprocessor features are supported.
2Operating Instructions Introduction This chapter provides information about powering up the MVME230x system, and functionality of the switches, status indicators, and I/O ports on the front panels of the MVME230x and PMCspan modules. Applying Power After you have verified that all necessary hardware preparation has been done, that all connections have been made correctly, and that the installation is complete, you can power up the system.
Operating Instructions Power-up/reset initialization STARTUP Initialize devices on the MVME230x INITIALIZATION module/system Power On Self Test diagnostics POST Firmware-configured boot mechanism, BOOTING if so configured. Default is no boot. Interactive, command-driven on-line PowerPC MONITOR debugger, when terminal connected. MVME230 x The front panel of the MVME230x module is shown on a following page.
MVME230x ABT (S1) When activated by software, the Abort switch, , can generate an interrupt signal from the base board to the processor at a user- programmable level. The interrupt is normally used to abort program execution and return control to the debugger firmware located in the MVME230x Flash memory.
Operating Instructions Status Indicators MVME There are four LED (light-emitting diode) status 230x indicators located on the MVME230x front panel.: , and BFL, CPU PMC2 PMC1 BFL (DS1) The yellow LED indicates board failure; lights when the BRDFAIL* signal line is active. CPU (DS2) The green LED indicates CPU activity;...
MVME230x DEBUG Port The RJ45 port labeled on the front panel of the MVME230x DEBUG supplies the MVME230x serial communications interface, implemented via a UART PC16550 controller chip from National Semiconductor. It is asynchronous only. This serial port is configured for EIA-232-D DTE, as shown in Figure 2-1. port may be used for connecting a terminal to the DEBUG MVME230x to serve as the firmware console for the factory...
Operating Instructions PMC Slots Two openings located on the front panel provide I/O expansion by allowing access to one or two 4-port single-wide or one 8-port double-wide PCI Mezzanine Card (PMC), connected to the PMC connectors on the MVME230x. For pin assignments for the PMC connectors, refer to Appendix C.
PMCspan PMCspan A PMCspan front panel is pictured at the right. The front panel is the same for all PMCspan models. There are two PMC slots, labeled PCI MEZZANINE , which support either two single-wide PMCs CARD or one double-wide PMC. The PMCspan board has two sets of three 32-bit connectors for PMC interface to secondary PCI bus and user-specific I/O.
The following table summarizes the features of the MVME230x VME processor module. Table 3-1. MVME230x Features Feature Description 200 MHZ MPC603 PowerPC processor (MVME2301 - 2304 models) Microprocessor 300 MHZ MPC604 PowerPC processor (MVME2305 - 2308 models) Form factor 6U VMEbus...
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Features Table 3-1. MVME230x Features (Continued) Feature Description 8KB NVRAM with RTC and battery backup (SGS-Thomson Real-time clock M48T59/T559) Switches Reset ) and abort (RST (ABT) Status LEDs Four: Board fail (one for PMC slot 2, one for slot 1) (BFL) One 16-bit timer in W83C553 ISA bridge;...
Functional Description General Description The MVME230x is a VME processor module equipped with a PowerPCª 603 or 604 microprocessor. As shown in the Features section, the MVME230x offers many standard features desirable in a computer systemÑincluding Ethernet and debug ports, Boot ROM, Flash memory, DRAM, and interface for two PCI Mezzanine Cards (PMCs), contained in a one- slot VME package.
Functional Description The PowerPC 603 is a 64-bit processor with 16KB on-chip caches (16KB data cache and 16KB instruction cache). The PowerPC 604 is a 64-bit processor with 32 KB on-chip caches (32KB data cache and 32KB instruction cache). The Raven bridge controller ASIC provides the bridge between the PowerPC microprocessor bus and the PCI local bus.
Block Diagram The following table shows the access timings for various types of transfers initiated by a 60X system bus master to PCI: Table 3-3. PowerPC 60x Bus to PCI Access Timing System Clock Periods Required For: Total Access Type Clocks 1st Beat 2nd Beat...
Block Diagram There are one or two blocks of DRAMs that provides 16M/32M or 64M/128M of ECC DRAM. The DRAM blocks consists of 9 devices each. Either 1Mx16 (Page) 50-pin TSOPII DRAM or 4Mx16 (EDO) 50-pin TSOPII DRAM are used to provide 16/32/64/128M. When populated, these blocks appears as Block A and Block B to the Falcon chipset.
Functional Description Table 3-5. PowerPC 60x Bus to DRAM Access Timing using 60ns Page Devices Clock Periods Required for: Total Access Type Clocks 1st Beat 2nd Beat 3rd Beat 4th Beat 4-Beat Read after Idle (Quad-word aligned) 4-Beat Read after Idle (Quad-word misaligned) 4-Beat Read after 4-Beat Read 11/7...
Block Diagram If all blocks of DRAMs are 50ns, EDO devices then the latency times for the ECC memory would be as follows: Table 3-6. PowerPC 60x Bus to DRAM Access Timing Using 50ns, EDO Devices Clock Periods Required for: Total Access Type Clocks...
Functional Description Flash Memory The MVME230x base board has provision for up to 5 MB of Flash memory. Bank B consists of 1 MB of 8-bit Flash memory in two 32-pin PLCC 8-bit sockets. Bank A consists of four 16-bit Smart Voltage SMT devices that can be populated with 8Mbit Flash devices (4 MB) or 4Mbit Flash devices (2 MB).
Block Diagram Flash Latency There is one 16-bit port bank of Flash on the MVME230x. The access times for this bank are shown in the following table. Table 3-7.PowerPC 60x Bus to FLASH Access Timing for Bank B (16-bit Port) Clock Periods Required for: Total Access type...
Functional Description 08003E2xxxxx is stored in NVRAM. The MVME230x debugger, PPCBug, has the capability to retrieve the Ethernet station address via the CNFG command. Note The unique Ethernet address is set at the factory and should not be changed. Any attempt to change this address may create node or bus contention and thereby render the board inoperable.
Block Diagram The MVME230x supports two PMC slots. Two sets of four 64-pin connectors on the base board (J11 - J14, and J21 - J24) interface with 32-bit/64-bit IEEE P1386.1 PMC-compatible mezzanines to add any desirable function. Refer to Appendix C for the pin assignments of the PMC connectors.
Functional Description For P2 I/O configurations, 46 I/O pins of PMC slot 2 are routed to the 5-row power adapter card. Pins 1 through 46 of J24 are routed to row D and row Z of P2. PMC Slots 1 and 2 (Double-Width PMC) PMC slots 1 and 2 with a double-width PMC have the following characteristics: Mezzanine Type...
Block Diagram programming information, refer to the Universe UserÕs Manual and to the discussions in the MVME2300-Series VME Processor Module Programmer's Reference Guide. Maximum performance is achieved with D64 Multiplexed Block Transfers (MBLT). The on-chip DMA channel should be used to move large blocks of data to/from the VMEbus.
Functional Description Ð ISA (Industry Standard Architecture) bus DMA (not functional on MVME230x) Ð The PHB (PCI Host Bridge) MPU/local bus interface function, implemented by the Raven ASIC Ð All on-board PCI devices Ð The PMC slot ISA bus arbitration for DMA devices ISA interrupt mapping for four PCI interrupts Interrupt controller functionality to support 14 ISA interrupts Edge/level control for ISA interrupts...
Block Diagram The SNAPHAT battery package is mounted on top of the M48T59/T559 device. The battery housing is keyed to prevent reverse insertion. The clock furnishes seconds, minutes, hours, day, date, month, and year in BCD 24-hour format. Corrections for 28-, 29- (leap year), and 30-day months are made automatically.
Functional Description Two software interrupts ISA interrupts (actually handles as a single 8259 interrupt at INT0) Programmable Timers Among the resources available to the local processor are a number of programmable timers. Timers are incorporated into the PCI/ISA Bridge (PIB) controller and the Raven device (diagrammed in Figure 3-1).
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Block Diagram periodic interrupts. For information on programming these timers, refer to the data sheet for the W83C553 PIB controller and to the MVME2300-Series VMe P:rocessor Module ProgrammerÕs Reference Guide. 3-20...
4Programming the MVME230x Introduction This chapter provides basic information useful in programming the MVME230x. This includes a description of memory maps, control and status registers, PCI arbitration, interrupt handling, sources of reset, and big/little endian issues. For additional programming information about the MVME230x, refer to the MVME2300-Series VME Processor Module ProgrammerÕs Reference Guide.
Programming the MVME230x Processor Bus Memory Map The processor memory map configuration is under the control of the Raven bridge controller ASIC and the Falcon memory controller chip set. The Raven and Falcon devices adjust system mapping to suit a given application via programmable map decoder registers. At system power-up or reset, a default processor memory map takes over.
Memory Maps For detailed processor memory maps, including suggested CHRP- and PREP-compatible memory maps, refer to the MVME2300-Series VME Processor Module ProgrammerÕs Reference Guide. PCI Local Bus Memory Map The PCI memory map is controlled by the Raven MPU/PCI bus bridge controller ASIC and by the Universe PCI/VME bus bridge ASIC.
Programming the MVME230x Programming Considerations Good programming practice dictates that only one MPU at a time have control of the MVME230x control registers. Of particular note are: Registers that modify the address map Registers that require two cycles to access VMEbus interrupt request registers PCI Arbitration There are seven potential PCI bus masters on the MVME230x :...
Programming Considerations INT_ Processor (8529 Pair) MCP_ RavenMPIC SERR_& PERR_ PCI Interrupts ISA Interrupts 11559.00 9609 Figure 4-2. MVME230x Interrupt Architecture The MVME230x routes the interrupts from the PMCs and PCI expansion slots as follows:...
Programming Considerations 6. The VMEbus ∗ signal SYSRESET 7. VMEbus Reset sources from the Universe ASIC (PCI/VME bus bridge controller): the System Software reset, Local Software Reset, and VME CSR Reset functions Table 4-3 shows which devices are affected by the various types of resets.
Programming the MVME230x Endian Issues The MVME230x supports both little-endian (e.g., Windows NT) and big-endian (e.g., AIX) software. The PowerPC processor and the VMEbus are inherently big-endian, while the PCI bus is inherently little-endian. The following sections summarize how the MVME230x handles software and hardware differences in big- and little-endian operations.
Programming Considerations PCI and Ethernet Ethernet is byte-stream-oriented; the byte having the lowest address in memory is the first one to be transferred regardless of the endian mode. Since the Raven maintains address invariance in both little-endian and big-endian mode, no endian issues should arise for Ethernet data.
Related Documentation appendix. PPCBug Basics The PowerPC debug firmware, PPCBug, is a powerful evaluation and debugging tool for systems built around the Motorola PowerPC microcomputers. Facilities are available for loading and executing user programs under complete operator control for system evaluation.
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PPCBug Basics Display and modification of memory Breakpoint and tracing capabilities A powerful assembler and disassembler useful for patching programs A self-test at power-up feature which verifies the integrity of the system PPCBug consists of three parts: A command-driven, user-interactive software debugger, described in the PPCBug Firmware Package UserÕs Manual.
PPCBug Memory Requirements PPCBug requires a maximum of512KB of read/write memory (i.e., DRAM). The debugger allocates this space from the top of memory. For example, a system containing 64MB ($04000000) of read/write memory will place the PPCBug memory page at locations $03F80000 to $03FFFFFF.
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MPU, Hardware, and Firmware Initialization 7. Calculates the external bus clock speed of the MPU. 8. Delays for 750 milliseconds. 9. Determines the CPU base board type. 10. Sizes the local read/write memory (i.e., DRAM). 11. Initializes the read/write memory controller. Sets base address of memory to $00000000.
PPCBug 26. Verifies the configuration data that is resident in NVRAM, and displays a warning message if the verification failed. 27. Calculates and displays the MPU clock speed, verifies that the MPU clock speed matches the configuration data, and displays a warning message if the verification fails. 28.
Using PPCBug After the debugger executes the command, the prompt reappears. However, if the command causes execution of user target code (for example GO) then control may or may not return to the debugger, depending on what the user program does. For example, if a breakpoint has been specified, then control returns to the debugger when the breakpoint is encountered during execution of the user program.
PPCBug Table 5-1. Debugger Commands Command Description One Line Assembler Block of Memory Compare Block of Memory Fill Block of Memory Initialize Block of Memory Move Breakpoint Insert NOBR Breakpoint Delete Block of Memory Search Block of Memory Verify Concurrent Mode NOCM No Concurrent Mode CNFG...
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Using PPCBug Table 5-1. Debugger Commands (Continued) Command Description Help IDLE Idle Master MPU I/O Control for Disk I/O Inquiry I/O Physical (Direct Disk Access) I/O Teach for ConÞguring Disk Controller Idle MPU Register Display Idle MPU Register Modify Idle MPU Register Set Load S-Records from Host Macro DeÞne/Display NOMA...
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PPCBug Table 5-1. Debugger Commands (Continued) Command Description NOPA Printer Detach PBOOT Bootstrap Operating System Port Format NOPF Port Detach PFLASH Program FLASH Memory Put RTC into Power Save Mode ROMboot Enable NORB ROMboot Disable Register Display REMOTE Remote RESET Cold/Warm Reset Read Loop Register Modify...
Using PPCBug Although a command to allow the erasing and reprogramming of Flash memory is available to you, keep in mind that reprogramming any portion of Flash Caution memory will erase everything currently contained in Flash, including the PPCBug debugger. Note, however, that both banks A and B of Flash contain the PPCBug debugger.
6Modifying the Environment Overview You can use the factory-installed debug monitor, PPCBug, to modify certain parameters contained in the MVME230x's Non- Volatile RAM (NVRAM), also known as Battery Backed-up RAM (BBRAM). The Board Information Block in NVRAM contains various elements concerning operating parameters of the hardware. Use the PPCBug command CNFG to change those parameters.
= “07” System Serial Number = “ nnnnnnn ” System Identifier = “Motorola MVME2300” License Identifier = “ nnnnnnnn “ The parameters that are quoted are left-justified character (ASCII) strings padded with space characters, and the quotes (Ò) are displayed to indicate the size of the string. Parameters that are not quoted are considered data strings, and data strings are right- justified.
Modifying the Environment ENV - Set Environment Use the ENV command to view and/or configure interactively all PPCBug operational parameters that are kept in Non-Volatile RAM (NVRAM). Refer to the PPCBug Firmware Package User's Manual for a description of the use of ENV. Additional information on registers in the Universe ASIC that affect these parameters is contained in your MVME2300-Series VME Processor Module ProgrammerÕs Reference Guide.
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ENV - Set Environment Remote Start Method Switch [G/M/B/N] = B? The Remote Start Method Switch is used when the MVME2300 is cross-loaded from another VME-based CPU, to start execution of the cross-loaded program. Use the Global Control and Status Register to pass and start execution of the cross-loaded program.
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Modifying the Environment Network PReP-Boot Mode Enable [Y/N] = N? Enable PReP-style network booting (same boot image from a network interface as from a mass storage device). Do not enable PReP-style network booting. (Default) Negate VMEbus SYSFAIL* Always [Y/N] = N? ∗...
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ENV - Set Environment NVRAM Bootlist (GEV.fw-boot-path) Boot Enable [Y/N] = N? Give boot priority to devices deÞned in the fw- boot-path global environment variable (GEV). Do not give boot priority to devices listed in the fw-boot-path GEV. (Default) Note When enabled, the GEV (Global Environment Variable) boot takes priority over all other boots, including Autoboot and Network Boot.
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Modifying the Environment Auto Boot Scan Enable [Y/N] = Y? If Autoboot is enabled, the Autoboot process attempts to boot from devices speciÞed in the scan list (e.g., FDISK/CDROM/TAPE/HDISK (Default) If Autoboot is enabled, the Autoboot process uses the Controller LUN and Device LUN to boot.
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ENV - Set Environment Auto Boot Controller LUN = 00? Refer to the PPCBug Firmware Package User's Manual for a listing of disk/tape controller modules currently supported by PPCBug. (Default = $00) Auto Boot Device LUN = 00? Refer to the PPCBug Firmware Package User's Manual for a listing of disk/tape devices currently supported by PPCBug.
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Modifying the Environment ROM Boot at power-up only [Y/N] = Y? ROMboot is attempted at power-up only. (Default) ROMboot is attempted at any reset. ROM Boot Enable search of VMEbus [Y/N] = N? VMEbus address space, in addition to the usual areas of memory, will be searched for a ROMboot module .
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ENV - Set Environment Network Auto Boot Controller LUN = 00? Refer to the PPCBug Firmware Package User's Manual for a listing of network controller modules currently supported by PPCBug. (Default = $00) Network Auto Boot Device LUN = 00? Refer to the PPCBug Firmware Package User's Manual for a listing of network controller modules currently supported by PPCBug.
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Modifying the Environment Memory Size Enable [Y/N] = Y? Memory will be sized for Self Test diagnostics. (Default) Memory will not be sized for Self Test diagnostics. Memory Size Starting Address = 00000000? The default Starting Address is $00000000. Memory Size Ending Address = 02000000? The default Ending Address is the calculated size of local memory.
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ENV - Set Environment ROM Next Access Length (0 - 15) = 0? The value programmed into theÒROMNALÓ Þeld (Memory Control ConÞguration Register 8: bits 28-31) to represent wait states in access time for nibble (or burst) mode ROM accesses. The lowest allowable ROMNAL setting is $0;...
Modifying the Environment LED/Serial Startup Diagnostic Codes: these codes can Note be displayed at key points in the initialization of the hardware devices. Should the debugger fail to come up to a prompt, the last code displayed will indicate how far the initialization sequence had progressed before stalling.
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ENV - Set Environment PCI Slave Image 0 Bound Address Register = 00000000? The conÞgured value is written into the LSI0_BD register of the Universe chip. PCI Slave Image 0 Translation Offset = 00000000? The conÞgured value is written into the LSI0_TO register of the Universe chip.
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Modifying the Environment PCI Slave Image 3 Control = C0400000? The conÞgured value is written into the LSI3_CTL register of the Universe chip. PCI Slave Image 3 Base Address Register = 2FFF0000? The conÞgured value is written into the LSI3_BS register of the Universe chip.
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ENV - Set Environment VMEbus Slave Image 1 Bound Address Register = 00000000? The conÞgured value is written into the VSI1_BD register of the Universe chip. VMEbus Slave Image 1 Translation Offset = 00000000? The conÞgured value is written into the VSI1_TO register of the Universe chip.
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Modifying the Environment PCI Miscellaneous Register = 10000000? The conÞgured value is written into the LMISC register of the Universe chip. Special PCI Slave Image Register = 00000000? The conÞgured value is written into the SLSI register of the Universe chip. Master Control Register = 80C00000? The conÞgured value is written into the MAST_CTL register of the Universe chip.
PMCspan PMC Adapter Carrier Module Installation and Use PMCSPANA/IH Note Although not shown in the above list, each Motorola Computer Group manual publication number is suffixed with characters that represent the revision level of the document, such as Ò/xx2Ó (the second revision of a manual);...
Table A-2. Manufacturers’ Documents Publication Document Title and Source Number PowerPC 603 RISC Microprocessor Technical Summary MPC603/D Literature Distribution Center for Motorola Telephone: 1-800- 441-2447 FAX: (602) 994-6430 or (303) 675-2150 E-mail: ldcformotorola@hibbertco.com PowerPC 603 RISC Microprocessor UserÕs Manual MPC603UM/AD...
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Table A-2. Manufacturers’ Documents (Continued) Publication Document Title and Source Number PowerPC Microprocessor Family: The Programming Environments MPCFPE/AD Literature Distribution Center for Motorola Telephone: 1-800- 441-2447 FAX: (602) 994-6430 or (303) 675-2150 E-mail: ldcformotorola@hibbertco.com IBM Microelectronics Mail Stop A25/862-1 MPRPPCFPE-01...
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Ordering Related Documentation Table A-2. Manufacturers’ Documents (Continued) Publication Document Title and Source Number W83C553 Enhanced System I/O Controller with PCI Arbiter (PIB) W83C553 Winbond Electronics Corporation Winbond Systems Laboratory 2730 Orchard Parkway San Jose, CA 95134 Telephone: (408) 943-6666 FAX:(408) 943-6668 M48T59 CMOS 8K x 8 TIMEKEEPER SRAM Data Sheet...
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Related Specifications Related Specifications For additional information, refer to the following table for related specifications. As an additional help, a source for the listed document is also provided. Please note that in many cases, the information is preliminary and the revision levels of the documents are subject to change without notice.
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Ordering Related Documentation Table A-3. Related Specifications (Continued) Publication Document Title and Source Number IEEE - PCI Mezzanine Card SpeciÞcation (PMC) P1386.1 Draft 2.0 Institute of Electrical and Electronics Engineers, Inc. Publication and Sales Department 345 East 47th Street New York, New York 10017-21633 Telephone: 1-800-678-4333 Bidirectional Parallel Port Interface SpeciÞcation IEEE Standard 1284...
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Publication Document Title and Source Number PowerPC Microprocessor Common Hardware Reference Platform A System Architecture (CHRP), Version 1.0 Literature Distribution Center for Motorola Telephone: 1-800- 441-2447 FAX: (602) 994-6430 or (303) 675-2150 E-mail: ldcformotorola@hibbertco.com AFDA, Apple Computer, Inc. P. O. Box 319...
Specifications Specifications The following table lists the general specifications for the MVME230x VME processor module. The subsequent sections detail cooling requirements and EMC regulatory compliance. A complete functional description of the MVME230x boards appears in Chapter 3. Specifications for the optional PMCs can be found in the documentation for those modules.
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Specifications Table B-1. MVME230 x Specifications (Continued) Characteristics SpeciÞcations Relative humidity 10% to 80% Vibration (operating) 2 Gs RMS, 20Hz-2000Hz random Altitude (operating) 5000 meters (16,405 feet) Physical dimensions Height Double-high VME board, 9.2 in. (233 mm) (base board only) Front panel width 0.8 in.
(base board and modules) at a velocity typically achievable by using a 100 CFM axial fan. Temperature qualification is performed in a standard Motorola VMEsystem chassis. Twenty-five-watt load boards are inserted in two card slots, one on each side, adjacent to the board under test, to simulate a high power density system configuration.
Specifications achieved with 10 CFM and 490 LFM flowing over the module. Less airflow is required to cool the module in environments having lower maximum ambients. Under more favorable thermal conditions, it may be possible to operate the module reliably at higher than 55û...
Slot 2 64-bit PCI extension J23, J24 C-10 and P2 I/O Pin Assignments The following tables furnish pin assignments only. For detailed descriptions of the various interconnect signals, consult the support information documentation for the MVME230x (contact your Motorola sales office).
Connector Pin Assignments VMEbus Connector - P1 Two 160-pin DIN type connectors, P1 and P2, supply the interface between the base board and the VMEbus. P1 provides power and VME signals for 24-bit addressing and 16-bit data. Its pin assignments are set by the IEEE P1014-1987 VMEbus Specification and the VME64 Extension Standard.
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Pin Assignments Table C-1. P1 VMEbus Connector Pin Assignments (Continued) ∗ Not Used VIRQ6 VA13 Not Used ∗ VIRQ5 VA12 Not Used ∗ Not Used VIRQ4 VA11 Not Used ∗ VIRQ3 VA10 Not Used ∗ Not Used VIRQ2 Not Used ∗...
Connector Pin Assignments VMEbus Connector - P2 Row B of the P2 connector provides power to the MVME230x, the upper eight VMEbus lines, and additional 16 VMEbus data lines as specified by the VMEbus specification Rows A, C, Z, and D of the P2 connector provide power and interface signals to a transition module, when one is used.
Connector Pin Assignments Serial Port Connector - DEBUG (J2) A standard RJ45 connector located on the front plate of the MVME230x provides the interface to the asynchronous serial debug port. The pin assignments for this connector are as follows: Table C-3. DEBUG (J2)Connector Pin Assignments Ethernet Connector - 10BASET (J3) The 10BaseT/100BaseTx connector is an RJ45 connector located on the front plate of the MVME230x.
Pin Assignments CPU Debug Connector - J1 One 190-pin Mictor connector with center row of power and ground pins is used to provide access to the Processor Bus and some miscellaneous signals. The pin assignments for this connector are as follows: Table C-5.
Connector Pin Assignments PCI Expansion Connector - J18 One 114-pin Mictor connector with center row of power and ground pins is used to provide PCI/PMC expansion capability. The pin assignments for this connector are as follows: Table C-6. J18 - PCI Expansion Connector Pin Assignments +3.3V +3.3V PCICLK...
Pin Assignments PCI Mezzanine Card Connectors - J11 through J14 Four 64-pin SMT connectors, J11 through J14, supply 32/64-bit PCI interfaces and P2 I/O between the MVME230x board and an optional add-on PCI Mezzanine Card (PMC) in PMC Slot 1. The pin assignments for PMC Slot 1 are listed in the following two tables.
Connector Pin Assignments Table C-7. J11 - J12 PMC1 Connector Pin Assignments (Continued) 47 AD12 AD11 AD10 AD09 AD08 +3.3V C/BE0# AD07 Not Used AD06 AD05 +3.3V Not Used AD04 Not Used +5V (Vio) AD03 Not Used Not Used AD02 AD01 Not Used AD00...
Connector Pin Assignments PCI Mezzanine Card Connectors - J21 through J24 Four 64-pin SMT connectors, J21 through J24, supply 32/64-bit PCI interfaces and P2 I/O between the MVME230x board and an optional add-on PCI Mezzanine Card (PMC) in PMC Slot 2. The pin assignments for PMC Slot 2 are listed in the following two tables.
DTroubleshooting the MVME230x Solving Startup Problems In the event of difficulty with your MVME230x VME Processor Module, try the simple troubleshooting steps on the following pages before calling for help or sending the board back for repair. Some of the procedures will return the board to the factory debugger environment.
Troubleshooting the MVME230x Table D-1. Troubleshooting MVME230x Modules Condition Possible Problem Try This: I. Nothing works, A. If the 1. Make sure the system is plugged in. no display on is not lit, the 2. Check that the board is securely installed in its backplane the terminal.
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Solving Startup Problems Table D-1. Troubleshooting MVME230x Modules (Continued) Condition Possible Problem Try This: III. Debug prompt A. Debugger Flash 1. Disconnect all power from your system. may be missing PPC1-Bug> 2. Check that the proper debugger devices are installedl. does not 3.
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Troubleshooting the MVME230x Table D-1. Troubleshooting MVME230x Modules (Continued) Condition Possible Problem Try This: IV. Continued 2. At the command line prompt, type in: env;d <CR> This sets up the default parameters for the debugger environment. 3. When prompted to Update Non-Volatile RAM, type in: y <CR>...
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Solving Startup Problems Table D-1. Troubleshooting MVME230x Modules (Continued) Condition Possible Problem Try This: V. The debugger is A. No apparent No further troubleshooting steps are required. in system mode problems Ñ and the board troubleshooting autoboots, or is done. the board has passed selftests.
Glossary Abbreviations, Acronyms, and Terms to Know This glossary defines some of the abbreviations, acronyms, and key terms used in this document. An Ethernet implementation in which the physical medium 10Base-5 is a doubly shielded, 50-ohm coaxial cable capable of carrying data at 10 Mbps for a length of 500 meters (also referred to as thicknet).
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Glossary Application-Specific Integrated Circuit ASIC Attachment Unit Interface Battery Backed-up Random Access Memory BBRAM Having big-endian and little-endian byte ordering bi-endian capability. A byte-ordering method in memory where the address big-endian n of a word corresponds to the most significant byte. In an addressed memory word, the bytes are ordered (left to right) 0, 1, 2, 3, with 0 being the most significant byte.
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The Green signals (G-Y) can be extracted by these two signals. Common Hardware Reference Platform (CHRP) A specification published by Apple, IBM, and Motorola which defines the devices, interfaces, and data formats that make up a CHRP-compliant system using a PowerPC processor.
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Glossary Central Processing Unit. The master computer unit in a system. Data Circuit-terminating Equipment. Dynamic Link Library. A set of functions that are linked to the referencing program at the time it is loaded into memory. Direct Memory Access. A method by which a device may read or write to memory directly without processor intervention.
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A local area network standard that uses radio frequency Ethernet signals carried by coaxial cables. The DRAM controller chip developed by Motorola for the Falcon MVME2600 and MVME3600 series of boards. It is intended to be used in sets of two to provide the necessary interface between the Power PC60x bus and the 144-bit ECC DRAM (system memory array) and/or ROM/Flash.
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Glossary A computing system is normally spoken of as having two hardware major components: hardware and software. Hardware is the term used to describe any of the physical embodiments of a computer system, with emphasis on the electronic circuits (the computer) and electromechanical devices (peripherals) that make up the system.
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Multimedia Personal Computer The PowerPC-to-PCI bus bridge chip developed by MPC105 Motorola for the Ultra 603/Ultra 604 system board. It provides the necessary interface between the MPC603/ MPC604 processor and the Boot ROM (secondary cache), the DRAM (system memory array), and the PCI bus.
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Glossary several different ways, yielding substantially different results. The specification is based on a large number of samplings in one place, running continuously, and the rate at which failure occurs. MTBF is not representative of how long a device, or any individual device is likely to last, nor is it a warranty, but rather, a gauge of the relative reliability of a family of products.
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(branch units, fixed-point units, and floating-point units), where they can execute concurrently, but finish out of order. PowerPC is used by Motorola, Inc. under license from IBM. The first implementation of the PowerPC family of PowerPC 601™...
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64-entry buffer and an 8KB (instruction and data) cache. It provides a selectable 32-bit or 64-bit data bus and a separate 32-bit address bus. PowerPC 603 is used by Motorola, Inc. under license from IBM. The third implementation of the PowerPC family of PowerPC 604™...
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Glossary The PowerPC-to-PCI local bus bridge chip developed by Raven Motorola for the MVME2600 and MVME3600 series of boards. It provides the necessary interface between the PowerPC 60x bus and the PCI bus, and acts as interrupt controller. Reduced-Instruction-Set Computer (RISC) A computer in which the processorÕs instruction set is...
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Glossary Super I/O controller Symmetric MultiProcessing. A computer architecture in which tasks are distributed among two or more local processors. Surface Mount Technology. A method of mounting devices (such as integrated circuits, resistors, capacitors, and others) on a printed circuit board, characterized by not requiring mounting holes.
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Glossary ASIC developed by Tundra in consultation with Motorola, Universe that provides the complete interface between the PCI bus and the 64-bit VMEbus. UltraViolet Ultra Video Graphics Array. An improved VGA monitor UVGA standard that provides at least 256 simultaneous colors and a screen resolution of 1024 x 768 pixels.
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Glossary port for CPU accesses. The result of adding the serial port is a significantly reduced amount of interference from screen refresh. VRAMs cost more per bit than DRAMs. The trademark representing Windows New Technology, a Windows NT™ computer operating system developed by the Microsoft Corporation.
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Index Numerics configurations MVME230x 10/100 BASET port configure 16/32-bit timers 3-19 PPC1Bug parameters VMEbus interface 6-13 Configure Board Information Block abbreviations, acronyms, and terms to (CNFG) know GL-1 configuring the hardware abort (interrupt) signal connector pin assignments ABT switch (S1) console terminal address pipelining 3-9, 3-10...
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Index EMC regulatory compliance HE (Help) command 5-10 endian issues headers function of Raven ASIC 4-10 1-10 function of Universe ASIC 4-11 1-10 PCI domain 4-10 1-11 processor/memory domain 4-10 help command 5-10 VMEbus domain 4-11 humidity, relative ENV command environmental parameters IACK and BG signals 1-22...
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Index preparing 1-12 restart mode 5-11 PMCspan RF emissions preparing 1-12 ROMboot enable 6-8, 6-12 PMCspan Expansion Mezzanine ROMFAL 6-11 PMCspan-002 Installation on an ROMNAL 6-12 MVME230x 1-17 port SCSI bus asynchronous 3-16 SD command 5-10 debug 3-16 secondary PMCspan port, Ethernet installing 1-18...
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Index 16/32-bit 3-19 interval 3-19 timers, programmable 3-19 timers, via Universe chip timing owerPC bus to DRAM PCI to ECC memory PowerPC bus to DRAM troubleshooting procedures troubleshooting the MVME230x 5-10 Typical Single-width PMC Module Placement on MVME230x 1-15 Universe VMEbus interface ASIC 2-3, 3-15, 4-3, 4-4, 4-9, 4-11 unpacking the hardware...