Main Chassis Features; Chassis Block Diagram; Signal Processing; Digital Reception - Philips 42PF9731D Service Manual

EN 150 9. BJ2.4U/BJ2.5U LA

9. Circuit Descriptions, Abbreviation List, and IC Data Sheets

Index of this chapter:
9.1 Introduction
9.2 Power Supply
9.3 Inputs
9.4 Front-End
9.5 POD (Point Of Deployment)
9.6 MPIF (PNX 3000)
9.7 PNX2015
9.8 PNX2015: AVIP
9.9 PNX2015: Columbus (Comb Filter)
9.10 PNX2015: HD Subsystem
9.11 PNX2015: LVDS Transmitter
9.12 PNX2015: Stand-by Processor
9.13 VIPER 2 (PNX 8550)
9.14 Ambient Light (if present)
9.15 Abbreviation List
9.16 IC Data Sheets
Notes:
• Only new circuits (circuits that are not published recently)
are described.
• Figures can deviate slightly from the actual situation, due
to different set executions.
• For a good understanding of the following circuit
descriptions, please use the wiring, block (chapter 6) and
circuit diagrams (chapter 7). Where necessary, you will find
a separate drawing for clarification.
9.1 Introduction
The BJ2.x is derived from the BL2.x TV chassis. Main
difference with this chassis is the introduction of the Pacific 3
IC for picture enhancement and AmbiLight processing. The
MOP (or EPLD) has been taken out. The key components are:
• POD circuitry.
• MPIF (PNX3000).
• AVIP/COLUMBUS (PNX2015).
• VIPER 2 (PNX8550).
9.1.1 Features
Table 9-1 Main chassis features
Feature BJ2.5 (Entry) BJ2.4 (Top B) BJ2.4 (Top A)
AmbiLight No
USB 1 x USB1.1
Card reader No
MOP (EPLD) No
Pacific 3 Yes
PixelPlus Pixel Plus
The main features for this chassis are (see also table):
• The move from the analog world to the digital world. W.o.w.
from signal processing via "hardware circuits" to signal
processing via "software algorithms". This means: no
software = no picture and sound!
• Fit for both analog and digital signal processing, this by
converting analog signals into digital transport streams and
allowing seamless zapping between all possible signal
sources. This makes the chassis applicable for e.g.
receiving ATSC in an integrated product form.
• AmbiLight (Top, Step): To be able to control lamps at the
rear of the TV with respect to the measured ambient light
level from the light sensor or the picture content, a control
output from AutoTV has been foreseen.
• The internal digital processing allows new "Multi-Media"
applications such as Content Browser, Memory Card Slot,
Circuit Descriptions, Abbreviation List, and IC Data Sheets
Triple Full Surround
2 x USB2.0 2 x USB2.0
Yes Yes
No No
Yes Yes
Pixel Plus 3 Pixel Plus 3
Local Area Network support (future) and all kinds of
streaming applications (future).
• The chassis can be upgraded in the future with internal
functionality such as Personal Video Recording, DVD/RW.
9.1.2

Chassis Block Diagram

Description below refers to the block diagrams in chapter 6
"Block Diagrams, Test Point Overview, and Waveforms".
Analog Reception
The TV receives multimedia information by tuning to one of
many 6 MHz input channels available via a cable connection.
When the input channel is an analog channel, the signal is
processed via the NTSC decoder and the VBI data decoder.

Digital Reception

As depicted in the block diagram, the POD module consists of
the following functional blocks: POD Common Interface, Out of
Band part, and buffering. These blocks are interfacing with the
ATSC In Band (IB) channel decoder and Out of Band (OOB)
channel decoder. The interface is connected to the VIPER.
Also the POD Interface outgoing Transport Stream (TS) is
routed to the VIPER.
The TV receives multimedia information by tuning to one of
many 6 MHz input channels available via a cable connection.
When the input channel is a digital channel, it is processed via
the QAM demodulator and then passed to the CableCARD
device (POD) where secure and scrambled information is
processed. Non-scrambled information is passed through the
CableCARD Device to the MPEG-2 Transport Demultiplexer.
When the CableCARD Device is not inserted, the output of the
QAM demodulator is routed directly to the MPEG-2 Transport
Demultiplexer. The multi-media processor (VIPER) handles
the synchronization and display of audio-visual material.
The OpenCable Host Device also receives control information
and other data by tuning to an Out-Of-Band (OOB) Forward
Data Channel (FDC) channel. The terminal will remain tuned to
the OOB Forward Data Channel (own tuner) to continuously
receive information. This information is passed to the
CableCARD Device for processing, and relevant information is
passed back to the TV.

Signal Processing

The AVIP together with the MPIF device is used to perform the
input decoding of a single stream of analog audio and video
broadcast signals. In addition, the AVIP is used for decoding
and presentation of audio output streams. The main data
connection between MPIF and AVIP is done via an I
The AVIP converts the incoming video data to ITU-656 format
for communication to the VIPER IC.
The audio data is transferred between the AVIP and VIPER
2
using I S. The AVIP IC is controlled by the VIPER via the I
bus.
The key part in the system, the VIPER, performs almost all key
features, like video quality enhancement, motion
compensation, picture-in-picture processing, and others. It is a
completely digital IC with a TriMedia DSP (Digital Signal
Processor) core and a MIPS microcontroller core. The DSP
and some additional cores are used to do the video feature
processing and some auxiliary sound feature processing. The
MIPS microcontroller core is used for all internal and external
controlling tasks including a system wide I
provides a primary digital (YUV or RGB) output to the LVDS
transmitter. For picture enhancements, the Pacific 3 is
connected between VIPER output and LVDS Transmitter input.
In models with the AmbiLight feature, the Pacific 3 is also used
for AmbiLight processing.
2
D bus.
2
C
2
C bus. The VIPER