Pnx2015: Stand-By Processor; Viper 2 (Pnx 8550); Tv Start-Up Behavior And Fault Detection; I/O Stand-By Processor - Philips 42PF9731D Service Manual

EN 166 9. BJ2.4U/BJ2.5U LA
- Lower Voltage Swing (only 350 mV vs. 3 V)
- Allows faster Clocking
- Standard open Ended: 250Mbps
- LVDS: >1 Gbps
Standard Single Ended
1
- Differential Signals (Two Signals) ...Low Noise!
- Receiver reads a 1 or 0 based on the delta of the two signals.
- Noise Impacts both lines and cancels out each others.
Low Voltage Differential Signalling
1
Two Signals & Smaller Voltage Swing
Figure 9-26 LVDS technology
The digital video output from the VIPER is connected to the
display via the LVDS interface. This transmitter converts 28 bits
of LVCMOS/LVTTL data into four LVDS (Low Voltage
Differential Signalling) data streams. A phase-locked transmit
clock is transmitted in parallel with the data streams over a fifth
LVDS link. With every cycle of the transmit clock, 28 bits of
input data are sampled and transmitted. At a transmit clock
frequency of 85 MHz, 24 bits of RGB data and 3 bits of LCD
timing and control data (FPLINE, FPFRAME, DRDY) are
transmitted at a rate of 595 Mbps per LVDS data channel.
Using a 85 MHz clock, the data throughput is 297.5 Mbytes/
sec.

9.12 PNX2015: Stand-by Processor

9.12.1 Introduction
The Stand-by Processor's sub system is isolated from the other
sub systems within thePNX2015. It has its own power supply
(1.2V and 3.3V), together with separate clocking (16MHz) and
reset. This allows for it to be active while all other sub systems
are either inactive, via clock being disabled, or powered down.
The main tasks of the Stand-by Controller are:
• RC5/RC6 remote control handling.
• P50.
• Keyboard handling (side control, "on/off" switch).
• Detection and protection of the power supplies.
• Status detection on EXTernals.
• SAM/SDM entering.
• Provide boot-scripts to the VIPER.
• Start-up behavior of the set; sequentially enabling the
power supplies via the ENABLE lines.

9.12.2 TV Start-up Behavior and Fault Detection

1. The Stand-by Controller is powered by the +5V2 voltage
(3V3_STBY voltage is derived from the +5V2), which
becomes available when the set is connected to the Mains
/ AC Power.
2. By default, all I/O lines of the controller are "high", this state
is also the state that will not trigger protections or cause
supplies to rise, since enabling a supply requires that an IO
line is pulled "low". Also all protections are active "low".
3. The 16 MHz crystal starts running.
4. Reset IC 7M03 will generate a RESET_STBY pulse.
Circuit Descriptions, Abbreviation List, and IC Data Sheets
Single Signal & Larger
Voltage swing
0 1 0
Noise
0 1 0
CL 36532053_073.eps
5. All I/O lines will be set in default state, as "told" by the
software.
– RESET_SYSTEM will be "low" (this will hold the
VIPER in reset).
– LAMP_ON will be "low".
6. The system waits for an RC or functional switch command:
when this command is "low" the set will start-up.
The Stand-by Microprocessor is responsible for the start-up of
the VIPER, by providing the correct timing for the DC/DC
converted voltages (for timing of DC/DC converter voltages see
description in paragraph "Power Supply").
The +12V switch (via POD_MODE) and the DC/DC converters
(via ENABLE) are switched "on" (active "low"). Once these
voltages are switched "on", the Stand-by Controller is
monitoring these voltages via a voltage detector circuit
connected to port P2.x. When one of the voltages is missing,
the fault detection will be active "low" on port P2.x. An error
code will be written in the error buffer.
There is a common SUPPLY_FAULT line; connected to port
P1.3 (INT5) that is active "low" when there is a problem
detected on one of the DC/DC power supplies driver circuits.
One input (P2.6) is used for the Audio Supply protection from
310703
the audio amplifier.
The RESET_SYSTEM line (P4.0) is "low" in Stand-by and at
Start-up to keep the VIPER in reset state. Once the VIPER core
supply is available, the RESET_SYSTEM line will become
"high". The VIPER is starting up and will provide a RESET-
MIPS active "high" to the Stand-by Processor P3.3, AVIP, and
COLUMBUS.

9.12.3 I/O Stand-by Processor

The inputs on the Stand-by Microprocessor are used to detect
the AV status from the front inputs (see also the control block
diagram in chapter 6 "Block diagrams,...").
An UART communication line via an electronic switch is
available on a connector and will be used for Service to
communicate with ComPair. The UART line is switched to the
Stand-by Processor when the UART_SWITCH line (P0.7) is
"high". Otherwise it is switched to the VIPER.

9.13 VIPER 2 (PNX 8550)

9.13.1 Introduction
The PNX8550 is a highly integrated media processor intended
for deployment in analog, digital, and hybrid TV receivers. It
can be used for 100 Hz interlaced as well as 60 Hz progressive
screens. It is fully capable of performing advanced video
improvement algorithms, such as Digital Natural Motion™, on
Standard Definition analog or digital sources. It includes an HD
capable de-interlacer for converting interlaced HD
transmission signals to progressive output for driving wide-
XGA class Plasma or LCD displays. Two 32-bit 240 MHz VLIW
media processors, referred to as the TriMedia TM3260 CPU
core, carry out the advanced video improvement processing as
well as all audio operations. Fixed hardware functions perform
stable core video functions, such as picture level MPEG2
decoding, scaling, image composition and pixel post
processing.
The PNX8550 provides a primary digital (YUV or RGB) output
to connect to the display specific output processor. In addition,
a secondary analog video output (CVBS or S-Video) for a VCR
is available. This is the so-called DENC-out. It can operate
either in analog PAL/NTSC or digital mode.