Sharp ER-A770 Manual page 41

3) General description
The CPUs are fourth-generation enhanced microprocessors with ex-
ceptional computational power. They offer higher system throughput
and more efficient memory utilization than comparable second- and
third-generation microprocessors. Theinternal registers contain 208
bits of read/write memory that are accessible to the programmer.
These registers include two sets of six general-purpose registers
which may be used individually as either 8-bit registers or as 16-bit
register pairs. In addition, there are two sets of accumulator and flag
registers. A group of "Exchange" instructions makes either set of
main or alternate registers accessible to the programmer. The alter-
nate set allows operation inforeground-background mode or it may be
reserved for very fast interrupt response.
The CPU also contains a Stack Pointer, Program Counter, two index
registers, a Refresh register (counter), and an Interrupt register. The
CPU is easy to incorporate into a system since it requires only a
single +5V power source. All output signals are fully decoded and
timed to control standard memory or peripheral circuits; the CPU is
supported by an extensive family of peripheral controllers.
The internal block diagram (Figure 3) shows the primary functions of
the processors. Subsequent text provides more detail on the I/O con-
troller family, registers, instruction set, interrupts and daisy chaining,
and CPU timing.
INSTRUCTION INSTRUCTION
DECODER REGISTER
+5V
GND
CLOCK
CPU
TIMING
CONTROL
8 SYSTEMS 5 CPU
AND CPU CONTROL
CONTROL INPUTS
OUTPUTS
Figure 3. Z80C CPU Block Diagram
4) Pin description
Pin Signal
Symbol In/Out
No. name
1 CLK CLK
2 D4 S D4 In/Out
3 D3 S D3 In/Out
4 D5 S D5 In/Out
5 D6 S D6 In/Out
6 +5V VCC
7 D2 S D2 In/Out
8 D7 S D7 In/Out
9 D0 S D0 In/Out
10 D1 S D1 In/Out
11 NC NC
12 INT S INT
13 NMI VCC
14 HALT VCC
15 MREQ S MRQ Out
16 IORQ S IORQ Out
17 NC NC
8-BIT
DATA BUS
DATA BUS
INTERFACE
INTERNAL DATA BUS ALU
REGISTER
ARRAY
CPU
TIMING
ADDRESS
LOGIC AND
BUFFERS
16-BIT
ADDRESS BUS
Function
In Clock
Data bus
Data bus
Data bus
Data bus
— +5V
Data bus
Data bus
Data bus
Data bus
— NC
In Interrupt request signal
Non-maskable interrupt
—
signal
— +5V
Memory request signal
Input / Output request signal
— NC
Pin Signal
Symbol In/Out
No. name
18 RD S RDS Out
19 WR S WRS Out
20 BUSAK BUSAK Out
21 WAIT S WAIT
22 BUSRQ BUSRQ
23 RESET S RES
24 M1 S M1 Out
25 RFSH NC
26 GND GND
27 A0 S A0 Out
28 A1 S A1 Out
29 A2 S A2 Out
30 A3 S A3 Out
31 A4 S A4 Out
32 A5 S A5 Out
33 NC NC
34 A6 S A6 Out
35 A7 S A7 Out
36 A8 S A8 Out
37 A9 S A9 Out
38 A10 S A10 Out
39 NC NC
40 A11 S A11 Out
42 A13 S A13 Out
43 A14 S A14 Out
44 A15 S A15 Out
2-5. Z80 CTC
1) Features
Four independently programmable counter/timer channels, each
with a readable downcounter and a selectable 16 or 256 prescaler.
Downcounters are reloaded automatically at zero count.
Selectable positive or negative trigger initiates timer operation.
Three channels have Zero Count/Timeout outputs capable of driv-
ing Darlington transistors. (1.5mV @ 1.5V)
NMOS version for cost sensitive performance solutions.
CMOS version for the designs requiring low power consumption
NMOS Z0843004 - 4 MHz, Z0843006 - 6.17 MHz.
CMOS Z84C3006 - DC to 6.17 MHz, Z84C3008 - DC to 8 MHz,
Z84C3010 - DC to 10 MHz
Interfaces directly to the Z80 CPU or—for baud rate generation—
to the Z80 SIO.
Standard Z80 Family daisy-chain interrupt structure provides fully
vectored, prioritaized interrupts without external logic. The CTC
may also be used as an interrupt controller.
6 MHz version supports 6.144 MHz CPU clock operation.
2) General description
The Z80 CTC, hereinafter referred to as Z80 CTC or CTC, four-chan-
nel counter/timer can be programmed by system software for a broad
range of counting and timing applications. The four independently
programmable channels of the Z80 CTC satisfy common microcom-
puter system requirements for event counting, interrupt and interval
timing, and general clock rate generation.
System design is simplified because the CTC connects directly to
both the Z80 CPU and the Z80 SIO with no additional logic. In larger
systems, address decoders and buffers may be required.
Function
Rread signal
Write signal
Bus acknowledge signal
In Wait signal
In Bus request signal
In Reset signal
Machine cycle one signal
— NC
— GND
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
— NC
Address bus
Address bus
Address bus
Address bus
Address bus
— NC
Address bus
Address bus
Address bus
Address bus