Sharp ER-A770 Manual page 49

2-10. ISP2032
This IC has been developed specially for UP-3300 to achieve VGA
CHIP and PSRAM interfaces.
Pin descriotion
Pin
Name I/O
No.
VIDEO MEMORY DECODE
C00000H
1 /VMEM In
16bit/8bit access, 8 bit read from the
CPU is treated as 16-bit on the VGA.
VIDEO MEMORY DECODE (ONLY FOR
GRAPHICS MODE; 8BIT)
C80000H
/VMEM and /VMEM2 differ in their
2 /VMEM2 In apparent address to each other, but the
contents of memory to be accessed are
the same.
They differ in access method
(WORD/BYTE).
3 /HWR In HIGH BYTE WRITE FROM CPU
4 /LWR In LOW BYTE WRITE FROM CPU
5 PHAI In CLOCK FROM CPU
6 VCC
7 /ISPEN In for ISP (In System Program)
8 /VWAITI In WAIT FROM VGA CHIP (IOCHRDY)
WAIT TO MPCA
There are following 2 ORs.
IOCHRDY from VGA CHIP
9 /VWAIT Out
1 WAIT is generated when VRAM.
VGA I/O is accessed. (Because
IOCHRDY is slow, 1 WAIT is generated
prior to it.)
DELAYED WRITE (FOR VGA CHIP
10 /DWRI In
TIMING)
11 /DWRO Out WRITE FOR /DWRI
DELAYED READ (FOR VGA CHIP
12 /DRDI In
TIMING)
13 /DRD Out READ FOR /PRDI
RESET OUTPUT
14 RES Out
RESET
15 /RES In /RESET INPUT
16 A0 In A0
17 GND
18 A20 In A20
EXTENDED PSRAM1 DECODE (EVEN)
19 PCE21E Out
800000H
EXTENDED PSRAM1 DECODE (ODD)
20 PCE210 Out
800000H
EXTENDED PSRAM2 DECODE (ODD)
21 PCE220 Out
900000H
EXTENDED PSRAM2 DECODE (EVEN)
22 PCE22E Out
900000H
23 /IPLON0 In IPL SIGNAL
24 /PSRF0 Out PSRAM REFRESH
25 /OWR Out PSRAM WRITE (ODD SIDE)
MODE3 BUS SWAP (FOR PSRAM
26 /M3SWP Out
ACCESS WHEN IPL)
27 Y2/SCLK ISP
28 VCC
29 Y1/RESET ISP
30 MODE ISP
EXTENDED PSRAM2 DECODE
31 RASPN2E In (FROM MPCA)
800000H
Function
C1FFFFH
C9FFFFH 8-bit access only.
NOT (/RESET)
8FFFFFH
8FFFFFH
9FFFFFH
9FFFFFH
9FFFFFH
Pin
Name I/O
No.
EXTENDED PSRAM2 DECODE
32 RASPN2 In (FROM MPCA)
800000H
PSRAM DECODE (FROM MPCA)
33 /RASPN12 In
600000H
34 /AS In /AS FROM CPU
35 /RD In /RD FROM CPU
36 /RFSH In /RFSH FROM CPU
37 /SMEMR Out VIDEO MEMORY READ (TO VGA CHIP)
VIDEO MEMORY WRITE (TO VGA
38 /SMEMW Out
CHIP)
39 GND
40 /COE0 Not used
41 /IORD Out VGA IO READ (TO VGA CHIP)
42 /IOWR Out VGA IO WRITE (TO VGA CHIP)
43 /SBHE Out BUS HIGH ENABLE (TO VGA CHIP)
44 /VIO2 Out VGA IO CHIP SELECT
3. Address map
3-1. Total memory space
The address map of the total memory space is shown below. As you
can see, the memory space is divided into the following 5 blocks:
0page area (including the I/O area)
VRAM
RAM
ROM
Extended I/O area
000000h
0 page area
(64KB)
00FFFFh
200000h
Flash
(4MB)
600000h
RAM
(6MB)
C00000h
VRAM
(1MB)
D00000h
EP-ROM
(2MB)
F00000h
Extended I/O area
(1MB)
FFFFFFh
Fig. 2
Function
9FFFFFH
9FFFFFH
* In the 0 page area, lower 64KB
or less of the flash area is
mapped.
By mapping the ROM area, the
reset start and other vectors
become addressable.
* The expanded I/O area means
the space for the I/O device
addressed in the area excluding
the 0 page one.
MPCA8 uses FFFF00h to
FFFFFFh for the addressed
register (BAR) of SSP.
The I/O register for VGAC is
included.