Advertisement
Philips Semiconductors
40 Msps, 10-bit analog-to-digital
interface for CCD cameras
SYMBOL
Clamps
g
ADC clamp transconductance
m(ADC)
g
CDS clamp transconductance
m(CDS)
Analog-to-Digital Converter (ADC)
f
maximum clock frequency
CLK(max)
t
clock pulse width HIGH
CPH
t
clock pulse width LOW
CPL
SR
clock input slew rate (rising and
CLK
falling edge)
V
ADC input voltage level
i(ADC)(p-p)
(peak-to-peak value)
V
ADC reference voltage output
RB
code 0
V
ADC reference voltage output
RT
code 1023
I
ADC input current
ADCIN
INL
integral non-linearity
DNL
differential non-linearity
t
sampling delay time
d(s)
Total chain characteristics (CDS + AGC + ADC)
t
delay between SHD and CLK
d
N
total output noise (RMS value)
tot(rms)
V
maximum offset between CCD
offset(fl-d)
floating level and CCD dark pixel
level
V
equivalent input noise voltage
n(i)(eq)(rms)
(RMS value)
Digital-to-Analog Converter (OFDOUT)
V
additional 8-bit control DAC
OFDOUT(p-p)
(OFD) output voltage
(peak-to-peak value)
V
DC output voltage for code 0
OFDOUT(0)
V
DC output voltage for code 255
OFDOUT(255)
2002 Oct 23
PARAMETER
CONDITIONS
at clamp level
at clamp level
10% to 90%
ramp input
ramp input
50% at rising edges
CLK and SHD: transition full
scale code 0 to 1023;
f
= 120 MHz;
cut(CDS)
f
= 54 MHz;
cut(AGC)
V
= 600 mV
i(CDS)
f
= 120 MHz;
cut(CDS)
f
= 40 MHz; note 2
cut(AGC)
G
= 4.5 dB
AGC
G
= 34.5 dB
AGC
AGC gain = 34.5 dB
AGC gain = 4.5 dB
10
Product specification
TDA8783
MIN.
TYP.
MAX.
7
1.5
40
12
12
0.5
2
1.5
3.5
2
+120
0.6
1.5
0.2
0.75
5
30
0.125
1.6
200
+200
125
150
1.4
2.3
3.7
UNIT
mS
mS
MHz
ns
ns
V/ns
V
V
V
A
LSB
LSB
ns
ns
LSB
LSB
mV
V
V
V
V
V
Advertisement
