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Philips Semiconductors
40 Msps, 10-bit analog-to-digital
interface for CCD cameras
handbook, full pagewidth
handbook, full pagewidth
SDATA
SCLK
SEN
t
= t
= t
= 4 ns (min.); t
su1
su2
su3
Fig.4 Loading sequence of control DACs input data via the serial interface.
2002 Oct 23
SDATA
D0
SCLK
LSB
SEN
8
(D7 to D0)
(D8 to D0)
OFD
AGC GAIN
LATCHES
LATCHES
8-bit DAC
AGC control
Fig.3 Serial interface block diagram.
MSB
A2
A1
A0
D9
t su1
= t
= 4 ns (min.).
hd3
hd4
SHIFT REGISTER
D1
D2
D3
D4
D5
D6
10
9
8
(D7 to D0)
FREQUENCY
STANDBY
LATCHES
AND EDGE
frequency
control
CDS and AGC
or edge clocks
t su2
t hd4
D8
D7
D6
D5
12
D7
D8
D9
A0
A1
A2
MSB
LATCH
SELECTION
7
10
(D6 to D0)
(D9 to D0)
CLAMP
PARTIAL
REFERENCE
LATCHES
standby
10-bit DAC
control
MGM515
LSB
D4
D3
D2
D1
D0
Product specification
TDA8783
MGE373
t hd3
t su3
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