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Section IV
4-24. PRINTER AND DUMP HOLD CYCLING.
4-25. A low on the Dump Hold line or
a
high on the
Printer Hold line gives
a
high at the Cycle Control
one-shot
IC39 pin
2
to cause a
single
input
and
output Storage cycle.
4-26. PANEL TRANSFER.
4-27. On the Output Cycle
on
Storage (Mem)
mode,
A21C22 pin
8 goes
low to turn
off
Al Q4
and
Transfer the
Data from the MOS Shift Registers to the front panel
readout. Al Q5
saturates
to hold Oock Control low to
prevent the
3480
from taking
a
reading. Q6
saturates
to
hold Reset low to hold the
3480
Data flip-flops in the high
state.
4-28. When Panel Transfer goes low after outputting the
Data, it triggers Al IC39 to reset the Units Address Counter
IC32 to allow the Storage to skip
a single
reading
after
it
has
completed
an Output
cycle.
This is necessary because
when the Oock Control and Reset
lines are
allowed to
go
back high, they erroneously trigger the
3480 for a
reading.
4-29. The high Panel Transfer
at AlQ4
holds IC35 pin 4
high to allow
the
pushbutton on the plug-in unit of the
3480
to trigger the
Cycle Control
one-shot through the
External Trigger line to give a Storage
cycle.
4-30. BASIC COUNTER.
4-31
.
The basic storage operation
is
around a
counter
that
keeps track of how many readings have been inputted
and
outputted. The basic count pulse is generated
at
IC46 pin
11
on
the A2 assembly
and
is transferred across guard
through Ll8 to
a
4 µs one-shot
consisting
of IC37 pins 4
through 10 on the
Al
assembly.
This count pulse is gated
by
scanner
functions at IC35 on the
Al
assembly.
It
is
inverted and counted by
a
decade
counter
IC32.
Every
10
counts into this counter
generates one output
pulse which
is transferred back
across
guard to the outguard
section
by
Ll2,
amplified
by IC19 pins I and
2
on the A2 assembly
,
and
counted
by four
flip-flops,
IC's 43 and 44. While the
1Il80A
is capable
of taking in 50 readings
and
outputting
50 readings, the counter actually
acts
as
a
I 00 counter. The
frrst 50 as input; the second 50 as output. The first three
flip-flops of the Tens Counter are the ten, twenty and forty
bits, while the fourth flip-flop is the
IO
(Input/Output)
Flip-Flop.
4-32. The Tens Counter
counts
in
a
50 sequence. At each
reset, the
IO
Flip-Flop changes state, unless an Input Cycle
Hold signal holds
it
in one state or the other. The Reset
pulse is generated by IC45 pin 8 on the A2 assembly. A
delay by Ll9 produces the pulse width. The Reset pulse
does not actually come after the 49th reading, but after the
50th
;
so the reset takes place on the first cycling after the
50th reading has been inputted or outputted, thus causing
4-2
Model l l l
80A
the counter to count in a l -through-50 sequence instead of
the usual l-through-49.
4-33. The Reset pulse also
"enables"
the Measurement
Hold Flip-Flop at IC32 pin 5
on
A2,
and
resets the Jump
Flip-Flop at IC32 pin 10 on A2. This pulse will also be
outputted
on the Status Flag line if the Status Flip-Flop is
in Input Cycle Hold, thus
giving
an indication of when the
counter
has
completed
a complete
cycling.
This
can
be
useful in triggering such things as a high speed D-to-A
converter
or an oscilloscope display of the output data. The
outputs of the Units Counter
are
inverted and OR'ed in
with information from the 3485A Scanner by AIIC29 and
IC30, and
go
out as Storage
count
data. The Tens Counter
outputs are
also buffered and
outputted.
The Flip-Flop
output is buffered along with the Reset pulse by IC38 pins
3
through 6. IC3 7 pins 11 through 13
and
ICI 8 pins 8 and
9.
4-34. The
IO
Flip-Flop
is
used throughout the l l I 80A to
gate
different functions.
It
goes to IC23 pin I to create a
Storage Flag during
the output
time.
It
also goes to IC45
pin I and
gates
the
ability of Encode signal
to cause a
storage cycle.
This operation is used
only
with
a
computer.
It
also
goes
to IC46 pin 5 and "holds" the mainframe
through Al LI2 to
stop
internal
sampling,
and goes to the
S/H Trigger Inhibit line to
stop
the
trigger capabilities
of
the 11186
Sample/Hold
unit. During
this
time,
it
also gates
IC22 pin
9
to
generate a
Panel Transfer
condition
to put
the data
of
the MOS
shift
registers back to the front panel.
During the input
cycle only,
the
IO
Flip-Flop gates IC31
pin 12,
allowing
the
Scanner
to give a Jump Command
under
Scanner Control Enable only.
4-35. Input Cycle Hold, which goes directly to IC44,
prevents
IO
Flip-Flop from returning to the output
cycle.
This command
can
be
overridden
if the Preset Trigger gate,
consisting of
IC20 pins I
through
6 and gate IC20 pins 11
through 13 are used. This Preset Flip- Flop stores the
information that a Preset Trigger has occurred at IC4 pins
3,
4, or 5, and then gates the Reset pulse through IC20 pins
12 and 11 to
"clear"
the
IO
Flip-Flop back to the output
state.
4-36. The series of events goes as follows: Under Input
Cycle Hold, continuous input sampling takes place. At the
time of
a
Preset Trigger, the Tens and Units Address
counters are in the proper state and the Input Cycle Hold
override flip-flop IC20 is
"set".
The next time a Reset pulse
occurs at the end of an input cycle, the IO Flip-Flop is
cleared and starts an output cycle, and the Input Cycle
Hold overide flip-flop is reset and waits for another Preset
Trigger. At the end of this output cycle, the
IO
Flip-Flop
returns to an input cycle to await another Preset Trigger.
4-37. PRESET TRIGGERS.
4-38. There are three Preset Trigger Lines - Preset 0, 10 and
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