HP 13255 Manual page 14

13255
Memory Controller
13255-91252/12
REV JUN-23-81
3.9
3.9.1
3·9·3
MEMORY CYCLE GENERATOR
The memory cycle generator is a synchronous sequntial state machine
composed of several flip flops and gates. The purpose of this state
machine is to generate the row and column address strobes for memory
cycle operations with the appropriate timing.
A memory cycle begins when HEMGO goes low. This is synchronized with
the leading edge of REQ by a 74s74 flip flop (071). This also accom-
plishes the rising edge clock synchronization mentioned above in sec-
tion 3.6.2, as REQ is synchronized with the clock by the processor.
The output of this flip flop (071-9) represents a memory cycle pending.
This signal is ANDed with RFSH to prevent a memory cycle from starting
while a refresh cycle is in progress. The output of this gate(Ul5-6)
indicates an active memory cycle. The leading (negative) edge of this
cycle active signal sets HEM BUSY to the true state, thus
the start of any refresh cycle; it also clocks a 74LSl12
preventing
flip flop
which starts MEMRAS, the row address strobe (Ul2-12). Two flip flops
(U13 and U25) then maintain HEMRAS in the low state for 2 clock cycles
(408 nsec). The output of the second flip flop (U25-9) is the column
address strobe, CAS. It lasts for one clock cycle (204 nsec) and fol-
lows the leading edge of HEMRAS by 204 nsec subject to logic delays.
As
with the refresh cycle generator, two 74LS74 D flip flops (U21) are
used to extend the memory cycle to allow for RAS pre charge time. The
output of the second of these (U21-5) resets HEM BUSY to the false
state, thus ending the memory cycle.
MEMRAS is ted to a delay line (HP part I 1810-0384, 50 nsec delay, taps
at 10 nsec intervals) where it is delayed 40 nsec to become
R/C,
the
signal which determines which halt of the address is fed through the
address multiplexers (see section 3.4.2).