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Theory
4-82.
PULSE CIRCUITS.
4-83. See schematic 7. Also refer to the
voltages
and
waveforms
on figure 4-5
a
nd figures
8-21, -22, and
-23.
The
pulse
circuits
control
the storage
a
nd
variable
persistence
elements
in
the CRT.
4-84. Pulse
Generator.
The
pulse generator con-
sists of current source A5Q31, relaxation oscillator
A5Q32,
and monostable
multi
vibrator
A5Q33/
A5Q34.
The
current
through A5Q31 is determined
by either
the
PERSISTENCE
control
or
by
the store time adj
control
on schematic 6. Either of
these controls, when
set
full
counterclockwise,
will
reverse
bias A5Q31
and
disable
the pulse
generator.
As
either control is
set
more
clockwise,
A5Q31 conducts more
current.
This
charges
A5C24
faster and
increases the pulse
generator
frequency
as explained
in the following
paragraph.
4-85.
When A5C24
charges
to the firing point
of
uni-
junction transistor
A5Q32,
the transistor
conducts,
discharges A5C24, a
nd
generates a
positive
spike
across
A5R104. The
spike
triggers
the monostable
multivibrator.
The
monostable multivibrator gen-
erates
a
negative
going
pulse
about
10 microseconds
wide at the collector of
A5Q33. When A5C24 dis-
cha
rges to 0
volt,
A5Q32
turns
off
and
A5C24
starts
charging
again to repeat the cycle.
4-86. inverter.
The inverter
is
a
common emitter
a
mplifier
that
functions
as
a
logic
inverter and
as
a
transistor switch to control
the flood
gun gate
(A5Q36) a
nd the
write
gate
(A5Q37).
4-87.
Flood
Gun
Gate
and
Write
Gate.
The
flood gun
gate
(A5Q36) and
the write
gate (A5Q37)
a
re
common emitter amplifiers that
function
as
logic
inverters
and
tra
nsistor
switches to control
the
outputs
of
the
pulse circuits.
Two
switches are
required be-
cause
some of the
circuits need
to
be
isolated from
each
other.
Both
gates
function
as
negated
OR (NOR)
circuits
because
both can be activated
from
either
of
two
inputs. Both h
a ve
common inputs
at
the
collector
of
A5Q35
and
both h
ave
a
common input
at the
junction
of
A5R113 a
nd A5R114.
4-88. Erase Timing Circuit.
The
erase
timing
circuit
consists
of
A5CR38, A5CR39, A5R123,
and
A5C35.
The input to the
erase
timing
circuit
is
at
the
anode of
A5CR38
and
its two
outputs are to
the
base of A5Q48
and
to the base of A5Q52. When
+
158
volts
is
applied
from the ERASE switch
on
schematic
6,
A5CR38
and
A5CR39
turn
on.
The
voltage at
the
junction
of
the
two diodes rises from
0 volt to
about
+4.5
volts. This positive
change
is
coupled
through
A5C55
to the
base
of
A5C52
but it has no
effect
because
A5C52
is
already turned on.
At
the end of
prime
time (when the ERASE pushbutton is
re-
leased),
A5CR38
and
A5CR39 turn
off.
The
voltage
a
t the junction
of
the
two diodes drops to 0
volt.
4-6
Model
1331A
This negative change
is
coupled through
A5C35, drop-
ping the voltage
at
the base of A5Q52 toward
-4.5
volts.
Immedia tely,
the
capacitor starts
charging
through
A5R123 towa
rds
+50
volts.
The time required
to charge A5C35
to +1.4 volts (turn
on voltage.
for
A5Q52 and
A5Q39)
is approximately
800
milliseconds.
This
is
the
basic
timing for the erase
cycle.
4-89. Erase
Switch.
The
erase switch,
A5Q52
and
A5Q39,
is
a Da
rlington pair functioning
as a
transistor
switch.
The
Darlington
configuration
per-
mits a
la
rger
current
to be
switched
with
a
small
input
current.
Norma lly,
both transistors
are
turned
on
and the collector
of A5Q39
is
clamped near
0
volt.
When
the
negative
going
transition
of
the prime
time
pulse
is coupled to
the
base
of
A5Q52,
both
transistors turn
off
until
A5C35
charges
back up
to
+l.4
volts. During
this
time, A5CR51 clamps the
collector of
A5Q39 to
+50
volts. The
collector
of A5Q39
is
one output
of the
erase
switch
.
The
other
is
at
the other side
of
A5CR40.
When
A5Q39
is
turned
on,
A5CR40 is turned
on
a
nd
its anode
is
clamped
to
+0.6
volts.
When
A5Q39
is turned
off, A5CR40
turns
off and its
a node rises
to
+4.7
volts.
4-90. Blanking
Gate.
The
bla
nking
gate,
A5Q48,
is a
common
emitter amplifier
that functions
as a
logic
inverter
and
transistor
switch.
Because it
can
be
con-
trolled from
any of three
different inputs, it also
fun ctions
as a three-input
negated OR (NOR)
gate.
The three
inputs
a re:
the output of the
erase
timing
circuit
from the
cathode of A5CR39,
the output of
the
erase
switch
at the a
n ode of
A5CR40,
and
the
output
of the write gate from the
collector
of
A4Q37.
During
write
mode,
a
ll
three
of its inputs
are
LO
and
its output is HI. During
store mode,
the input
from
the write
gate
is HI
and
its output is LO.
During
the
erase
function,
the
input from the
erase
switch
is HI during
prime
time
and
the input from
the erase
timing
circuit
is
HI during the
erase
timing
period; consequently,
the
output
is
LO
during the
entire
erase
function.
4·91.
Storage
Gate.
The
storage
gate,
A5Q41,
is
a common emitter amplifier
functioning
as a
transistor
switch and
logic inverter.
Because
it is
activated
from
either
of two
inputs, it
a
lso fundions
as a
negated
OR (NOR) logic
gate. The
two inputs
are:
from the
pulse generator at the collector of
A5Q33,
and
from
the
write
gate at the collector
of A5Q37.
In
write
mode,
the
input from the write gate is LO
and
the
pulses
from the pulse
generator
turn the
gate
on
and
off so
that the output is a train of pulses.
In
store
mode,
the output from the write gate is HI
and
the
output
is clamped
LO.
During the
erase
timing period
(800
milliseconds),
both inputs are LO
and
the
output
tends
to
go
HI, but
the
change
is
an
RC
curve
because current
is being drawn by the
storage erase
circuit.
1·92.
Storage
Erase
Circuit.
The
storage erase
circuit
consists
of
switch
A5Q42
and
Darlington pair
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