Table 3-17 Pci Cardbus Cis Pointer Register; Table 3-18 Pci Subsystem Vendor Id Register; Table 3-19 Pci Subsystem Id Register; Table 3-20 Pci Expansion Rom Base Register - GE PCIE-5565PIORC* Hardware Reference Manual

Table 3-17 PCI Cardbus CIS Pointer Register

Bit Description
31:0 Cardbus Information Structure Pointer for PCMCIA. Not Supported.

Table 3-18 PCI Subsystem Vendor ID Register

Bit Description
15:0 Subsystem Vendor ID (unique add-in board Vendor ID). Yes
*NOTE: The value $1556 denotes a PLD Application.

Table 3-19 PCI Subsystem ID Register

Bit Description
15:0 Subsystem ID (unique add-in board device ID).
*NOTE: The value $0080 denotes a PLD Application PCI-X core.

Table 3-20 PCI Expansion ROM Base Register

Bit Description
0 Address Decode Enable.
A one (1) indicates a device accepts accesses to the Expansion ROM address.
A zero (0) indicates a device does not accept accesses to Expansion ROM
space. Should be set to zero (0) if there is no Expansion ROM. Works in
conjunction with EROMRR[0].
10:1 Reserved
31:11 Expansion ROM Base Address (upper 21 bits).
*NOTE: PCI Expansion ROM and related registers are not applicable to the Reflective Memory.

Table 3-21 PCI Capability Pointer Register

Bit Description
7:0 New Capability Pointer. Offset into PCI Configuration Space for the location
of the first item in the New Capabilities Linked List.
31:8 Reserved
PCI Cardbus CIS Pointer: Offset $28
PCI Subsystem Vendor ID: Offset $2C
Read
PCI Subsystem ID: Offset $2E
Read
Yes
PCI Expansion ROM Base: Offset $30
Capability Pointer: Offset $34
Value after
Read Write
PCI Reset
Yes No $0
*Value after
Write
PCI Reset
No $1556
*Value after
Write
PCI Reset
No $0080
*Value after
Read Write
PCI Reset
Yes No 0
Yes No $0
Yes Yes $0
Value after
Read Write
PCI Reset
Yes No $78
Yes No $0
Programming 37