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DESCRIPTION
The µ PD75512 is a 4-bit single-chip microcomputer which employs 75X series architecture, and its perform-
ance is comparable to that of an 8-bit microcomputer.
In addition to its high-speed processing capabilities, the µ PD75512 is also capable of processing data in units
of 1, 4, or in 8-bits. With its internally provided A/D converter and serial interface, the µ PD75512 provides the
highest performance in its class.
Detailed functions are described in the following user's manual. Be sure to read it for designing.
FEATURES
• Adequate I/O lines: 64
(can be provided pull-up/pull-down resistors: 47)
• Built-in 8-bit serial interface: 2-ch
NEC standard serial bus interface (SBI) internally provided
• Built-in 8-bit A/D converter: 8-ch
• Variable instruction execution time function which is convenient for high-speed operation and power saving
· 0.95 µ s/1.95 µ s/15.3 µ s (at 4.19 MHz operation),
· 122 µ s (at 32.768 kHz operation)
• Program memory (ROM) size: 12,160 × 8 bits
• Data memory (RAM) size: 512 × 4 bits
• High-performance timer function: 4-ch
· 8-bit timer/event counter
· Clock timer
· 8-bit basic interval timer
· Timer/pulse generator: Capable of outputting 14-bit PWM
• Clock operation for reduced power consumption possible
(5 µ A TYP. at 3 V operation)
• PROM version ( µ PD75P516) available
APPLICATIONS
VCRs, CD players, telephones, cameras, etc.
Document No.
IC-2569D
(O. D. No.
IC-7833E)
Date Published
November 1993 P
Printed in Japan
DATA SHEET
4-BIT SINGLE-CHIP MICROCOMPUTER
µ PD75516 User's Maual: IEM-5049
The information in this document is subject to change without notice.
The mark
shows major revised points.
MOS INTEGRATED CIRCUIT
µ PD75512
© NEC Corporation 1990
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Table of Contents
Related Manuals for NEC mPD75512
Summary of Contents for NEC mPD75512
- Page 1 (can be provided pull-up/pull-down resistors: 47) • Built-in 8-bit serial interface: 2-ch NEC standard serial bus interface (SBI) internally provided • Built-in 8-bit A/D converter: 8-ch • Variable instruction execution time function which is convenient for high-speed operation and power saving ·...
- Page 2 (14 × 20mm) Remarks: xxx is ROM code number. Please refer to “Quality Grade on NEC Semiconductor Devices” (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. µ PD75512 FUNCTIONS...
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Page 3: Table Of Contents
µ PD75512 CONTENTS PIN CONFIGURATION ........................TYPICAL SYSTEM CONFIGURATION .................... INTERNAL BLOCKDIAGRAM ......................PIN FUNCTIONS ..........................PORT PINS ............................. NON-PORT PINS ........................... PIN INPUT/OUTPUT CIRCUITS ......................RECOMMENDED CONDITIONS FOR UNUSED PINS ................MASK OPTION SELECTION ......................... MEMORY CONFIGURATION ......................PERIPHERAL HARDWARE FUNCTIONS ..................19 PORT .............................. - Page 4 µ PD75512 13. PACKAGE DRAWINGS ........................14. RECOMMENDED SOLDERING CONDITIONS ................64 APPENDIX A. DEVELOPMENT TOOLS ....................APPENDIX B. RELATED DOCUMENTS ....................
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Page 5: Pin Configuration
µ PD75512 PIN CONFIGURATION 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 P140 P141 P142 P143 P113 RESET P112 P111 P110 P103 P102 P101 P00/INT4 P100 P01/SCK0 P02/SO0/SB0 P03/SI0/SB1 P10/INT0 SI1/P83 P11/INT1 SO1/P82 P12/INT2 SCK1/P81 P13/TI0... -
Page 6: Typical System Configuration
µ PD75512 TYPICAL SYSTEM CONFIGURATION VTR (Voltage synthesizer tuner) PD75512 Remote control INT0 Analog Input port input Mechanism Tuner Mechanical Mechanism controller/ control Output Timer Servo IC port Port4, 5 FIP driver Key matrix KR0-KR7 System clock Clock for clock... -
Page 7: Internal Blockdiagram
BASIC PORT 0 P00-P03 INTERVAL TIMER PORT 1 P10-P13 INTBT SP (8) PROGRAM PORT 2 P20-P23 TI0/P13 TIMER/EVENT COUNTER COUNTER (14) PTO0/P20 PORT 3 P30-P33 INTT0 PORT 4 P40-P43* BANK WATCH BUZ/P23 TIMER P50-P53* PORT 5 INTW PORT 6 P60-P63 GENERAL REG. -
Page 8: Pin Functions
µ PD75512 PIN FUNCTIONS PORT PINS (1/2) Input/ Input/ Shared Function 8-bit When Reset Output Name Output Circuit Type* INT4 4-bit input port (PORT0). For P01 to P03, built-in pull-up SCK0 resistors can be specified in 3-bit F -A Input units by software. - Page 9 µ PD75512 PORT PINS (2/2) Input/ Input/ Shared Function 8-bit When Reset Output Name Output Circuit Type* 4-bit input/output port (PORT7). Input/ Built-in pull-up resistor can be output specified in 4-bit units by software. Input SCK1 Input 4-bit input port (PORT8). Input Low level 4-bit input/output port (PORT9).
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Page 10: Non-Port Pins
µ PD75512 NON-PORT PINS Input/ Input/ Shared Function When Reset Output Name Output Circuit Type* Input The external event pulse input pin for the timer/ — B -C event counter. PTO0 Output Timer/event counter output pin Input Output Clock output pin Input Output Fixed frequency output pin (for buzzer output or... -
Page 11: Pin Input/Output Circuits
µ PD75512 PIN INPUT/OUTPUT CIRCUITS The following shows a simplified input/output circuit diagram for each pin of the µ PD75512. TYPE A TYPE D data P–ch P–ch output N–ch N–ch disable Input buffer of CMOS standard Push-pull output that can be set in a output high-impedance state (both P-ch and N-ch are off) TYPE E TYPE B... - Page 12 µ PD75512 Type E-C Type F-B P.U.R. P.U.R. P.U.R. P–ch enable P.U.R. output P–ch enable disable (P-ch) data P-ch IN/OUT IN/OUT Type D data output output disable N-ch disable output disable Type A (N-ch) Type B P.U.R. : Pull-Up Resistor P.U.R.
- Page 13 µ PD75512 Type M-C Type Y-A IN instruction P.U.R. P.U.R. P–ch enable P–ch IN/OUT N–ch – data N-ch Sampling output disable Reference voltage (from a voltage tap of series resistor string) input P.U.R. : Pull-Up Resistor enable Type V Type Z data IN/OUT Type D...
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Page 14: Recommended Conditions For Unused Pins
µ PD75512 RECOMMENDED CONDITIONS FOR UNUSED PINS Table 4-1 Recommended Conditions for Unused Pins Recommended Conditions P00/INT4 Connect to V P01/ SCK0 P02/SO0/SB0 Connect to V or V P03/SI1/SB1 P10/INT0-P12/INT2 Connect to V P13/TI0 P20/PTO0 P22/PCL P23/BUZ Input state: Connect to V or V P30-P33 Output state: Open... -
Page 15: Mask Option Selection
µ PD75512 MASK OPTION SELECTION The following mask options are provided with the pins. Pull-up/pull-down resistor selection Table 4-2 Pull-up/Pull-down Resistor Selection Pins Mask Option P40-P43 (1) With pull-up resistor (2) Without pull-up resistor P50-P53 (Can be specified in bit units) (Can be specified in bit units) P120-P123 P130-P133... -
Page 16: Memory Configuration
µ PD75512 MEMORY CONFIGURATION • Program memory (ROM) ... 12160 words × 8 bits (0000H-2F7FH) • 0000H, 0001H : Vector table to which address from which program is started is written after reset • 0002H-000DH : Vector table to which address from which program is started is written after interrupt •... - Page 17 µ PD75512 Address 0000H Internal reset start address (upper 6 bits) Internal reset start address (lower 8 bits) 0002H INTBT/INT4 start address (upper 6 bits) INTBT/INT4 start address (lower 8 bits) 0004H INT0 start address (upper 6 bits) CALL !addr instruction INT0 start address (lower 8 bits) subroutine...
- Page 18 µ PD75512 Data memory Memory bank 000H General purpose (32 × 4) register 01FH area 008H Stack 256× 4 area Data area Static RAM (512 × 4) 0FFH 100H 256× 4 1FFH Unmapped F80H Peripheral hardware area 128× 4 FFFH Fig.
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Page 19: Peripheral Hardware Functions
µ PD75512 PERIPHERAL HARDWARE FUNCTIONS PORT I/O ports are classified into following kinds: • CMOS input (PORTS 0, 1, 8, 15) : 16 • CMOS input/output (PORTS 2, 3, 6, 7, 9, 10, 11) : 28 • N-ch open-drain input/output (PORTS 4, 5, 12, 13, 14) : 20 Total : 64... -
Page 20: Clock Generator Circuit
µ PD75512 CLOCK GENERATOR CIRCUIT The operation of the clock generator circuit is determined by the processor clock control regiser (PPC) and system clock control register (SCC). This circuit can generate two types of clocks: main system clock and subsystem clock. In addition, it can also change the instruction execution time. -
Page 21: Clock Output Circuit
µ PD75512 CLOCK OUTPUT CIRCUIT The clock output circuit outputs clock pulse from the P22/PCL pin. This clock pulse is used for the remote control output, peripheral LSIs, etc. • Clock output (PCL): Φ, 524, 262, 65.5 kHz (operating at 4.19 MHz) •... -
Page 22: Basic Interval Timer
µ PD75512 BASIC INTERVAL TIMER The µ PD75512 is provided with the 8-bit basic interval timer. The basic interval timer has these functions: • Interval timer operation which generates a reference time interrupt • Watchdog timer application which detects a program runaway •... -
Page 23: Watch Timer
µ PD75512 WATCH TIMER The µ PD75512 has a built-in 1-ch watch timer. The watch timer is configured as shown in Fig. 5-4. • Sets the test flag (IRQW) with 0.5 sec interval. The standby mode can be released by IRQW. •... - Page 24 Internal bus SET1* TMOD0 TOE0 PORT2.0 Bit 2 of PGMB Port 2 input/ Modulo register (8) TM07 TM06 TM05 TM04 TM03 TM02 TM01 TM00 enable output output flag latch mode To serial interface PORT1.3 Coinci- dence TOUT Comparator (8) P20/PTO0 Output Input Reset...
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Page 25: Timer/Pulse Generator
µ PD75512 TIMER/PULSE GENERATOR The µ PD75512 contains a timer/pulse generator, that can be used as the timer or the pulse generator. Timer/pulse generator has the following functions. Function, when used in the timer mode • 8-bit interval timer operation (IRQTPG generation), for which the clock source can be changed in 5 steps. -
Page 26: Serial Interface
µ PD75512 Internal bus MODH MODL Modulo register H (8) Modulo register L (8) TPGM3 MODH(8) MODL Modulo latch (14) Output buffer TPGM1 PWM pulse generator Selector Frequency divider INTTPG TPGM5 TPGM7 IRQTPG set signal = 7.8 ms: f at 4.19MHz) Fig. - Page 27 Internal bus Bit manipulation Bit test test Slave address register CSIM0 SBIC (SVA) Coincidence RELT signal Address comparator CMDT SO0 latch P03/SI/SB1 SET CLR Shift register (SIO0) P02/SO/SB0 Busy/ acknowledge output circuit RELD Bus release/ CMDD command/ acknowledge ACKD detector circuit P01/SCK0 INTCSI0...
- Page 28 µ PD75512 Serial interface (Channel 1) configuration µ PD75512 serial interface (channel 1) has following two modes. • Operation stop mode • 3-line serial I/O mode...
- Page 29 Internal bus manipulation manipulation SIO1 write signal (serial start signal) bit 0 bit 7 SIO1 Serial operation mode (8) CSIM1 Shift register 1 (8) P83/SI1 register 1 (8) P82/SO1 Clear Serial transfer completion flag Serial clock Overflow (EOT) counter (3) Clear P81/SCK1 f /2...
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Page 30: A/D Converter
µ PD75512 A/D CONVERTER The µ PD75512 is provided with an 8-bit resolution analog-to-digital (A/D) converter with eight channels of analog inputs (AN0-AN7). This A/D converter is of a successive approximation type. Internal bus ADM1 ADM6 ADM5 ADM4 Control circuit Sample hold circuit SA register (8) –... -
Page 31: Bit Sequential Buffer
µ PD75512 6.10 BIT SEQUENTIAL BUFFER ..16 BITS The bit sequential buffer is a data memory specifically provided for bit manipulation. With this buffer, addresses and bit specifications can be sequentially up-dated in bit manipulation operation. Therefore, this buffer is very useful for processing long data in bit units. Address bit FC3H FC2H... - Page 32 Internal bus (IME) Interrupt enable flag (IExxx) Decoder IRQBT Both edge INT4 detection VRQn IRQ4 /P00 circuit Noise Edge INT0 elimination detection IRQ0 /P10 circuit circuit Edge INT1 detection IRQ1 /P11 circuit Vector table address Priority control generator IRQCSI0 INTCSI0 circuit INTT0 IRQT0...
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Page 33: Standby Functions
µ PD75512 STANDBY FUNCTIONS In order to fully exploit the µ PD75512 low power dissipation, CPU operation can be stopped by setting the unit to the standby mode, thus, further reducing power dissipation. The µ PD75512 features two standby modes, a STOP mode and a HALT mode. -
Page 34: Reset Function
µ PD75512 RESET FUNCTION When the RESET signal is input, the µ PD75512 is reset and each hardware is initialized as indicated in Table 9-1. Fig. 9-1 shows the reset operation timing. Wait (31.3ms/4.19MHz) RESET input Operation mode or standby mode HALT mode Operation mode Internal reset operation... - Page 35 µ PD75512 Table 9-1 Status of Each Hardware after Reset (2/2) Hardware RESET Input in Standby Mode RESET Input during Operation Serial Shift Register (SIO0) Retained Undefined Interface Operation Mode (Channel 0) Register (CSIM0) SBI Control Register (SBIC) Slave Address Register Retained Undefined (SVA)
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Page 36: 10. Instruction Set
µ PD75512 10. INSTRUCTION SET Operand representation and description Describe one or more operands in the operand field of each instruction according to the operand representation and description methods of the instruction (for details, refer to RA75X Assembler Package User's Manual - Language (EEU-730)). With some instructions, only one operand should be selected from several operands. - Page 37 µ PD75512 Legend of operation field : A register; 4-bit accumulator : B register; 4-bit accumulator : C register; 4-bit accumulator : D register; 4-bit accumulator : E register; 4-bit accumulator : H register; 4-bit accumulator : L register; 4-bit accumulator : X register;...
- Page 38 µ PD75512 Symbols in addressing area field MB = MBE . MBS (MBS = 0, 1, 15) MB = 0 MBE = 0 : MB = 0 (00H-7FH) Data memory MB = 15 (80H-FFH) addressing MBE = 1 : MB = MBS (MBS = 0, 1, 15) MB = 15, fmem = FB0H-FBFH, FF0H-FFFH MB = 15, pmem = FC0H-FFFH...
- Page 39 µ PD75512 Instruc- Mne- chine dress- Skip Operand Bytes Operation tions monics Cyc- Conditions Area A ← n4 Transfer MOV A, #n4 String effect A reg1 ← n4 reg1, #n4 XA ← n8 XA, #n8 String effect A HL ← n8 HL, #n8 String effect B rp2 ←...
- Page 40 µ PD75512 Instruc- Mne- chine dress- Skip Operand Bytes Operation tions monics Cyc- Conditions Area CY ← (fmem.bit) CY, fmem.bit CY ← (pmem Transfer CY, pmem.@L .bit(L CY ← (H+mem CY, @H+mem. .bit) MOV1 (fmem.bit) ← CY fmem.bit, CY )) ← CY pmem.@L, CY (pmem .bit(L...
- Page 41 µ PD75512 Instruc- Mne- chine dress- Skip Operand Bytes Operation tions monics Cyc- Conditions Area CY ← A ← CY, A ← A Accumu- RORC lator A ← A Manipu- lation reg ← reg+1 Incre- reg = 0 rp1 ← rp1+1 ment/ INCS rp1 = 00H...
- Page 42 µ PD75512 Instruc- Mne- chine dress- Skip Operand Bytes Operation tions monics Cyc- Conditions Area (mem.bit) ← 1 Memory/ SET1 mem.bit (fmem.bit) ← 1 fmem.bit )) ← 1 Manipu- pmem.@L (pmem .bit(L .bit) ← 1 lation @H+mem.bit (H + mem (mem.bit) ←...
- Page 43 µ PD75512 Instruc- Mne- chine dress- Skip Operand Bytes Operation tions monics Cyc- Conditions Area (SP-4)(SP-1)(SP-2) ← PC Subrou- CALL !addr 11-0 (SP-3) ← MBE, RBE, PC tine/ 13,12 ← addr, SP ← SP-4 Stack 13-0 (SP-4)(SP-1)(SP-2) ← PC Control CALLF !faddr 11-0...
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Page 44: Electrical Specifications
µ PD75512 ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS (T = 25°C) Parameter Symbol Conditions Ratings Unit Supply Voltage -0.3 to +7.0 Other than ports 4, 5, 12-14 -0.3 to V +0.3 Input Voltage Ports 4, 5, 12-14 w/pull-up -0.3 to V +0.3 resistor Open drain... - Page 45 µ PD75512 MAIN SYSTEM CLOCK OSCILLATOR CIRCUIT CHARACTERISTICS = -40 to +85°C, V = 2.7 to 6.0 V) Recommended Oscillator Item Conditions MIN. TYP. MAX. Unit Constants Ceramic Oscillation = osccillation frequency(f voltage range Oscillation stabiliza- After V came to tion time* MIN.
- Page 46 µ PD75512 Note: When using the oscillation circuit of the main system clock and subsystem clock, wire the portion enclosed in dotted line in the figures as follows to avoid adverse influences on the wiring capacity: • Keep the wiring length as short as possible. •...
- Page 47 µ PD75512 DC CHARACTERISTICS (T = -40 to +85°C, V = 2.7 to 6.0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit High-Level Input Ports 2, 3, 9-11, P80, P82 0.7V Voltage Ports 0, 1, 6, 7, 15, P81, P83, RESET 0.8V Ports 4, 5, 12-14 w/pull-up resistor...
- Page 48 µ PD75512 Parameter Symbol Conditions MIN. TYP. MAX. Unit Supply Current * 4.19 MHz* crystal Ooperation = 5 V±10%* oscillator mode = 3 V±10%* 0.55 C1 = C2 = 22pF µ A HALT mode = 5 V±10% 1800 µ A = 3 V±10% 32.768 kHz* crystal Operation...
- Page 49 µ PD75512 AC CHARACTERISTICS (T = -40 to +85°C, V = 2.7 to 6.0 V) Basic Operation Parameter Symbol Conditions MIN. TYP. MAX. Unit µ s w/main system clock = 4.5 to 6.0 V 0.95 CPU Clock Cycle Time* µ s (Minimum Instruction Execution Time µ...
- Page 50 µ PD75512 Serial Transfer Operation Two-Line and Three-Line Serial I/O Modes (SCK: internal clock output) Parameter Symbol Conditions MIN. TYP. MAX. Unit SCK Cycle Time = 4.5 to 6.0 V 1600 KCY1 3800 SCK High-, Low-Level = 4.5 to 6.0 V /2)-50 KCY1 Widths...
- Page 51 µ PD75512 SBI Mode (SCK: internal clock output (master)) Parameter Symbol Conditions MIN. TYP. MAX. Unit SCK Cycle Time = 4.5 to 6.0 V 1600 KCY3 3800 SCK High-, Low-Level = 4.5 to 6.0 V /2-50 KCY3 Widths /2-150 KCY3 SB0, 1 Set-Up Time SIK3 (vs.
- Page 52 µ PD75512 (3) A/D Converter (T = -10 to +70°C, V = 3.5 to 6.0 V, AV = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution 2.5 V ≤ AV ≤ V ±1.5 Absolute Accuracy* µ s Conversion Time* 168/f CONV µ...
- Page 53 µ PD75512 AC TIMING TEST POINT (excluding X1 and XT1 inputs) 0.8 V 0.8 V Test points 0.2 V 0.2 V CLOCK TIMING X1 input –0.5V 0.4 V XT1 input –0.5V 0.4 V TI0 TIMING...
- Page 54 µ PD75512 SERIAL TRANSFER TIMING THREE-LINE SERIAL I/O MODE: KCY1 SIK1 KSI1 Input data KSO1 Output data TWO-LINE SERIAL I/O MODE: KCY2 KSO2 SIK2 KSI2 SB0,1...
- Page 55 µ PD75512 SERIAL TRANSFER TIMING BUS RELEASE SIGNAL KCY3,4 KL3,4 KH3,4 SIK3,4 KSI3,4 SB0,1 KSO3,4 COMMAND SIGNAL TRANSFER: KCY3,4 KL3,4 KH3,4 SIK3,4 KSI3,4 SB0,1 KSO3,4 INTERRUPT INPUT TIMING: INTL INTH INT0, 1, 2, 4 KR0-7 RESET INPUT TIMING: RESET...
- Page 56 µ PD75512 LOW-VOLTAGE DATA RETENTION CHARACTERISTICS OF DATA MEMORY IN STOP MODE = –40 to +85°C) Parameter Symbol Conditions MIN. TYP. MAX. Unit Data Retention Supply DDDR Voltage Data Retention Supply = 2.0 V µ A DDDR DDDR Current* µ s Release Signal Set Time SREL Oscillation Stabilization...
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Page 57: Performance Curves
µ PD75512 PERFORMANCE CURVES vs V (Main system clock: Crystal oscillator) (T = 25°C) 5000 High-speed mode PCC=0011 Middle-speed mode PCC=0010 Low-speed mode PCC=0000 1000 Main system clock HALT mode Subsystem clock Operation mode Main system clock STOP mode + 32 kHz oscillation and subsystem clock HALT mode... - Page 58 µ PD75512 vs V (Main system clock: Ceramic oscillator) (T = 25°C) 5000 High-speed mode PCC=0011 Middle-speed mode PCC=0010 Low-speed mode PCC=0000 1000 Main system clock HALT mode Subsystem clock Operation mode Main system clock STOP mode + 32 kHz oscillation and subsystem clock HALT mode...
- Page 59 µ PD75512 vs V (Main system clock: Ceramic oscillator) (T = 25°C) 5000 High-speed mode PCC=0011 Middle-speed mode PCC=0010 Low-speed mode PCC=0000 1000 Main system clock HALT mode Subsystem clock Operation mode Main system clock STOP mode + 32 kHz oscillation and subsystem clock HALT mode...
- Page 60 µ PD75512 vs V (Main system clock: Ceramic oscillator) (T = 25°C) 5000 High-speed mode PCC=0011 Middle-speed mode PCC=0010 Low-speed mode PCC=0000 1000 Main system clock HALT mode Subsystem clock Operation mode Main system clock STOP mode + 32 kHz oscillation and subsystem clock HALT mode...
- Page 61 µ PD75512 vs f = 5V, T = 25°C) vs f = 3V, T = 25°C) Middle-speed High-speed mode mode High-speed mode PPC = 0010 PPC = 0011 PPC = 0011 Middle-speed mode [mA] PPC = 0010 Low-speed mode PPC = 0000 [mA] Low-speed mode PPC = 0000...
- Page 62 µ PD75512 vs I (T = 25°C) = 6V = 5V [mA] = 4V = 3V = 2.7V...
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Page 63: Package Drawings
µ PD75512 PACKAGE DRAWINGS 80 PIN PLASTIC QFP (14×20) detail of lead end P80GF-80-3B9-2 NOTE ITEM MILLIMETERS INCHES Each lead centerline is located within 0.15 23.6 ± 0.4 0.929 ± 0.016 mm (0.006 inch) of its true position (T.P.) at maximum material condition. -
Page 64: 14. Recommended Soldering Conditions
For details on the recommended soldering conditions, refer to Information Document "Semiconductor Devices Mounting Manual" (IEI-616). The soldering methods and conditions are not listed here, consult NEC. Table 14-1 Soldering Conditions µ PD75512GF-xxx-3B9: 80-pin plastic QFP (14 × 20 mm) -
Page 65: Appendix A. Development Tools
µ PD75512 APPENDIX A. DEVELOPMENT TOOLS The following development support tools are readily available to support development of systems using µ PD75512: Hardware IE-75000-R * In-circuit emulator for 75X series IE-75001-R IE-75000-R-EM * Emulation board for IE-75000-R and IE-75001-R Emulation prove for µ PD75512, provided with 80-pin conversion socket EP-75516GF-R EV-9200G-80. -
Page 66: Appendix B. Related Documents
µ PD75512 APPENDIX B. RELATED DOCUMENTS... - Page 67 Therefore, when transporting or storing the MOS device, use a conductive tray, magazine case, or conductive buffer materials, or the metal case NEC uses for packaging and shipment, and use grounding when assembling the MOS device system. Do not leave the MOS device on a plastic plate and do not touch the pins of the device.
- Page 68 The devices listed in this document are not suitable for uses in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. If customers intend to use NEC devices for above applications or they intend to use "Standard" quality grade NEC devices for the applications not intended by NEC, please contact our sales people in advance.