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4310, V 4400, V 5000A, V 5432, and V Series are trademarks of NEC Electronics Corporation. MIPS is a registered trademark of MIPS Technologies, Inc. in the United States. MBA is a trademark of Vadem Corporation. Pentium, Intel, and StrataFlash are trademarks of Intel Corporation.
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NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
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Regional Information Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify: •...
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Major Revisions in This Edition (1/5) Page Description Throughout this Separation of the following parts of the previous (the 2nd) edition manual CHAPTER 3 MIPS III INSTRUCTION SET SUMMARY, CHAPTER 4 MIPS16 INSTRUCTION SET, CHAPTER 5 V 4181 PIPELINE, CHAPTER 6 MEMORY MANAGEMENT SYSTEM (first half), CHAPTER 7 EXCEPTION PROCESSING (second half), CHAPTER 9 CACHE MEMORY, CHAPTER 10 CPU CORE INTERRUPTS, CHAPTER 27 MIPS III INSTRUCTION SET DETAILS, CHAPTER 28 MIPS16 INSTRUCTION SET FORMAT...
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Major Revisions in This Edition (2/5) Page Description p. 119 Modification of description in 6.3.2 Connection to external ROM (x 16) devices p. 122 Modification of Remark in 6.3.3 (4) 64 Mbit PageROM p. 123 Modification of figure in 6.3.3 (5) 32 Mbit flash memory (when using Intel DD28F032) Modification of Figure 6-3 through Figure 6-8 pp.
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Major Revisions in This Edition (3/5) Page Description p. 198 Modification of description of Cautions in 10.5.4 Activation via DCD interrupt request pp. 201 to 204 Modification of descriptions in 10.6.1 through 10.6.4 pp. 205 to 207 Addition of 10.6.5 through 10.6.8 Modification of description for bit 6 in 10.7.1 PMUINTREG (0x0B00 00A0) p.
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Major Revisions in This Edition (4/5) Page Description p. 333 Modification of signal names in Figure 17-1. CompactFlash Interrupt Logic p. 333 Modification of description for bit 0 in 17.3.3 CFG_REG_1 (0x0B00 08FE) p. 336 Addition of Caution for bit 4 in 17.4.3 PWRRSETDRV (Index: 0x02) Modification of description for bit 7 in 17.4.4 ITGENCREG (Index: 0x03) p.
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Major Revisions in This Edition (5/5) Page Description p. 399 Modification of description in 21.1.1 LCD interface p. 401 Modification of bus width in Figure 21-1. LCD Controller Block Diagram p. 406 Modification of description in 21.3.4 Frame buffer memory and FIFO Addition of Remark in 21.4.11 LCDCFGREG0 (0x0A00 0414) p.
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PREFACE Readers This manual targets users who intend to understand the functions of the V 4181 and to design application systems using this microprocessor. Purpose This manual introduces the hardware functions of the V 4181 to users, following the organization described below. Organization Two manuals are available for the V 4181: Hardware User’s Manual (this manual)
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Related Documents When using this manual, also refer to the following documents. Document name Document number 4181 Hardware User’s Manual This manual µ PD30181 (V 4181) Data Sheet U14273E 4100 Series Architecture User’s Manual U15509E Series Programming Guide Application Note U10710E The related documents indicated here may include preliminary version.
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LIST OF FIGURES (3/3) Fig. No. Title Page 14-1. PIU Peripheral Block Diagram ........................276 14-2. Coordinate Detection Equivalent Circuits ....................277 14-3. Internal Block Diagram of PIU ........................277 14-4. Scan Sequencer State Transition Diagram ....................278 14-5. Interval Times and States ........................... 286 14-6.
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LIST OF TABLES (1/2) Table No. Title Page 1-1. Supported PClock and TClock Frequencies ....................31 1-2. Devices Supported by System Bus ......................31 1-3. GPIO(31:0) Pin Functions ........................... 33 1-4. LCD Panel Resolutions (in Pixels, TYP.) ....................34 1-5. Functions of LCD Interface Pins when LCD Controller Is Disabled ............
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LIST OF TABLES (2/2) Table No. Title Page 13-5. Serial Interface Channel 1 (SIU1) Loopback Control .................. 239 13-6. Serial Interface Channel 2 (SIU2) Signals ....................240 13-7. Serial Interface Channel 2 (SIU2) Loopback Control .................. 240 13-8. STN Color LCD Interface Signals ....................... 241 13-9.
The V 4181, which is a high-performance 64-/32-bit microprocessor employing the RISC (reduced instruction set computer) architecture developed by MIPS , is one of the V -Series microprocessor products manufactured by NEC Electronics. The V 4181 contains the V 4110 CPU core of ultra-low-power consumption with cache memory, high-speed product-sum operation unit, and memory management unit.
CHAPTER 1 INTRODUCTION 1.2 Ordering Information Part number Package Maximum internal operating frequency µ PD30181GM-66-8ED 160-pin plastic LQFP (fine pitch) (24 × 24) 66 MHz 1.3 V 4181 Key Features Figure 1-1. Internal Block Diagram ROM/ DRAM/ Flash LCD Panel memory SDRAM System bus (ISA)
CHAPTER 1 INTRODUCTION 1.3.1 CPU core The V 4181 integrates an NEC Electronics’ V 4110 CPU core supporting both the MIPS III and MIPS16 instruction sets. The V 4181 supports the following pipeline clock (PClock) and internal bus clock (TClock) frequencies. The PClock is set by attaching pull-up or pull-down resistors to the CLKSEL(2:0) pins.
CHAPTER 1 INTRODUCTION 1.3.3 Memory interface The V 4181 provides control for both ROM/flash memory and DRAM. Up to four 16-bit ROM/flash memory banks may be supported utilizing either 32-Mbit or 64-Mbit single cycle or page mode devices. Bank mixing is not supported for ROM/flash memory.
CHAPTER 1 INTRODUCTION 1.3.12 Clocked serial interface (CSI) The V 4181 provides a clocked serial interface (CSI) which has an option to be configured as general-purpose I/O pins. This interface supports slave mode operation only. The clocked serial interface requires allocation of 4 signals; SI, SO, SCK, and FRM.
The LCD controller can be disabled to allow connection of an external LCDC with integrated frame buffer RAM such as NEC Electronics’ µ PD16661. When the internal LCD controller is disabled, the SHCLK, LOCLK, VPLCD, and VPBIAS pins are redefined as follows: Table 1-5.
CHAPTER 1 INTRODUCTION 1.3.17 Wake-up events The V 4181 supports 4 power management modes: Fullspeed, Standby, Suspend, and Hibernate. Of these modes, Hibernate is the lowest power mode and results in the powering off of all system components including the 2.5 V logic in the V 4181.
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CHAPTER 1 INTRODUCTION (1) CPU The CPU has hardware resources to process an integer instruction. They are the 64-bit register file, 64-bit integer data path, and multiply-and-accumulate operation unit. (2) Coprocessor 0 (CP0) The CP0 incorporates a memory management unit (MMU) and exception handling function. MMU checks whether there is an access between different memory segments (user, supervisor, and kernel) by executing address translation.
CHAPTER 1 INTRODUCTION 1.4.1 CPU registers The V 4110 core has thirty-two 64-bit general-purpose registers (GPRs). In addition, the processor provides the following special registers: • 64-bit Program Counter (PC) • 64-bit HI register, containing the integer multiply and divide upper doubleword result •...
CHAPTER 1 INTRODUCTION 1.4.2 CPU instruction set overview There are two types of CPU instructions: 32-bit length instructions (MIPS III) and 16-bit length instructions (MIPS16). Use of the MIPS16 instructions is enabled or disabled by setting MIPS16EN pin during a reset. For details about instruction formats and their fields in each instruction set and operation of each instruction, refer to V 4100 Series Architecture User’s Manual.
CHAPTER 1 INTRODUCTION (2) MIPS16 instructions All the CPU instructions except for JAL and JALX are 16-bit length when executing MIPS16 instructions, and they are classified into thirteen instruction formats as shown in Figure 1-5. Figure 1-5. CPU Instruction Formats (16-Bit Length Instruction) I-type immediate RI-type...
CHAPTER 1 INTRODUCTION The instruction set can be further divided into the following four groupings: (a) Load and store instructions move data between memory and general-purpose registers. They include RRI, RI, I8, and RI64 types. (b) Computational instructions perform arithmetic, logical, shift, and multiply and divide operations on values in registers.
CHAPTER 1 INTRODUCTION The CPU core uses the following byte boundaries for halfword, word, and doubleword accesses: • Halfword: An even byte boundary (0, 2, 4...) • Word: A byte boundary divisible by four (0, 4, 8...) • Doubleword: A byte boundary divisible by eight (0, 8, 16...) The following special instructions are used to load and store data that are not aligned on 4-byte (word) or 8-byte (doubleword) boundaries: •...
CHAPTER 1 INTRODUCTION 1.4.4 CP0 registers The CP0 has thirty-two registers, each of which has its own register number. Table 1-6 shows simple descriptions of each register. For the detailed descriptions of the registers, refer to CHAPTER 3 CP0 REGISTERS. Table 1-6.
CHAPTER 1 INTRODUCTION 1.4.5 Floating-point unit (FPU) The V 4181 does not support the floating-point unit (FPU). Coprocessor Unusable exception will occur if any FPU instructions are executed. If necessary, FPU instructions should be emulated by software in an exception handler. 1.4.6 Memory management unit The V 4181 has a 32-bit physical addressing range of 4 GB.
CHAPTER 1 INTRODUCTION 1.4.9 Power modes The V 4181 supports four power modes: Fullspeed mode, Standby mode, Suspend mode, and Hibernate mode. A detailed description of these power modes is also given in CHAPTER 10 POWER MANAGEMENT UNIT (PMU). (1) Fullspeed mode This is the normal operation mode.
CHAPTER 1 INTRODUCTION 1.4.10 Code compatibility The V 4110 core is designed in consideration of the program compatibility to other V -Series processors. However since it has some differences from other processors on their architecture, it cannot necessarily execute all programs that can be executed in other V -Series processors, and also other V -Series processors cannot...
CHAPTER 1 INTRODUCTION 1.5 Clock Interface The V 4181 has the following eight clocks. • CLKX1, CLKX2 (input) These are oscillation inputs of 18.432 MHz, and used to generate operation clocks for the CPU core, serial interface, and other peripheral units. •...
CHAPTER 1 INTRODUCTION Figure 1-9. Incorrect Connection Circuits of Resonator (a) Connection circuit wiring is too long. (b) There is another signal line crossing. Note 1 Note 2 Note 3 Note 1 Note 2 Note 3 (c) A high fluctuating current flows near a signal line. (d) A current flows over the ground line of the oscillator (The potentials of points A, B, and C change).
CHAPTER 2 PIN FUNCTIONS 2.2 Pin Function Description Remark # indicates active low. 2.2.1 System bus interface signals (1/2) Signal name Description of function Note ADD(21:0) Output Address bus. Used to specify address for the DRAM, ROM, flash memory, or system bus (ISA). DATA(15:0) Data bus.
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CHAPTER 2 PIN FUNCTIONS (2/2) Signal name Description of function Note SYSDIR Output Data bus isolation buffer direction control. This signal is valid only when ROM, ISA, or CompactFlash accesses are enabled. This becomes low level during ROM, ISA, or CompactFlash read cycle, or becomes high level during ROM, ISA, or CompactFlash write cycle.
CHAPTER 2 PIN FUNCTIONS 2.2.2 LCD interface signals Signal name Description of function SHCLK/LCDCS# Output LCD shift clock output or chip select for external LCD controller. LOCLK/MEMCS16# LCD load clock output or bus sizing request input for system bus memory access. When using as MEMCS16#, the external agent must activate this signal at the system bus memory access in 16-bit width.
CHAPTER 2 PIN FUNCTIONS 2.2.3 Initialization interface signals Signal name Description of function POWER Input 4181 activation signal. RSTSW# Input 4181 reset signal. RTCRST# Input Reset signal for internal Real-time clock and internal logic. When power is first supplied to the system, the external agent must activate this signal. POWERON Output This signal indicates that the V...
CHAPTER 2 PIN FUNCTIONS 2.2.6 Touch panel interface and audio interface signals Signal name Description of function TPX(1:0) Touch panel X coordinate data. They use the voltage applied to the X coordinate and the voltage input to the Y coordinate to detect which coordinates on the touch panel are being pressed.
CHAPTER 2 PIN FUNCTIONS 2.2.9 Serial interface channel 1 signals Signal name Description of function RxD1/GPIO25 Serial channel 1 receive data input or general-purpose I/O. TxD1/GPIO26/CLKSEL0 The function of this pin differs depending on the operating status. <During RTC reset (input)> Note This signal is used to set CPU core operation clock frequency <During normal operation (input/output)>...
CHAPTER 2 PIN FUNCTIONS 2.2.10 IrDA interface signals Signal name Description of function IRDIN/RxD2 Input IrDA receive data input or serial channel 2 receive data input. Connect this pin to GND (digital) via resistor when an IrDA receive component is connected.
CHAPTER 2 PIN FUNCTIONS 2.2.12 Dedicated V /GND signals Signal name Power Description of function supply VDD_PLL 2.5 V Power supply dedicated for the PLL analog block. GND_PLL 2.5 V Ground dedicated for the PLL analog block. VDD_TP 3.3 V Power supply dedicated for the touch panel interface.
CHAPTER 2 PIN FUNCTIONS 2.3 Pin Status in Specific Status (1/3) Signal Name During RTC After RTC Reset After Reset by During Suspend During Reset Deadman’s Mode Hibernate Mode Switch or or Shutdown by RSTSW HALTimer ADD(21:0) Hi-Z Note 1 DATA(15:0) Hi-Z Hi-Z...
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CHAPTER 2 PIN FUNCTIONS (2/3) Signal Name During RTC After RTC Reset After Reset by During Suspend During Reset Deadman’s Mode Hibernate Mode Switch or or Shutdown by RSTSW HALTimer − − POWERON MPOWER − − − − − BATTINH/BATTINT# −...
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CHAPTER 2 PIN FUNCTIONS (3/3) Signal Name During RTC After RTC Reset After Reset by During Suspend During Reset Deadman’s Mode Hibernate Mode Switch or or Shutdown by RSTSW HALTimer − RxD1/GPIO25 Hi-Z Hi-Z Note 1 Note 1/Note 2 TxD1/GPIO26/CLKSEL0 Note 3 Hi-Z Hi-Z...
CHAPTER 2 PIN FUNCTIONS 2.4 Recommended Connection of Unused Pins and I/O Circuit Types (1/3) Pin Name Recommended Connection When Not Used I/O Circuit Type − ADD(21:0) − DATA(15:0) − MEMRD# − MEMWR# − SDCS(1:0)#/RAS(1:0)# − UDQM/UCAS# − LDQM/LCAS# CAS# Leave open SDRAS# Leave open...
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CHAPTER 2 PIN FUNCTIONS (2/3) Pin Name Recommended Connection When Not Used I/O Circuit Type ADIN(2:0) Connect to GND_AD AUDIOIN Connect to GND_AD AUDIOOUT Leave open CF_WE#/SCANOUT7 Leave open CF_OE#/SCANOUT6 Leave open CF_IOW#/SCANOUT5 Leave open CF_IOR#/SCANOUT4 Leave open CF_STSCHG#/SCANOUT3 Connect to VDD_IO via resistor CF_CE(2:1)#/SCANOUT(2:1) Leave open CF_BUSY#/SCANOUT0...
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CHAPTER 2 PIN FUNCTIONS (3/3) Pin Name Recommended Connection When Not Used I/O Circuit Type GPIO3/PCS0# Connect to VDD_IO or GND_IO via resistor GPIO2/SCK Connect to VDD_IO or GND_IO via resistor GPIO1/SO Connect to VDD_IO or GND_IO via resistor GPIO0/SI Connect to VDD_IO or GND_IO via resistor LEDOUT Leave open...
CHAPTER 2 PIN FUNCTIONS 2.5 Pin I/O Circuits Type A Type C Data Data P-ch P-ch IN/OUT IN/OUT Output Output N-ch N-ch disable disable P-ch − N-ch Input enable Type B Data P-ch Input N-ch enable IN/OUT Output N-ch disable Type D P-ch P-ch...
CHAPTER 3 CP0 REGISTERS 3.1 Coprocessor 0 (CP0) The Coprocessor 0 (CP0), which is also called as System Control Coprocessor, is implemented as an integral part of the CPU, and supports memory management, address translation, exception handling, and operation mode control.
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CHAPTER 3 CP0 REGISTERS Table 3-1. CP0 Registers Number Register Usage Description Index Memory management Programmable pointer to TLB array Random Memory management Pseudo-random pointer to TLB array (read only) EntryLo0 Memory management Lower half of TLB entry for even VPN EntryLo1 Memory management Lower half of TLB entry for odd VPN...
CHAPTER 3 CP0 REGISTERS 3.2 Details of CP0 Registers 3.2.1 Index register (0) The Index register is a 32-bit, read/write register containing five low-order bits to index an entry in the TLB. The most-significant bit of the register shows the success or failure of a TLB probe (TLBP) instruction. The Index register also specifies the TLB entry affected by TLB read (TLBR) or TLB write index (TLBWI) instructions.
CHAPTER 3 CP0 REGISTERS 3.2.3 EntryLo0 (2) and EntryLo1 (3) registers The EntryLo register consists of two registers that have identical formats: EntryLo0, used for even virtual pages and EntryLo1, used for odd virtual pages. The EntryLo0 and EntryLo1 registers are both read-/write-accessible. They are used to access the built-in TLB.
CHAPTER 3 CP0 REGISTERS Table 3-2. Cache Algorithm C bit value Cache algorithm Cached Cached Uncached Cached Cached Cached Cached Cached 3.2.4 Context register (4) The Context register is a read/write register containing the pointer to an entry in the page table entry (PTE) array on the memory;...
CHAPTER 3 CP0 REGISTERS 3.2.5 PageMask register (5) The PageMask register is a read/write register used for reading from or writing to the TLB; it holds a comparison mask that sets the page size for each TLB entry, as shown in Table 3-3. Five page sizes can be selected between 1 KB and 256 KB.
CHAPTER 3 CP0 REGISTERS 3.2.6 Wired register (6) The Wired register is a read/write register that specifies the lower boundary of the random entry of the TLB as shown in Figure 3-6. Wired entries cannot be overwritten by a TLBWR instruction, but by a TLBWI instruction. Random entries can be overwritten by both instructions.
CHAPTER 3 CP0 REGISTERS 3.2.7 BadVAddr register (8) The Bad Virtual Address (BadVAddr) register is a read-only register that saves the most recent virtual address that failed to have a valid translation, or that had an addressing error. Caution This register saves no information after a bus error exception, because it is not an address error exception.
CHAPTER 3 CP0 REGISTERS 3.2.9 EntryHi register (10) The EntryHi register is write-accessible. It is used to access the built-in TLB. The EntryHi register holds the high- order bits of a TLB entry for TLB read and write operations. If a TLB Refill, TLB Invalid, or TLB Modified exception occurs, the EntryHi register holds the high-order bit of the TLB entry.
CHAPTER 3 CP0 REGISTERS 3.2.10 Compare register (11) The Compare register causes a timer interrupt; it maintains a stable value that does not change on its own. When the value of the Count register (see 3.2.8 Count register (9)) equals the value of the Compare register, the IP7 bit in the Cause register is set.
CHAPTER 3 CP0 REGISTERS Figure 3-12. Status Register (2/2) Enables 64-bit addressing in Kernel mode (0 → 32-bit, 1 → 64-bit). 64-bit operations are always valid in Kernel mode. Enables 64-bit addressing and operation in Supervisor mode (0 → 32-bit, 1 → 64-bit). Enables 64-bit addressing and operation in User mode (0 →...
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CHAPTER 3 CP0 REGISTERS (1) Interrupt enable Interrupts are enabled when all of the following conditions are true: • IE bit is set to 1. • EXL bit is cleared to 0. • ERL bit is cleared to 0. • The appropriate bit of the IM field is set to 1. (2) Operating modes The following Status register bit settings are required for User, Kernel, and Supervisor modes.
CHAPTER 3 CP0 REGISTERS 3.2.12 Cause register (13) The 32-bit read/write Cause register holds the cause of the most recent exception. A 5-bit exception code indicates one of the causes (see Table 3-4). Other bits hold the detailed information of the specific exception. All bits in the Cause register, with the exception of the IP1 and IP0 bits, are read-only;...
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CHAPTER 3 CP0 REGISTERS Table 3-4. Cause Register Exception Code Field Exception code Mnemonic Description Interrupt exception TLB Modified exception TLBL TLB Refill exception (load or fetch) TLBS TLB Refill exception (store) AdEL Address Error exception (load or fetch) AdES Address Error exception (store) Bus Error exception (instruction fetch) Bus Error exception (data load or store)
CHAPTER 3 CP0 REGISTERS 3.2.13 Exception Program Counter (EPC) register (14) The Exception Program Counter (EPC) is a read/write register that contains the address at which processing resumes after an exception has been serviced. The contents of this register change depending on whether execution of MIPS16 instructions is enabled or disabled.
CHAPTER 3 CP0 REGISTERS Figure 3-16. EPC Register (When MIPS16 ISA Is Enabled) (a) 32-bit mode EPC: Bits 31 to 1 of restart address (virtual) after exception processing. ISA mode at which an exception occurs (1 → When MIPS16 SIA instruction is executed, 0 → EIM: When MIPS III ISA instruction is executed).
CHAPTER 3 CP0 REGISTERS 3.2.15 Config register (16) The Config register specifies various configuration options selected on the V 4181. Some configuration options, as defined by the EC and BE fields, are set by the hardware during Cold Reset and are included in the Config register as read-only status bits for the software to access.
CHAPTER 3 CP0 REGISTERS Figure 3-18. Config Register (2/2) kseg0 cache coherency algorithm 2 → Uncached Others → Cached 1 is returned when read. 0 is returned when read. 3.2.16 Load Linked Address (LLAddr) register (17) The read/write Load Linked Address (LLAddr) register is not used with the V 4181 processor except for diagnostic purpose, and serves no function during normal operation.
CHAPTER 3 CP0 REGISTERS 3.2.17 WatchLo (18) and WatchHi (19) registers The V 4181 processor provides a debugging feature to detect references to a selected physical address; load and store instructions to the location specified by the WatchLo and WatchHi registers cause a Watch exception. The contents of these registers are undefined after a reset so that they must be initialized by software.
CHAPTER 3 CP0 REGISTERS 3.2.18 XContext register (20) The read/write XContext register contains a pointer to an entry in the page table entry (PTE) array, an operating system data structure that stores virtual-to-physical address translations. If a TLB miss occurs, the operating system loads the untranslated data from the PTE into the TLB to handle the software error.
CHAPTER 3 CP0 REGISTERS 3.2.19 Parity Error register (26) The Parity Error (PErr) register is a readable/writable register. This register is defined to maintain software- compatibility with the V 4100, and is not used in hardware because the V 4181 has no parity. Figure 3-23.
CHAPTER 3 CP0 REGISTERS 3.2.21 TagLo (28) and TagHi (29) registers The TagLo and TagHi registers are 32-bit read/write registers that hold the primary cache tag during cache initialization, cache diagnostics, or cache error processing. The Tag registers are written by the CACHE and MTC0 instructions.
CHAPTER 3 CP0 REGISTERS 3.2.22 ErrorEPC register (30) The Error Exception Program Counter (ErrorEPC) register is similar to the EPC register. It is used to store the Program Counter value at which the Cold Reset, Soft Reset, or NMI exception has been serviced. The read/write ErrorEPC register contains the virtual address at which instruction processing can resume after servicing an error.
CHAPTER 4 MEMORY MANAGEMENT SYSTEM 4.1 Overview The V 4181 provides a memory management unit (MMU) which uses a translation lookaside buffer (TLB) to translate virtual addresses into physical addresses. Virtual addresses are translated into physical addresses using an on-chip TLB. The on-chip TLB is a full- associative memory that holds 32 entries, which provide mapping to 32 odd/even page pairs for one entry.
CHAPTER 4 MEMORY MANAGEMENT SYSTEM 4.2 Physical Address Space Using a 32-bit address, the processor physical address space encompasses 4 GB. The V 4181 uses this 4 GB physical address space as shown in Figure 4-1. Figure 4-1. V 4181 Physical Address Space 0xFFFF FFFF (Mirror image of 0x0000 0000 to 0x1FFF FFFF area) 0x2000 0000...
CHAPTER 4 MEMORY MANAGEMENT SYSTEM Table 4-1. V 4181 Physical Address Space Physical address Space Capacity (bytes) 0xFFFF FFFF to 0x2000 0000 Mirror image of 0x1FFF FFFF to 0x0000 0000 3.5 G 0x1FFF FFFF to 0x1800 0000 ROM space 128 M 0x17FF FFFF to 0x1400 0000 External system bus I/O space (ISA I/O) 64 M...
CHAPTER 4 MEMORY MANAGEMENT SYSTEM 4.2.3 Internal I/O space The V 4181 has three internal I/O spaces. Each of these spaces is described below. Table 4-3. Internal I/O Space 1 Physical address Internal I/O 0x0C00 001F to 0x0C00 0010 SIU1 0x0C00 000F to 0x0C00 0000 SIU2 Table 4-4.
CHAPTER 4 MEMORY MANAGEMENT SYSTEM Table 4-5. MBA Bus I/O Space Physical address Internal I/O 0x0A00 06FF to 0x0A00 0600 DCU-2 0x0A00 05FF to 0x0A00 0500 Reserved for future use 0x0A00 04FF to 0x0A00 0400 LCD controller 0x0A00 03FF to 0x0A00 0300 Memory controller 0x0A00 02FF to 0x0A00 0220 Reserved for future use...
CHAPTER 5 INITIALIZATION INTERFACE This chapter describes the reset signal descriptions and types, signal- and timing-related dependence, and the initialization sequence during each mode that can be selected by the user. A detailed description of the operation during and after a reset and its relationships to the power modes are also provided in CHAPTER 10 POWER MANAGEMENT UNIT (PMU).
CHAPTER 5 INITIALIZATION INTERFACE 5.1.1 RTC reset During power-on, set the RTCRST# pin as active. After waiting about 600 ms for the 32.768 kHz oscillator to begin oscillating when the power supply is stable at 3.0 V or above, setting the RTCRST# pin as inactive causes the RTC unit to begin counting.
CHAPTER 5 INITIALIZATION INTERFACE 5.1.2 RSTSW reset After the RSTSW# pin becomes active and then becomes inactive 100 µ s later, the V 4181 starts PLL oscillation and starts all clocks (a period of about 16 ms following the start of PLL oscillation is required for stabilization of PLL oscillation).
CHAPTER 5 INITIALIZATION INTERFACE 5.1.3 Deadman’s Switch reset After the Deadman’s Switch unit is enabled, if the Deadman’s Switch is not cleared within the specified time period, the V 4181 immediately enters to reset status. Setting and clearing of the Deadman’s Switch is performed by software.
CHAPTER 5 INITIALIZATION INTERFACE 5.1.4 Software shutdown When the software executes the HIBERNATE instruction, the V 4181 sets the MPOWER pin as inactive, then enters reset status. Recovery from reset status occurs when the POWER pin or DCD# signal is asserted or when an unmasked wake-up interrupt request is occurred.
CHAPTER 5 INITIALIZATION INTERFACE 5.1.5 HALTimer shutdown After an RTC reset or RSTSW reset is canceled, if the HALTimer is not canceled (the HALTIMERRST bit of the PMUCNTREG register is not set) by software within about four seconds, the V 4181 enters reset status.
CHAPTER 5 INITIALIZATION INTERFACE 5.2 Power-on Sequence The factors that cause the V 4181 to switch from Hibernate mode or shutdown mode to Fullspeed mode are called activation factors. There are five activation factors: assertion of the POWER pin, the DCD1# pin or the GPIO(15:0) pins, or activation of the ElapsedTime or CompactFlash interrupt request.
CHAPTER 5 INITIALIZATION INTERFACE 5.3 Reset of CPU Core This section describes the reset sequence of the V 4110 CPU core. 5.3.1 Cold Reset In the V 4181, a Cold Reset sequence is executed in the CPU core in the following cases: •...
CHAPTER 5 INITIALIZATION INTERFACE 5.3.2 Soft Reset Caution Soft Reset is not supported in the current V 4181. A Soft Reset initializes the CPU core without affecting the output clocks; in other words, a Soft Reset is a logical reset. In a Soft Reset, the CPU core retains as much state information as possible; all state information except for the following is retained: •...
CHAPTER 5 INITIALIZATION INTERFACE 5.4 Notes on Initialization This section explains the case in which manipulation by software is necessary after the V 4181 has been reset. When a Cold Reset sequence is executed, the reset exception vector is accessed. Perform manipulation described here by using the software (handler) for reset exceptions located at the reset exception vector.
CHAPTER 5 INITIALIZATION INTERFACE 5.4.3 Returning from power mode For initialization after the V 4181 has returned from the Hibernate mode or Suspend mode, refer to 10.6 DRAM Interface Control. User’s Manual U14272EJ3V0UM...
CHAPTER 6 BUS CONTROL 6.1 MBA Host Bridge The MBA (Modular Bus Architecture) Host Bridge is an interface between the CPU core and the MBA bus and operates as an external agent to the CPU core. It handles all requests from the CPU core if it is provided proper resources.
CHAPTER 6 BUS CONTROL 6.1.1 MBA Host Bridge ROM and register address space Physical address Type Device 0x1FFF FFFF to 0x1800 0000 Memory (range) 0x0A00 0014 to 0x0A00 0000 I/O (range) Bus control registers 0x0A00 0080 Interrupt register 0x0A00 008C Interrupt register 0x0A00 0098 Interrupt register...
CHAPTER 6 BUS CONTROL (4) ISA Bridge Physical address Type Device 0x17FF FFFF to 0x1400 0000 I/O (64M, range) External ISA bus (I/O) 0x13FF FFFF to 0x1000 0000 Memory (64M, range) External ISA bus (Memory) 0x0BFF FFFF to 0x0B00 0000 I/O (16M, range) ISA internal I/O 1 0x0CFF FFFF to 0x0C00 0000...
CHAPTER 6 BUS CONTROL 6.2.1 BCUCNTREG1 (0x0A00 0000) Name ROMs1 ROMs0 Reserved Reserved Reserved Reserved Reserved Reserved At reset Name Reserved Reserved Reserved ROMWEN0 Reserved Rtype1 Rtype0 RSTOUT At reset Name Function 15, 14 ROMs(1:0) Defines ROM size to be used (for all banks) 00 : Reserved 01 : 32 Mbit 10 : 64 Mbit...
CHAPTER 6 BUS CONTROL 6.2.2 CMUCLKMSK (0x0A00 0004) Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved At reset Name Reserved MSKCSU MSKAIU MSKPIU MSKADU MSKSIU MSKADU Reserved PCLK PCLK PCLK PCLK At reset Name Function 15 to 7 Reserved 0 is returned when read MSKCSUPCLK Supply/Mask Clocked Serial Interface (CSI) peripheral clock (PCLK)
CHAPTER 6 BUS CONTROL 6.2.3 BCUSPEEDREG (0x0A00 000C) Name Reserved WPROM2 WPROM1 WPROM0 Reserved Reserved Reserved Reserved At reset Name Reserved Reserved Reserved Reserved WROMA3 WROMA2 WROMA1 WROMA0 At reset Name Function Reserved 0 is returned when read 14 to 12 WPROM(2:0) Page ROM access speed 000 : 1.5 TClock...
CHAPTER 6 BUS CONTROL 6.2.4 BCURFCNTREG (0x0A00 0010) Name Reserved Reserved BRF13 BRF12 BRF11 BRF10 BRF9 BRF8 At reset Name BRF7 BRF6 BRF5 BRF4 BRF3 BRF2 BRF1 BRF0 At reset Name Function 15, 14 Reserved 0 is returned when read 13 to 0 BRF(13:0) These bits select the DRAM refresh rate that is based on the TClock.
CHAPTER 6 BUS CONTROL 6.2.5 REVIDREG (0x0A00 0014) Name RID3 RID2 RID1 RID0 MJREV3 MJREV2 MJREV1 MJREV0 Name Reserved Reserved Reserved Reserved MNREV3 MNREV2 MNREV1 MNREV0 Name Function 15 to 12 RID(3:0) Processor revision ID (Read Only) 11 to 8 MJREV(3:0) Major revision ID number (Read only) 7 to 4...
CHAPTER 6 BUS CONTROL 6.2.6 CLKSPEEDREG (0x0A00 0018) Name DIV2 DIV3 DIV4 Reserved Reserved Reserved Reserved Reserved Name Reserved Reserved Reserved CLKSP4 CLKSP3 CLKSP2 CLKSP1 CLKSP0 Name Function 15 to 13 DIV(2:4) Value used to calculate the TClock, MBA clock, and SDCLK operating frequency 12 to 5 Reserved 0 is returned when read...
CHAPTER 6 BUS CONTROL 6.3 ROM Interface The V 4181 supports three ROM modes, ordinary ROM, PageROM, and flash memory. The mode setting is made via the BCUCNTREG1 register’s Rtype(1:0) bits and ROMWEN0 bit. Access speed setting in ordinary ROM or PageROM mode is made via the BCUSPEEDREG register.
CHAPTER 6 BUS CONTROL 6.3.2 Connection to external ROM (x 16) devices The ADD(21:0) pins are connected to the address line ADD(21:0) inside the V 4181 during DRAM accesses. However, during ROM or flash memory accesses, they are connected to the address line ADD(22:1) inside the 4181.
CHAPTER 6 BUS CONTROL 6.3.3 Example of ROM connection (1) 32 Mbit ordinary ROM ADD(20:0) A(20:0) A(20:0) A(20:0) A(20:0) ROMCS0# ROMCS1# ROMCS2# ROMCS3# Bank0 Bank1 Bank2 Bank3 D(15:0) D(15:0) D(15:0) D(15:0) DATA(15:0) (2) 64 Mbit ordinary ROM ADD(21:0) A(21:0) A(21:0) A(21:0) A(21:0) ROMCS0#...
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CHAPTER 6 BUS CONTROL (3) 32 Mbit PageROM Remark The maximum burst number when using a PageROM is 8 halfwords (i.e. 128 bits; 1 word = 32 bits). ADD(20:3) ADD(2:0) A(19:2) A(19:2) A(19:2) A(19:2) A(1:−1) A(1:−1) A(1:−1) A(1:−1) Page Page Page Page Bank0...
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CHAPTER 6 BUS CONTROL (4) 64 Mbit PageROM Remark The maximum burst number when using a PageROM is 8 halfwords (i.e. 128 bits; 1 word = 32 bits). ADD(21:3) ADD(2:0) A(20:2) A(20:2) A(20:2) A(20:2) A(1:−1) A(1:−1) A(1:−1) A(1:−1) Page Page Page Page Bank0...
CHAPTER 6 BUS CONTROL 6.3.4 External ROM cycles The following timing diagrams illustrate the external ROM cycles depending on the settings in the bus control register and bus speed control register. (1) Ordinary ROM read cycle Figure 6-3. Ordinary ROM Read Cycle (WROMA(3:0) = 0101) TClock (internal) ADD(21:0)
CHAPTER 6 BUS CONTROL 6.4 DRAM Interface The V 4181 supports 16 Mbit or 64 Mbit DRAM (EDO DRAM or SDRAM). The DRAM size, type, and access speed is set via the memory controller’s registers. 6.4.1 EDO DRAM configuration Figure 6-7. External EDO DRAM Configuration ADD(12:0) A(12:0) UCAS#...
CHAPTER 6 BUS CONTROL 6.4.2 Mixed memory mode (EDO DRAM only) The MEMCFG_REG register provides two bits each for Bank 0 and Bank 1 to set types of DRAMs to be used. This allows the two banks to be configured with different types of DRAMs, for example, Bank 0 can be mapped on 64 Mbit devices and Bank 1 on 16 Mbit devices, to optimize the cost of the total memory required.
CHAPTER 6 BUS CONTROL 6.4.4 SDRAM configuration Figure 6-8. SDRAM Configuration ADD(13:0) A(13:0) SDRAS# RAS# CAS# CAS# UDQM UDQM LDQM LDQM SDRAM Bank0 MEMWR# SDCS0# DATA(15:0) D(15:0) SDCLK CLKEN 4181 A(13:0) RAS# CAS# UDQM LDQM SDRAM Bank1 SDCS1# D(15:0) Figure 6-8 illustrates an example when connecting devices of 4 Mbits x 16. Remark The SDRAMs supported by the V 4181 are as follows.
CHAPTER 6 BUS CONTROL 6.5 Memory Controller Register Set Table 6-3. Memory Controller Registers Physical address Register symbol Function 0x0A00 0300 EDOMCYTREG EDO DRAM timing register 0x0A00 0304 MEMCFG_REG Memory configuration register 0x0A00 0308 MODE_REG SDRAM mode register 0x0A00 030C SDTIMINGREG SDRAM timing register Caution Since these registers are powered by 2.5 V power supply, the contents of these registers are...
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CHAPTER 6 BUS CONTROL (2/2) Name Function 5, 4 Tcas(1:0) CAS pulse width 00 : 1/2 TClock 01 : 1 TClock 10 : 2 TClock 11 : Reserved 3, 2 Trp(1:0) RAS precharge time 00 : 1 TClock 01 : 2 TClock 10 : 3 TClock 11 : 4 TClock 1, 0...
CHAPTER 6 BUS CONTROL 6.5.2 MEMCFG_REG (0x0A00 0304) (1/2) Name Init Reserved Reserved Reserved B1Config1 B1Config0 Reserved Bstreftype At reset Name BstRefr EDOAsym Reserved Reserved Reserved B0Config1 B0Config0 EDO/ SDRAM At reset Name Function Init This bit is for SDRAM only. When software writes 1 to this bit, the memory controller issues a SDRAM mode set command.
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CHAPTER 6 BUS CONTROL (2/2) Name Function 5 to 3 Reserved 0 is returned when read 2, 1 B0Config(1:0) Bank 0 Capacity 00 : Bank 0 is not installed 01 : 16 Mbit 10 : 64 Mbit 11 : Reserved EDO/SDRAM DRAM Type 0 : EDO DRAM...
CHAPTER 6 BUS CONTROL 6.5.3 MODE_REG (0x0A00 0308) Name Reserved Reserved Reserved Reserved BR-SW TE-Ven1 At reset Name TE-Ven2 LTMode2 LTMode1 LTMode0 At reset Name Function 15 to 12 Reserved 0 is returned when read 11, 10 These bits should be always written to 00. BR-SW Burst read - single write This bit should be always written to 0.
CHAPTER 6 BUS CONTROL 6.5.4 SDTIMINGREG (0x0A00 030C) Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved At reset Name TRAS1 TRAS0 TRC1 TRC0 TRP1 TRP0 TRCD1 TRCD0 At reset Name Function 15 to 10 Reserved 0 is returned when read Note Write 0 when write.
CHAPTER 6 BUS CONTROL 6.6 ISA Bridge The V 4181 has an external bus used for ROM, flash memory, DRAM, and I/O. This bus’s operation emulates an ISA bus at accesses to external memory and I/O spaces. The V 4181 also uses an ISA bus internally for the slow, embedded peripherals.
CHAPTER 6 BUS CONTROL 6.7.1 ISABRGCTL (0x0B00 02C0) Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved RTCRST Other resets Name Reserved Reserved Reserved Reserved Reserved Reserved PCLKDIV1 PCLKDIV0 RTCRST Other resets Name Function 15 to 2 Reserved 0 is returned when read 1, 0 PCLKDIV(1:0) PCLK (peripheral clock) divisor rate selection.
CHAPTER 6 BUS CONTROL 6.7.2 ISABRGSTS (0x0B00 02C2) Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved RTCRST Other resets Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved IDLE RTCRST Other resets Name Function 15 to 1 Reserved 0 is returned when read IDLE ISA Bridge status 0 : ISA Bridge is busy...
CHAPTER 6 BUS CONTROL 6.7.3 XISACTL (0x0B00 02C4) (1/2) EXTRESULT Name Reserved Reserved Reserved Reserved Reserved INTRESULT EXBUFFEN RTCRST Other resets Name MEMWS1 MEMWS0 IOWS1 IOWS0 Reserved Reserved SCLKDIV1 SCLKDIV0 RTCRST Other resets Name Function 15 to 11 Reserved 0 is returned when read EXTRESULT External ISA result cycle enable 0 : Disabled.
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CHAPTER 6 BUS CONTROL (2/2) Name Function 3, 2 Reserved 0 is returned when read 1, 0 SCLKDIV(1:0) SYSCLK (external ISA bus clock) divisor rate selection 00 : PCLK / 2 01 : PCLK / 3 10 : PCLK / 6 11 : PCLK / 8 This register is used to set the external ISA configurations.
CHAPTER 7 DMA CONTROL UNIT (DCU) 7.1 General The DMA Control Unit (DCU) controls four channels of DMA transfer. Two of them are allocated for the AIU (microphone and speaker), though the remaining two are reserved for future use. The Microphone channel performs the I/O-to-memory transfers from the A/D converter included in the AIU to memory.
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CHAPTER 7 DMA CONTROL UNIT (DCU) Priority of each DMA channel is fixed. The channel priority is as follows. 1. AIU Microphone channel 2. AIU Speaker channel DCU runs at the MBA bus clock (TClock) frequency. Remark The DCU contains a 32-bit temporary storage register for each DMA channel. For memory-to-I/O transfers, the DCU performs a 32-bit memory read from DRAM and stores the read data into the temporary storage register.
CHAPTER 7 DMA CONTROL UNIT (DCU) 7.2.1 Microphone destination 1 address registers (1) MICDEST1REG1 (0x0A00 0020) Name MD1A15 MD1A14 MD1A13 MD1A12 MD1A11 MD1A10 MD1A9 MD1A8 At reset Name MD1A7 MD1A6 MD1A5 MD1A4 MD1A3 MD1A2 MD1A1 MD1A0 At reset Name Function 15 to 0 MD1A(15:0) Lower 16 bits (A(15:0)) of DMA destination 1 address for Microphone...
CHAPTER 7 DMA CONTROL UNIT (DCU) 7.2.2 Microphone destination 2 address registers (1) MICDEST2REG1 (0x0A00 0024) Name MD2A15 MD2A14 MD2A13 MD2A12 MD2A11 MD2A10 MD2A9 MD2A8 At reset Name MD2A7 MD2A6 MD2A5 MD2A4 MD2A3 MD2A2 MD2A1 MD2A0 At reset Name Function 15 to 0 MD2A(15:0) Lower 16 bits (A(15:0)) of DMA destination 2 address for Microphone...
CHAPTER 7 DMA CONTROL UNIT (DCU) 7.2.3 Speaker source 1 address registers (1) SPKRSRC1REG1 (0x0A00 0028) Name SS1A15 SS1A14 SS1A13 SS1A12 SS1A11 SS1A10 SS1A9 SS1A8 At reset Name SS1A7 SS1A6 SS1A5 SS1A4 SS1A3 SS1A2 SS1A1 SS1A0 At reset Name Function 15 to 0 SS1A(15:0) Lower 16 bits (A(15:0)) of DMA source 1 address for Speaker...
CHAPTER 7 DMA CONTROL UNIT (DCU) 7.2.4 Speaker source 2 address registers (1) SPKRSRC2REG1 (0x0A00 002C) Name SS2A15 SS2A14 SS2A13 SS2A12 SS2A11 SS2A10 SS2A9 SS2A8 At reset Name SS2A7 SS2A6 SS2A5 SS2A4 SS2A3 SS2A2 SS2A1 SS2A0 At reset Name Function 15 to 0 SS2A(15:0) Lower 16 bits (A(15:0)) of DMA source 2 address for Speaker...
CHAPTER 7 DMA CONTROL UNIT (DCU) 7.2.5 DMARSTREG (0x0A00 0040) Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved At reset Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved DMARST At reset Name Function 15 to 1 Reserved 0 is returned after a read. DMARST Resets DMA functions 0 : Resets DMA channels...
CHAPTER 7 DMA CONTROL UNIT (DCU) 7.2.7 MICRCLENREG (0x0A00 0658) Name MICRL15 MICRL14 MICRL13 MICRL12 MICRL11 MICRL10 MICRL9 MICRL8 At reset Name MICRL7 MICRL6 MICRL5 MICRL4 MICRL3 MICRL2 MICRL1 MICRL0 At reset Name Function 15 to 0 MICRL(15:0) DMA Record Length for Microphone. MICRL0 bit must be written to zero. This register defines the number of 16-bit words to be transferred during DMA operation in the Microphone channel.
CHAPTER 7 DMA CONTROL UNIT (DCU) 7.2.9 MICDMACFGREG (0x0A00 065E) Name Reserved MicDsize1 MicDsize0 MicSrctype MicDestype Reserved Reserved MicLoad At reset Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved At reset Name Function Reserved 0 is returned after a read. 14, 13 MicDsize(1:0) Indicates Microphone channel data size...
CHAPTER 7 DMA CONTROL UNIT (DCU) 7.2.10 SPKDMACFGREG (0x0A00 0660) Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved At reset Name Reserved SpkDsize1 SpkDsize0 SpkSrctype SpkDestype Reserved Reserved SpkLoad At reset Name Function 15 to 7 Reserved 0 is returned after a read. 6, 5 SpkDsize(1:0) Indicates Speaker channel data size...
CHAPTER 7 DMA CONTROL UNIT (DCU) 7.2.11 DMAITRQREG (0x0A00 0662) Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved At reset Name Reserved Reserved SpkEOP MicEOP Reserved Reserved Reserved Reserved At reset Name Function 15 to 6 Reserved 0 is returned after a read. SpkEOP Speaker channel end of process (EOP) interrupt status 0 : None...
CHAPTER 7 DMA CONTROL UNIT (DCU) 7.2.13 DMAITMKREG (0x0A00 0666) Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved At reset Name Reserved Reserved SpkEOPMsk MicEOPMsk Reserved Reserved Reserved Reserved At reset Name Function 15 to 6 Reserved 0 is returned after a read. SpkEOPMsk Speaker channel end of process (EOP) interrupt mask 0 : Disable...
CHAPTER 8 CLOCKED SERIAL INTERFACE UNIT (CSI) 8.1 Overview The CSI manages communication via a synchronous serial bus. The CSI of the V 4181 has the following key characteristics: • Slave-only synchronous serial interface • Able to transmit and receive data simultaneously •...
CHAPTER 8 CLOCKED SERIAL INTERFACE UNIT (CSI) 8.2.2 SCK phase and CSI transfer timing The external master drives SCK and SI and samples data driven on SO. The CSI supports 4 basic operating modes of SCK depending on the settings of CKPOL and CKMD bits. These are illustrated in the following figure. Figure 8-1.
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CHAPTER 8 CLOCKED SERIAL INTERFACE UNIT (CSI) The four modes of SCK are described below. (1) When CKMD bit = 0 and CKPOL bit = 0 • Transmission The first transmit data bit is output before the first rising edge of SCK. The second transmit data and those that follow are output synchronized with the falling edge of SCK.
CHAPTER 8 CLOCKED SERIAL INTERFACE UNIT (CSI) 8.2.3 CSI transfer types (1) Burst mode Burst mode is supported for both transmit and receive transfers. Burst lengths for transmission and reception are independently programmable and can be set from 1 to 65535 bits. The transmit and receive shift registers are both 8-bit lengths.
CHAPTER 8 CLOCKED SERIAL INTERFACE UNIT (CSI) 8.2.4 Transmit and receive FIFOs The CSI contains two 8-deep 16-bit FIFOs. One is for transmission and the other for reception. The transmit and receive shift registers access the FIFOs by 8 bits at a time. The CPU core accesses the FIFOs in either 8-bit or 16-bit units.
CHAPTER 8 CLOCKED SERIAL INTERFACE UNIT (CSI) 8.3.1 CSIMODE (0x0B00 0900) (1/2) Name FRMEN TXEN TXBMD TXCLR Reserved RXEN RXBMD RXCLR RTCRST Other resets Name FRMMD CKPOL CKMD Reserved Reserved Reserved Reserved LSBMSB RTCRST Other resets Name Function FRMEN CSI FRM enable 0 : Disabled.
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CHAPTER 8 CLOCKED SERIAL INTERFACE UNIT (CSI) (2/2) Name Function FRMMD FRM mode 0 : FRM controls transfer directions (receive when FRM= 1, transmit when FRM= 1 : FRM enables transfers (transmit/receive enabled when FRM = 0) Note CSI clock polarity CKPOL 0 : SCK is active high (1st transition is low to high) 1 : SCK is active low (1st transition is high to low)
CHAPTER 8 CLOCKED SERIAL INTERFACE UNIT (CSI) 8.3.2 CSIRXDATA (0x0B00 0902) Name RXD15 RXD14 RXD13 RXD12 RXD11 RXD10 RXD9 RXD8 RTCRST Other resets Name RXD7 RXD6 RXD5 RXD4 RXD3 RXD2 RXD1 RXD0 RTCRST Other resets Name Function 15 to 0 RXD(15:0) CSI receive data.
CHAPTER 8 CLOCKED SERIAL INTERFACE UNIT (CSI) 8.3.4 CSILSTAT (0x0B00 0906) (1/2) Name TFIFOT1 TFIFOT0 Reserved Reserved Reserved TXFIFOF TXFIFOE TXBUSY RTCRST Other resets Name RFIFOT1 RFIFOT0 Reserved FRMDIR Reserved RXFIFOF RXFIFOE RXBUSY RTCRST Other resets Name Function 15, 14 TFIFOT(1:0) CSI transmit FIFO threshold.
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CHAPTER 8 CLOCKED SERIAL INTERFACE UNIT (CSI) (2/2) Name Function FRMDIR FRM input pin status 0 : Low level (transmit direction) 1 : High level (receive direction) Reserved 0 is returned after read RXFIFOF CSI receive FIFO full status. This bit is set to 1 when the receive FIFO reaches to the full level defined by RFIFOT bits.
CHAPTER 8 CLOCKED SERIAL INTERFACE UNIT (CSI) 8.3.5 CSIINTMSK (0x0B00 0908) Name Reserved Reserved Reserved Reserved MUNDRN MTXBEND MTXFIFOE MTXBUSY RTCRST Other resets Name Reserved Reserved Reserved Reserved MOVRRN MRXBEND MRXFIFOF MRXBUSY RTCRST Other resets Name Function 15 to 12 Reserved 0 is returned after read MUNDRN...
CHAPTER 8 CLOCKED SERIAL INTERFACE UNIT (CSI) 8.3.6 CSIINTSTAT (0x0B00 090A) (1/2) Name Reserved Reserved Reserved Reserved URNINT TXBEINT TXFEINT TXBSYINT RTCRST Other resets Name Reserved Reserved Reserved Reserved ORNINT RXBEINT RXFFINT RXBSYINT RTCRST Other resets Name Function 15 to 12 Reserved 0 is returned after read URNINT...
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CHAPTER 8 CLOCKED SERIAL INTERFACE UNIT (CSI) (2/2) Name Function RXBEINT Receive Burst End interrupt request status 0 : Not pending 1 : Pending This bit is cleared by writing 1. RXFFINT Receive FIFO Full interrupt request status 0 : Not pending 1 : Pending This bit is cleared by writing 1.
CHAPTER 8 CLOCKED SERIAL INTERFACE UNIT (CSI) 8.3.7 CSITXBLEN (0x0B00 090C) Name TXBLN15 TXBLN14 TXBLN13 TXBLN12 TXBLN11 TXBLN10 TXBLN9 TXBLN8 RTCRST Other resets Name TXBLN7 TXBLN6 TXBLN5 TXBLN4 TXBLN3 TXBLN2 TXBLN1 TXBLN0 RTCRST Other resets Name Function 15 to 0 TXBLN(15:0) Transmit burst length.
CHAPTER 8 CLOCKED SERIAL INTERFACE UNIT (CSI) 8.3.8 CSIRXBLEN (0x0B00 090E) Name RXBLN15 RXBLN14 RXBLN13 RXBLN12 RXBLN11 RXBLN10 RXBLN9 RXBLN8 RTCRST Other resets Name RXBLN7 RXBLN6 RXBLN5 RXBLN4 RXBLN3 RXBLN2 RXBLN1 RXBLN0 RTCRST Other resets Name Function 15 to 0 RXBLN(15:0) Receive burst length.
CHAPTER 9 INTERRUPT CONTROL UNIT (ICU) 9.1 Overview The ICU collects interrupt requests from the various on-chip peripheral units and transfers them with internal interrupt request signals (Int0, Int1, Int2, Int3, Int4, and NMI) to the CPU core. The signals used to notice interrupt requests to the CPU are as below. NMI: battint only.
CHAPTER 9 INTERRUPT CONTROL UNIT (ICU) 9.2.1 SYSINT1REG (0x0A00 0080) (1/2) Name Reserved Reserved DOZEPIU Reserved SOFTINTR Reserved SIUINTR GIUINTR INTR RTCRST Other resets Name KIUINTR AIUINTR PIUINTR Reserved ETIMER RTCL1 POWER BATINTR INTR INTR INTR RTCRST Other resets Name Function 15, 14 Reserved...
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CHAPTER 9 INTERRUPT CONTROL UNIT (ICU) (2/2) Name Function PIUINTR PIU interrupt request 0 : Not occurred 1 : Occurred Reserved 0 is returned when read ETIMERINTR ElapsedTime interrupt request 0 : Not occurred 1 : Occurred RTCL1INTR RTCLong1 interrupt request 0 : Not occurred 1 : Occurred POWERINTR...
CHAPTER 9 INTERRUPT CONTROL UNIT (ICU) 9.2.3 NMIREG (0x0A00 0098) Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved RTCRST Other resets Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved NMIORINT RTCRST Other resets Name Function 15 to 1 Reserved 0 is returned when read NMIORINT Battery low interrupt request routing...
CHAPTER 9 INTERRUPT CONTROL UNIT (ICU) 9.2.4 SOFTINTREG (0x0A00 009A) Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved RTCRST Other resets Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved SOFTINTR RTCRST Other resets Name Function 15 to 1 Reserved 0 is returned when read SOFTINTR Set/clear a software interrupt request.
CHAPTER 9 INTERRUPT CONTROL UNIT (ICU) 9.2.5 SYSINT2REG (0x0A00 0200) Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved RTCRST Other resets Name Reserved LCDINTR DMAINTR Reserved CSUINTR ECUINTR LEDINTR RTCL2INTR RTCRST Other resets Name Function 15 to 7 Reserved 0 is returned when read LCDINTR LCD interrupt request...
CHAPTER 9 INTERRUPT CONTROL UNIT (ICU) 9.2.6 MSYSINT2REG (0x0A00 0206) Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved RTCRST Other resets Name Reserved MLCDINTR MDMAINTR Reserved MCSUINTR MECUINTR MLEDINTR MRTCL2 INTR RTCRST Other resets Name Function 15 to 7 Reserved 0 is returned when read MLCDINTR...
CHAPTER 9 INTERRUPT CONTROL UNIT (ICU) 9.2.7 PIUINTREG (0x0B00 0082) Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved RTCRST Other resets Name Reserved PADCMD PADADP PADPAGE1 PADPAGE0 PADDLOST Reserved PENCHG INTR INTR INTR INTR INTR INTR RTCRST Other resets Name Function 15 to 7...
CHAPTER 9 INTERRUPT CONTROL UNIT (ICU) 9.2.8 AIUINTREG (0x0B00 0084) Name Reserved Reserved Reserved Reserved Reserved Reserved INTMIDLE INTMST RTCRST Other resets Name Reserved Reserved Reserved Reserved Reserved Reserved INTSIDLE Reserved RTCRST Other resets Name Function 15 to 10 Reserved 0 is returned when read INTMIDLE Audio input (microphone) idle interrupt request (received data is lost).
CHAPTER 9 INTERRUPT CONTROL UNIT (ICU) 9.2.9 KIUINTREG (0x0B00 0086) Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved RTCRST Other resets Name Reserved Reserved Reserved Reserved Reserved KDATLOST KDATRDY KDOWNINT RTCRST Other resets Name Function 15 to 3 Reserved 0 is returned when read KDATLOST Keyboard Data Lost interrupt request.
CHAPTER 9 INTERRUPT CONTROL UNIT (ICU) 9.2.10 MPIUINTREG (0x0B00 008E) Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved RTCRST Other resets Name Reserved PADCMD PADADP PADPAGE1 PADPAGE0 PADDLOST Reserved PENCHG INTR INTR INTR INTR INTR INTR RTCRST Other resets Name Function 15 to 7...
CHAPTER 9 INTERRUPT CONTROL UNIT (ICU) 9.2.11 MAIUINTREG (0x0B00 0090) Name Reserved Reserved Reserved Reserved Reserved Reserved INTMIDLE INTMST RTCRST Other resets Name Reserved Reserved Reserved Reserved Reserved Reserved INTSIDLE Reserved RTCRST Other resets Name Function 15 to 10 Reserved Write 0 when write INTMIDLE Enables audio input (microphone) idle interrupt (received data is lost)
CHAPTER 9 INTERRUPT CONTROL UNIT (ICU) 9.2.12 MKIUINTREG (0x0B00 0092) Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved RTCRST Other resets Name Reserved Reserved Reserved Reserved Reserved MSKKDAT MSKKDAT MSKK LOST DOWNINT RTCRST Other resets Name Function 15 to 3 Reserved 0 is returned when read MSKKDATLOST...
CHAPTER 10 POWER MANAGEMENT UNIT (PMU) This chapter describes the Power Management Unit (PMU) operation, register settings and power modes. 10.1 General The PMU performs power management within the V 4181 and controls the power supply throughout the system. The PMU provides the following functions: •...
CHAPTER 10 POWER MANAGEMENT UNIT (PMU) Figure 10-1. Transition of V 4181 Power Mode Standby Suspend mode mode Fullspeed mode reset Hibernate mode Transition No. Factors STANDBY instruction All interrupt requests SUSPEND instruction <After transition> DRAM self refresh Assertion of POWER Assertion and then deassertion of RSTSW# Interrupt request such as: ElapsedTime timer Key press...
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CHAPTER 10 POWER MANAGEMENT UNIT (PMU) Table 10-1 shows power mode overview and transaction: Table 10-1. Overview of Power Modes Mode Internal peripheral unit CPU core LCDC Others Fullspeed Selectable Standby Selectable Suspend Hibernate (1) Fullspeed mode All internal clocks and bus clocks operate. The V 4181 can perform every function during the Fullspeed mode.
CHAPTER 10 POWER MANAGEMENT UNIT (PMU) (4) Hibernate mode All clocks other than the RTC clock (32.768 kHz) are fixed to high level and the PLL operation stops. An RTC and a monitor for activation factors in the PMU continue their operation. To enter to Hibernate mode from Fullspeed mode, execute a Hibernate mode sequence (see 10.6 DRAM Interface Control) first.
CHAPTER 10 POWER MANAGEMENT UNIT (PMU) 10.3.2 RSTSW reset When the RSTSW# signal becomes active, the PMU resets (Cold Reset) the CPU core. When bit 6 of the PMUINTREG register is cleared to 0, the PMU also resets all internal peripheral units except for the RTC and GIU. In addition, the RSTSW bit in the PMUINTREG register is set to 1.
CHAPTER 10 POWER MANAGEMENT UNIT (PMU) 10.4 Shutdown Control The operations of the RTC, peripheral units, and CPU core, and PMUINTREG register bit settings during a reset are listed below. For detail of the timing of each shutdown, refer to CHAPTER 5 INITIALIZATION INTERFACE. Table 10-3.
CHAPTER 10 POWER MANAGEMENT UNIT (PMU) 10.5 Power-on Control The causes of CPU core activation (mode change from shutdown mode or Hibernate mode to Fullspeed mode) are called activation factors. There are twenty activation factors: a power switch interrupt (POWER), sixteen types of GPIO activation interrupts (GPIO(15:0)), a DCD interrupt (DCD#), a CompactFlash interrupt, and an ElapsedTime interrupt.
CHAPTER 10 POWER MANAGEMENT UNIT (PMU) 10.5.1 Activation via Power Switch interrupt request When the POWER signal is asserted, the PMU asserts the POWERON signal to provide an external notification that the CPU core is being activated. After asserting the POWERON signal, the PMU checks the BATTINH signal and then de-asserts the POWERON signal.
CHAPTER 10 POWER MANAGEMENT UNIT (PMU) 10.5.2 Activation via CompactFlash interrupt request When the CF_BUSY# signal is asserted, the PMU asserts the POWERON signal to provide an external notification that the CPU core is being activated. After asserting the POWERON signal, the PMU checks the BATTINH signal and then de-asserts the POWERON signal.
CHAPTER 10 POWER MANAGEMENT UNIT (PMU) 10.5.3 Activation via GPIO activation interrupt request When any of the GPIO(15:0) signals are asserted, the PMU checks the GPIO(15:0) activation interrupt enable bits in the GIU. If GPIO(15:0) activation interrupts are enabled, the PMU asserts the POWERON signal to provide an external notification that the CPU core is being activated (since the GPIO(15:0) activation enable interrupt bits are cleared after an RTC reset, the GPIO(15:0) signal cannot be used for activation immediately after an RTC reset).
CHAPTER 10 POWER MANAGEMENT UNIT (PMU) 10.5.4 Activation via DCD interrupt request When the DCD1# signal is asserted, the PMU asserts the POWERON signal to provide an external notification that the CPU core is being activated. After asserting the POWERON signal, the PMU checks the BATTINH signal and then de-asserts the POWERON signal.
CHAPTER 10 POWER MANAGEMENT UNIT (PMU) 10.5.5 Activation via ElapsedTime (RTC alarm) interrupt request When the alarm (alarm_intr signal) generated from the ElapsedTime timer is asserted, the PMU asserts the POWERON signal to provide an external notification that the CPU core is being activated. After asserting the POWERON signal, the PMU checks the BATTINH signal and then de-asserts the POWERON signal.
CHAPTER 10 POWER MANAGEMENT UNIT (PMU) 10.6 DRAM Interface Control The PMU provides a register to control the DRAM interface during Hibernate mode or Suspend mode. The DRAMHIBCTL register permits software to directly control the state of the DRAM interface pins prior to executing a HIBERNATE or SUSPEND instruction.
CHAPTER 10 POWER MANAGEMENT UNIT (PMU) 10.6.2 Entering Hibernate mode (SDRAM) <1> Copy contents of all 2.5 V registers (i.e. DRAM type and configuration, ROM type and configuration, etc.) that must be preserved during Hibernate mode into the general-purpose registers, MISCREG(0:15), in the GIU or into external memory.
CHAPTER 10 POWER MANAGEMENT UNIT (PMU) 10.6.3 Exiting Hibernate mode (EDO DRAM) <1> Generate a wake-up event such as a transition on the POWER pin, a DCD interrupt, etc. which causes the PMU to start a power-on sequence. <2> Apply 2.5 V power supply when the MPOWER signal becomes high level. The PMU waits until 3.3 V and 2.5 V power supply are stable, and then deasserts the reset signals to the V 4110 CPU core and on-chip peripheral units.
CHAPTER 10 POWER MANAGEMENT UNIT (PMU) 10.6.4 Exiting Hibernate mode (SDRAM) <1> Generate a wake-up event such as a transition on the POWER pin, a DCD interrupt, etc. which causes the PMU to start a power-on sequence. <2> Apply 2.5 V power supply when the MPOWER signal becomes high level. The PMU waits until 3.3 V and 2.5 V power supply are stable, and then deasserts the reset signals to the V 4110 CPU core and on-chip peripheral units.
CHAPTER 10 POWER MANAGEMENT UNIT (PMU) 10.6.5 Entering Suspend mode (EDO DRAM) <1> Stop operations of the DMA controller and LCD controller. <2> Set registers in the ICU and CP0 to allow notification of the interrupt requests used as wake-up events to Fullspeed mode to the CPU core.
CHAPTER 10 POWER MANAGEMENT UNIT (PMU) 10.6.6 Entering Suspend mode (SDRAM) <1> Stop operations of the DMA controller and LCD controller. <2> Set registers in the ICU and CP0 to allow notification of the interrupt requests used as wake-up events to Fullspeed mode to the CPU core.
CHAPTER 10 POWER MANAGEMENT UNIT (PMU) 10.6.7 Exiting Suspend mode (EDO DRAM) <1> Generate a wake-up event from Suspend mode such as a transition on the POWER pin, a DCD interrupt, etc. <2> Software execution resumes at the General exception vector (0x0BFC 0380 when BEV = 1). <3>...
CHAPTER 10 POWER MANAGEMENT UNIT (PMU) 10.7.1 PMUINTREG (0x0B00 00A0) (1/2) Name Reserved Reserved Reserved CF_INT DCDST RTCINTR BATTINH WAKEUP RTCRST Other resets Name Reserved SDRAM TIMOUT RTCRST RSTSW DMSRST BATTINTR POWER SWINTR RTCRST Other resets Name Function 15 to 13 Reserved 0 is returned when read GPWAKEUP...
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CHAPTER 10 POWER MANAGEMENT UNIT (PMU) (2/2) Name Function TIMOUTRST HALTimer reset request detection. Cleared to 0 when 1 is written. 1 : Detected 0 : Not detected This bit must be checked and cleared to 0 after the CPU core is restarted. RTCRST RTC reset detection.
CHAPTER 10 POWER MANAGEMENT UNIT (PMU) 10.7.2 PMUCNTREG (0x0B00 00A2) (1/2) Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved RTCRST Other resets Name STANDBY Reserved Selfrfresh Suspend Hibernate HALTIMER Reserved Reserved RTCRST Other resets Note Name Function 15 to 8 Reserved 0 is returned when read STANDBY...
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CHAPTER 10 POWER MANAGEMENT UNIT (PMU) (2/2) Name Function HALTIMERRST HALTimer reset 1 : Reset 0 : Set Note1, 2 This bit is cleared to 0 automatically after reset of the HALTimer Reserved 0 is returned when read Reserved Write 0 when write. 0 is returned when read. Notes1.
CHAPTER 10 POWER MANAGEMENT UNIT (PMU) 10.7.4 PMUDIVREG (0x0B00 00AC) Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved RTCRST Other resets Name Reserved Reserved Reserved Reserved Reserved DIV2 DIV1 DIV0 RTCRST Other resets Note Note Note Name Function 15 to 3 Reserved 0 is returned when read 2 to 0...
CHAPTER 11 REALTIME CLOCK UNIT (RTC) This chapter describes the RTC unit’s operations and register settings. 11.1 General The RTC unit has a total of three timers, including the following two types. • RTCLong ..This is a 24-bit programmable counter that counts down by 32.768 kHz clock cycle. Cycle interrupts can be occurred for up to every 512 seconds.
CHAPTER 12 DEADMAN’S SWITCH UNIT (DSU) This chapter describes operations and register settings of the DSU (Deadman’s Switch Unit). 12.1 General The DSU detects runaway (endless loop) state of the V 4181 and resets the V 4181. Use of the DSU allows terminating runaway states that may occur due to software in earlier phase to minimize data loss.
CHAPTER 12 DEADMAN’S SWITCH UNIT (DSU) 12.2.1 DSUCNTREG (0x0B00 00E0) Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved RTCRST Other resets Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved DSWEN RTCRST Other resets Name Function 15 to 1 Reserved 0 is returned when read DSWEN Deadman’s Switch function enable...
CHAPTER 12 DEADMAN’S SWITCH UNIT (DSU) 12.2.2 DSUSETREG (0x0B00 00E2) Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved RTCRST Other resets Name Reserved Reserved Reserved Reserved DEDTIME3 DEDTIME2 DEDTIME1 DEDTIME0 RTCRST Other resets Name Function 15 to 4 Reserved 0 is returned when read 3 to 0 DEDTIME(3:0)
CHAPTER 12 DEADMAN’S SWITCH UNIT (DSU) 12.2.3 DSUCLRREG (0x0B00 00E4) Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved RTCRST Other resets Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved DSWCLR RTCRST Other resets Name Function 15 to 1 Reserved 0 is returned when read DSWCLR Deadman’s Switch timer clear...
CHAPTER 12 DEADMAN’S SWITCH UNIT (DSU) 12.2.4 DSUTIMREG (0x0B00 00E6) Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved RTCRST Other resets Name Reserved Reserved Reserved Reserved CRTTIME3 CRTTIME2 CRTTIME1 CRTTIME0 RTCRST Other resets Name Function 15 to 4 Reserved 0 is returned when read 3 to 0 CRTTIME(3:0)
CHAPTER 12 DEADMAN’S SWITCH UNIT (DSU) 12.3 Register Setting Flow The DSU register setting flow is described below. <1> Set the DSU timer count cycle (from 1 to 15 seconds). Register: DSUSETREG, address: 0x0B00 00E2, data: 0x000x The CPU core will be reset if the timer is not cleared (1 is not written to DSUCLRREG register) within this time period.
CHAPTER 13 GENERAL PURPOSE I/O UNIT (GIU) 13.1 Overview 13.1.1 GPIO pins and alternate functions The V 4181 provides 32 general-purpose I/O divided into two groups of 16 pins each. The first group, GPIO(15:0) pins, are capable of supporting the following types of functions: •...
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CHAPTER 13 GENERAL PURPOSE I/O UNIT (GIU) The second group, GPIO(31:16) pins, are capable of supporting the following types of functions: • External ISA I/O interface • External 16-bit bus sizing signal • ROM chip select • Serial interface channel 1 •...
CHAPTER 13 GENERAL PURPOSE I/O UNIT (GIU) 13.1.2 I/O direction control For each GPIO pin, the GIU provides register fields of one buffer enable, GPENn, one output data, GPOn, and one input data, GPIn. The function of each GPIO pin is decoded by 2 register bits in one of the GPIO Mode registers. The most significant bit, GPnMD1, controls the input/output direction of the GPIO pin while the system is powered (during Fullspeed, Standby, or Suspend mode).
CHAPTER 13 GENERAL PURPOSE I/O UNIT (GIU) 13.2.2 Serial interface channels 1 and 2 The GIU also provides pin mapping for the serial interface (equivalent to 16550 UART) channels 1 and 2. The serial interface channel 1 (SIU1) is enabled by writing to the GPIO Mode registers. It utilizes the following GPIO pins: Table 13-4.
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CHAPTER 13 GENERAL PURPOSE I/O UNIT (GIU) The serial interface channel 2 (SIU2) utilizes the dedicated IRDIN/RxD2 and IRDOUT/TxD2 pins. The line control signals, DTR2#, RTS2#, DCD2#, DSR2#, and CTS2#, are enabled by writing to the GPIO Mode registers and are utilized through the following GPIO pins: Table 13-6.
CHAPTER 13 GENERAL PURPOSE I/O UNIT (GIU) 13.2.3 LCD interface The GIU supports two functions for the LCD interface. The first is pin mapping for 8-bit STN color LCD panel support. The second is pin mapping for support of an external LCD controller with integrated frame buffer RAM. For additional details about the LCD registers, see CHAPTER 21 LCD CONTROLLER.
CHAPTER 13 GENERAL PURPOSE I/O UNIT (GIU) 13.2.4 Programmable chip selects The GIU provides two programmable chip select signals, PCS(1:0)#. These chip select signals are available on the following GPIO pins: Table 13-10. Programmable Chip Select Signals GPIO pin Programmable chip select Type GPIO11 PCS1#...
CHAPTER 13 GENERAL PURPOSE I/O UNIT (GIU) 13.2.7 Interrupt requests and wake-up events Each of the lower sixteen GPIO pins, GPIO(15:0), can be defined as an interrupt request input. The GIU provides a single asynchronous interrupt request output to the MBA Host Bridge, GPIOINTR. The MBA Host Bridge is responsible for synchronizing this interrupt request with the MasterOut clock (internal).
CHAPTER 13 GENERAL PURPOSE I/O UNIT (GIU) 13.3.1 GPMD0REG (0x0B00 0300) (1/2) Name GP7MD1 GP7MD0 GP6MD1 GP6MD0 GP5MD1 GP5MD0 GP4MD1 GP4MD0 RTCRST Note Note Note Note Note Note Note Note Other resets Name GP3MD1 GP3MD0 GP2MD1 GP2MD0 GP1MD1 GP1MD0 GP0MD1 GP0MD0 RTCRST Other resets...
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CHAPTER 13 GENERAL PURPOSE I/O UNIT (GIU) (2/2) Name Function 5, 4 GP2MD(1:0) These bits control direction and function of the GPIO2 pin as follows: 00 : General-purpose input 01 : CSI SCK input 10 : General-purpose output 11 : RFU 3, 2 GP1MD(1:0) These bits control direction and function of the GPIO1 pin as follows:...
CHAPTER 13 GENERAL PURPOSE I/O UNIT (GIU) 13.3.2 GPMD1REG (0x0B00 0302) (1/2) Name GP15MD1 GP15MD0 GP14MD1 GP14MD0 GP13MD1 GP13MD0 GP12MD1 GP12MD0 RTCRST Note Note Note Note Note Note Note Note Other resets Name GP11MD1 GP11MD0 GP10MD1 GP10MD0 GP9MD1 GP9MD0 GP8MD1 GP8MD0 RTCRST Other resets...
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CHAPTER 13 GENERAL PURPOSE I/O UNIT (GIU) (2/2) Name Function 5, 4 GP10MD(1:0) These bits control direction and function of the GPIO10 pin as follows: 00 : General-purpose input 01 : CSI FRM input 10 : General-purpose output 11 : SYSCLK output 3, 2 GP9MD(1:0) These bits control direction and function of the GPIO9 pin as follows:...
CHAPTER 13 GENERAL PURPOSE I/O UNIT (GIU) 13.3.3 GPMD2REG (0x0B00 0304) (1/2) Name GP23MD1 GP23MD0 GP22MD1 GP22MD0 GP21MD1 GP21MD0 GP20MD1 GP20MD0 RTCRST Note Note Note Note Note Note Note Note Other resets Name GP19MD1 GP19MD0 GP18MD1 GP18MD0 GP17MD1 GP17MD0 GP16MD1 GP16MD0 RTCRST Other resets...
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CHAPTER 13 GENERAL PURPOSE I/O UNIT (GIU) (2/2) Name Function 5, 4 GP18MD(1:0) These bits control direction and function of the GPIO18 pin as follows: 00 : General-purpose input 01 : IORDY input 10 : General-purpose output 11 : RFU 3, 2 GP17MD(1:0) These bits control direction and function of the GPIO17 pin as follows:...
CHAPTER 13 GENERAL PURPOSE I/O UNIT (GIU) 13.3.4 GPMD3REG (0x0B00 0306) (1/2) Name GP31MD1 GP31MD0 GP30MD1 GP30MD0 GP29MD1 GP29MD0 GP28MD1 GP28MD0 RTCRST Note Note Note Note Note Note Note Note Other resets Name GP27MD1 GP27MD0 GP26MD1 GP26MD0 GP25MD1 GP25MD0 GP24MD1 GP24MD0 RTCRST Other resets...
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CHAPTER 13 GENERAL PURPOSE I/O UNIT (GIU) (2/2) Name Function 5, 4 GP26MD(1:0) These bits control direction and function of the GPIO26 pin as follows: 00 : General-purpose input 01 : RFU 10 : General-purpose output 11 : SIU1 TxD1 output 3, 2 GP25MD(1:0) These bits control direction and function of the GPIO25 pin as follows:...
CHAPTER 13 GENERAL PURPOSE I/O UNIT (GIU) 13.3.9 GPINTTYPH (0x0B00 0310) (1/2) Name I15TYP1 I15TYP0 I14TYP1 I14TYP0 I13TYP1 I13TYP0 I12TYP1 I12TYP0 RTCRST Note Note Note Note Note Note Note Note Other resets Name I11TYP1 I11TYP0 I10TYP1 I10TYP0 I9TYP1 I9TYP0 I8TYP1 I8TYP0 RTCRST Other resets...
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CHAPTER 13 GENERAL PURPOSE I/O UNIT (GIU) (2/2) Name Function 7, 6 I11TYP(1:0) These bits define the type of interrupt generated when the GPIO11 pin is defined as a general-purpose input: 00 : Negative edge triggered interrupt 01 : Positive edge triggered interrupt 10 : Low level triggered interrupt 11 : High level triggered interrupt 5, 4...
CHAPTER 13 GENERAL PURPOSE I/O UNIT (GIU) 13.3.10 GPINTTYPL (0x0B00 0312) (1/2) Name I7TYP1 I7TYP0 I6TYP1 I6TYP0 I5TYP1 I5TYP0 I4TYP1 I4TYP0 RTCRST Note Note Note Note Note Note Note Note Other resets Name I3TYP1 I3TYP0 I2TYP1 I2TYP0 I1TYP1 I1TYP0 I0TYP1 I0TYP0 RTCRST Other resets...
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CHAPTER 13 GENERAL PURPOSE I/O UNIT (GIU) (2/2) Name Function 7, 6 I3TYP(1:0) These bits define the type of interrupt generated when the GPIO3 pin is defined as a general-purpose input: 00 : Negative edge triggered interrupt 01 : Positive edge triggered interrupt 10 : Low level triggered interrupt 11 : High level triggered interrupt 5, 4...
CHAPTER 13 GENERAL PURPOSE I/O UNIT (GIU) 13.3.14 GPSICTL (0x0B00 031A) (1/2) Name LOOPBK1 Reserved Reserved Reserved REGRXD1 REGCTS1 REGDSR1 REGDCD1 RTCRST Note Note Note Note Note Other resets Name LOOPBK2 Reserved Reserved Reserved Reserved REGCTS2 REGDSR2 REGDCD2 RTCRST Other resets Note Note Note...
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CHAPTER 13 GENERAL PURPOSE I/O UNIT (GIU) (2/2) Name Function LOOPBK2 Loopback enable for serial interface channel 2. When GPIO pins have not be allocated for the line status signals DSR2# and/or CTS2# of the serial interface channel 2, this bit can be set to 1 to allow the serial interface line status output signals to be connected to the line status input signals as follows: DTR2# output from serial interface drives the DSR2# input to serial interface RTS2# output from serial interface drives the CTS2# input to serial interface...
CHAPTER 13 GENERAL PURPOSE I/O UNIT (GIU) 13.3.23 LCDGPMODE (0x0B00 032E) Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved RTCRST Other resets Name LCDGPEN Reserved Reserved Reserved LCDCS1 LCDCS0 GPVPBIAS GPVPLCD RTCRST Other resets Note Note Note Note Note Name Function 15 to 8...
CHAPTER 14 TOUCH PANEL INTERFACE UNIT (PIU) 14.1 General The PIU uses the on-chip A/D converter to detect the X and Y coordinates of pen contact locations on a touch panel and to scan the general-purpose A/D input port. Since the touch panel control circuit and the A/D converter (conversion precision: 10 bits) are both incorporated, the touch panel is connected directly to the V 4181.
CHAPTER 14 TOUCH PANEL INTERFACE UNIT (PIU) 14.1.1 Block diagrams Figure 14-1. PIU Peripheral Block Diagram 4181 AUDIOIN Battery, etc. ADIN2 ADIN1 Buffer ADIN0 Touch panel TPY1 TPY0 TPX1 Buffer TPX0 • Touch panel A set of four pins are located at the edges of the X-axis and Y-axis resistance layers, and the two layers have high resistance when there is no pen contact and low resistance when there is a pen contact.
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CHAPTER 14 TOUCH PANEL INTERFACE UNIT (PIU) Figure 14-2. Coordinate Detection Equivalent Circuits (a) Y-coordinate detection TPY1 pin: 3 V TPY1 pin: 0 V TPX0 pin TPX0 pin TPY0 pin: 0 V TPY0 pin: 3 V (b) X-coordinate detection TPY0 pin TPY0 pin TPX0 pin: 3 V TPX1 pin: 0 V...
CHAPTER 14 TOUCH PANEL INTERFACE UNIT (PIU) The PIU includes three blocks: the internal bus controller, the scan sequencer, and the touch panel interface controller. • Internal bus controller The internal bus controller controls the internal bus, the PIU registers, and interrupts, and communicates with the A/D converter.
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CHAPTER 14 TOUCH PANEL INTERFACE UNIT (PIU) • Disable state In this state, the A/D converter is in standby status, the output pins are in touch detection status (no PIU interrupt), and the input pins are in mask status (to prevent misoperation when an undefined input is applied). •...
CHAPTER 14 TOUCH PANEL INTERFACE UNIT (PIU) This register sets and indicates the interrupt request generation of the PIU. When the PENCHGINTR bit is set to1, the PENSTC bit of the PIUCNTREG register indicates the touch panel contact status (touch or release) when a contact status changes. The PENSTC bit’s status remains until the PENCHGINTR bit is cleared to 0.
CHAPTER 14 TOUCH PANEL INTERFACE UNIT (PIU) Figure 14-5. Interval Times and States State DataScan Interval ADPScan Interval DataScan Operation S A S A S A S A A A A A S A S A S A S A Interval time Remark S: Voltage stabilization wait time (STABLE(5:0) in PIUSTBLREG)
CHAPTER 14 TOUCH PANEL INTERFACE UNIT (PIU) 14.3.5 PIUCMDREG (0x0B00 012A) (1/2) Name Reserved Reserved Reserved STABLEON TPYEN1 TPYEN0 TPXEN1 TPXEN0 RTCRST Other resets Name TPYD1 TPYD0 TPXD1 TPXD0 ADCMD3 ADCMD2 ADCMD1 ADCMD0 RTCRST Other resets Name Function 15 to 13 Reserved 0 is returned when read STABLEON...
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CHAPTER 14 TOUCH PANEL INTERFACE UNIT (PIU) (2/2) Name Function 3 to 0 ADCMD(3:0) A/D converter input port selection for command scan 1111 : A/D converter standby mode request 1110 : RFU 1000 : RFU 0111 : AUDIOIN port 0110 : ADIN2 port 0101 : ADIN1 port 0100 : ADIN0 port 0011 : TPY1 port...
CHAPTER 14 TOUCH PANEL INTERFACE UNIT (PIU) 14.3.6 PIUASCNREG (0x0B00 0130) Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved RTCRST Other resets Name Reserved Reserved Reserved Reserved Reserved Reserved TPPSCAN ADPS START RTCRST Other resets Name Function 15 to 2 Reserved 0 is returned when read Port selection for ADPScan...
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CHAPTER 14 TOUCH PANEL INTERFACE UNIT (PIU) Table 14-4. PIUASCNREG Bit Manipulation and States PIUASCNREG bit Scan sequencer’s state manipulation Disable Standby WaitPenTouch DataScan Note1 Note2 Note2 0 → 1 × × ADPSSTART ADPScan ADPScan 1 → 0 × × 0 →...
CHAPTER 14 TOUCH PANEL INTERFACE UNIT (PIU) 14.3.7 PIUAMSKREG (0x0B00 0132) Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved RTCRST Other resets Name ADINM3 ADINM2 ADINM1 ADINM0 TPYM1 TPYM0 TPXM1 TPXM0 RTCRST Other resets Name Function 15 to 8 Reserved 0 is returned when read ADINM3...
CHAPTER 14 TOUCH PANEL INTERFACE UNIT (PIU) 14.4 State Transition Flow Be sure to initialize the PIU before scan sequencer operation. Initialization via a reset sets particular values for the sequence interval, etc., which should be re-set to appropriate values. The following registers require initial settings.
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CHAPTER 14 TOUCH PANEL INTERFACE UNIT (PIU) (3) Transition flow for manual scan coordinate detection Disable state <1> PIUCNTREG PIUPWR = 1 ↓ Standby state <2> PIUCNTREG PIUMODE(1:0) = 00 PADSCANSTART = 1 <3> PIUCNTREG PIUSEQEN = 1 ↓ DataScan state (4) Transition flow when entering Suspend mode transition Standby, WaitPenTouch, or Interval state <1>...
CHAPTER 14 TOUCH PANEL INTERFACE UNIT (PIU) 14.6 Timing 14.6.1 Touch/release detection timing Touch/release detection is not determined via the A/D converter but the voltage level of the TPY1 pin. The following figure shows a timing of touch/release detection and coordinate detection. Figure 14-6.
CHAPTER 14 TOUCH PANEL INTERFACE UNIT (PIU) 14.7 Data Loss Conditions The PIU issues a data lost interrupt request when any of the following four conditions exist. 1. Data for one coordinate has not been obtained within the interval period 2.
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CHAPTER 14 TOUCH PANEL INTERFACE UNIT (PIU) (3) When transfer of the next coordinate data starts while valid data for both pages remains in the buffer Cause This condition is caused when the data buffer contains two pages of valid data (both the data buffer page 1 and data buffer page 0 interrupt requests have occurred) but the valid data has not been processed.
CHAPTER 15 AUDIO INTERFACE UNIT (AIU) 15.1 General The AIU controls the analog output (speaker output) processing of the internal D/A converter and the analog input (microphone input) processing of the internal A/D converter. It is also used to make settings related to the A/D and D/A converters.
CHAPTER 15 AUDIO INTERFACE UNIT (AIU) 15.2.1 SDMADATREG (0x0B00 0160) Name Reserved Reserved Reserved Reserved Reserved Reserved SDMA9 SDMA8 RTCRST Other resets Name SDMA7 SDMA6 SDMA5 SDMA4 SDMA3 SDMA2 SDMA1 SDMA0 RTCRST Other resets Name Function 15 to 10 Reserved 0 is returned when read 9 to 0 SDMA(9:0)
CHAPTER 15 AUDIO INTERFACE UNIT (AIU) 15.2.2 MDMADATREG (0x0B00 0162) Name Reserved Reserved Reserved Reserved Reserved Reserved MDMA9 MDMA8 RTCRST Other resets Name MDMA7 MDMA6 MDMA5 MDMA4 MDMA3 MDMA2 MDMA1 MDMA0 RTCRST Other resets Name Function 15 to 10 Reserved 0 is returned when read 9 to 0 MDMA(9:0)
CHAPTER 15 AUDIO INTERFACE UNIT (AIU) 15.2.4 SODATREG (0x0B00 0166) Name Reserved Reserved Reserved Reserved Reserved Reserved SODAT9 SODAT8 RTCRST Other resets Name SODAT7 SODAT6 SODAT5 SODAT4 SODAT3 SODAT2 SODAT1 SODAT0 RTCRST Other resets Name Function 15 to 10 Reserved 0 is returned when read 9 to 0 SODAT(9:0)
CHAPTER 15 AUDIO INTERFACE UNIT (AIU) 15.2.6 SCNVC_END (0x0B00 016E) Name SCNVC15 SCNVC14 SCNVC13 SCNVC12 SCNVC11 SCNVC10 SCNVC9 SCNVC8 RTCRST Other resets Name SCNVC7 SCNVC6 SCNVC5 SCNVC4 SCNVC3 SCNVC2 SCNVC1 SCNVC0 RTCRST Other resets Name Function 15 to 0 SCNVC(15:0) Speaker sample rate control This register is used to select a conversion rate for the D/A converter.
CHAPTER 15 AUDIO INTERFACE UNIT (AIU) 15.2.7 MIDATREG (0x0B00 0170) Name Reserved Reserved Reserved Reserved Reserved Reserved MIDAT9 MIDAT8 RTCRST Other resets Name MIDAT7 MIDAT6 MIDAT5 MIDAT4 MIDAT3 MIDAT2 MIDAT1 MIDAT0 RTCRST Other resets Name Function 15 to 10 Reserved 0 is returned when read 9 to 0 MIDAT(9:0)
CHAPTER 15 AUDIO INTERFACE UNIT (AIU) 15.2.9 DVALIDREG (0x0B00 0178) Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved RTCRST Other resets Name Reserved Reserved Reserved Reserved SODATV SDMAV MIDATV MDMAV RTCRST Other resets Name Function 15 to 4 Reserved 0 is returned when read SODATV This indicates whether valid data has been stored in SODATREG.
CHAPTER 15 AUDIO INTERFACE UNIT (AIU) 15.2.10 SEQREG (0x0B00 017A) Name AIURST Reserved Reserved Reserved Reserved Reserved Reserved Reserved RTCRST Other resets Name Reserved Reserved Reserved AIUMEN Reserved Reserved Reserved AIUSEN RTCRST Other resets Name Function AIURST AIU reset via software 1 : Reset 0 : Normal 14 to 5...
CHAPTER 15 AUDIO INTERFACE UNIT (AIU) 15.2.11 INTREG (0x0B00 017C) Name Reserved Reserved Reserved Reserved Reserved Reserved MIDLEINTR MSTINTR RTCRST Other resets Name Reserved Reserved Reserved Reserved Reserved Reserved SIDLEINTR Reserved RTCRST Other resets Name Function 15 to 10 Reserved 0 is returned when read MIDLEINTR Microphone idle interrupt request (receive data loss).
CHAPTER 15 AUDIO INTERFACE UNIT (AIU) 15.3 Operation Sequence 15.3.1 Output (speaker) 1. Set conversion rate (0x0B00 016E: SCNVC(15:0) = any value) 2. Set D/A converter Vref setup time (0x0B00 0164: any value to be DVAREF(15:0)/PCLK frequency = 5 µ s) 3.
CHAPTER 15 AUDIO INTERFACE UNIT (AIU) 15.3.2 Input (microphone) 1. Set conversion rate (0x0B00 017E: MCNVC(15:0) = any value) 2. Set D/A converter Vref setup time (0x0B00 0164: any value to be DVAREF(15:0)/PCLK frequency = 5 µ s) 3. Enable DMA after setting DMA address in DCU 4.
CHAPTER 16 KEYBOARD INTERFACE UNIT (KIU) 16.1 General The Keyboard Interface Unit (KIU) provides the interface between the V 4181 and an external matrix type keyboard. This unit supports key matrix of 8 x 8. The interface to the keyboard consists of SCANOUT (3-state output) and SCANIN (input) lines. The SCANOUT lines are used to search the matrix for pressed keys.
CHAPTER 16 KEYBOARD INTERFACE UNIT (KIU) The following table illustrates the relationship between these bits: Table 16-1. Settings of Keyboard Scan Mode ASTOP ASTART MSTART MSTOP Operation Scanning disabled Scanning stopped Manual Scan mode. Scan operation starts as soon as a setting of the MSTART bit is detected by the scan sequencer and stops when the MSTOP bit is set to 1.
CHAPTER 16 KEYBOARD INTERFACE UNIT (KIU) 16.2.4 Scan operation Scan operations are controlled by the T1CNT(4:0) and T3CNT(4:0) bits of the KIUWKS register and the WINTVL(9:0) bits of the KIUWKI register. The following diagram illustrates the relationship of these register bits to the scan operation: Figure 16-1.
CHAPTER 16 KEYBOARD INTERFACE UNIT (KIU) 16.2.5 Reading scanned data Scanned data is read from the SCANIN(7:0) pins. When a SCANOUT pin has been driven as low and the keyboard settling time specified by the T1CNT(4:0) bits has been elapsed, the KIU latches scanned data from the SCANIN pins and stores into one of the internal key data registers.
CHAPTER 16 KEYBOARD INTERFACE UNIT (KIU) 16.3 Register Set The KIU registers are listed below. Table 16-2. KIU Registers Physical address Register symbol Function 0x0B00 0180 KIUDAT0 Scan line 0 keyboard data register 0x0B00 0182 KIUDAT1 Scan line 1 keyboard data register 0x0B00 0184 KIUDAT2 Scan line 2 keyboard data register...
CHAPTER 16 KEYBOARD INTERFACE UNIT (KIU) 16.3.2 KIUSCANREP (0x0B00 0190) Name KEYEN Reserved Reserved Reserved Reserved Reserved STPREP5 STPREP4 RTCRST Other resets Name STPREP3 STPREP2 STPREP1 STPREP0 MSTOP MSTART ASTOP ASTART RTCRST Other resets Name Function KEYEN KIU enable. This bit enables a KIU operation. When this bit is set to 0, the scan sequencer and all interrupt requests are disabled.
CHAPTER 16 KEYBOARD INTERFACE UNIT (KIU) 16.3.3 KIUSCANS (0x0B00 0192) Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved RTCRST Other resets Name Reserved Reserved Reserved Reserved Reserved Reserved SSTAT1 SSTAT0 RTCRST Other resets Name Function 15 to 2 Reserved 0 is returned when read 1, 0 SSTAT(1:0)
CHAPTER 16 KEYBOARD INTERFACE UNIT (KIU) 16.3.4 KIUWKS (0x0B00 0194) Name Reserved T3CNT4 T3CNT3 T3CNT2 T3CNT1 T3CNT0 Reserved Reserved RTCRST Other resets Name Reserved Reserved Reserved T1CNT4 T1CNT3 T1CNT2 T1CNT1 T1CNT0 RTCRST Other resets Name Function Reserved 0 is returned when read 14 to 10 T3CNT(4:0) Scan idle time.
CHAPTER 16 KEYBOARD INTERFACE UNIT (KIU) 16.3.5 KIUWKI (0x0B00 0196) Name Reserved Reserved Reserved Reserved Reserved Reserved WINTVL9 WINTVL8 RTCRST Other resets Name WINTVL7 WINTVL6 WINTVL5 WINTVL4 WINTVL3 WINTVL2 WINTVL1 WINTVL0 RTCRST Other resets Name Function 15 to 10 Reserved 0 is returned when read 9 to 0 WINTVL(9:0)
CHAPTER 16 KEYBOARD INTERFACE UNIT (KIU) 16.3.6 KIUINT (0x0B00 0198) Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved RTCRST Other resets Name Reserved Reserved Reserved Reserved Reserved KDATLOST KDATRDY KEYDOWN RTCRST Other resets Name Function 15 to 3 Reserved 0 is returned when read KDATLOST Key data lost interrupt request.
CHAPTER 17 COMPACTFLASH CONTROLLER (ECU) 17.1 General The V 4181 provides an ExCA-compatible controller (ECU) supporting a single CompactFlash slot. The interface for this controller is shared with that of the keyboard interface unit. To use this interface for CompactFlash control, the KEYSEL bit of the KEYEN register in the GIU must be clear to 0.
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CHAPTER 17 COMPACTFLASH CONTROLLER (ECU) Table 17-2. ECU Registers (1/2) Index Register symbol Function 0x0000 ID_REV_REG Identification and revision register 0x0001 IF_STAT_REG Interface status register 0x0002 PWRRSETDRV Power and RESETDRV control register 0x0003 ITGENCTREG Interrupt and general control register 0x0004 CDSTCHGREG Card status change register 0x0005...
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CHAPTER 17 COMPACTFLASH CONTROLLER (ECU) Table 17-2. ECU Registers (2/2) Index Register symbol Function 0x0020 SYSMEMSL2REG System memory 2 mapping start address low byte register 0x0021 MEMWID2_REG System memory 2 mapping start address high byte register 0x0022 SYSMEMEL2REG System memory 2 mapping stop address low byte register 0x0023 MEMSEL2_REG System memory 2 mapping stop address high byte register...
CHAPTER 17 COMPACTFLASH CONTROLLER (ECU) 17.4 ECU Registers 17.4.1 ID_REV_REG (Index: 0x00) Name IFTYP1 IFTYP0 Reserved Reserved REV3 REV2 REV1 REV0 Reset Name Function 7, 6 IFTYP(1:0) PCSC interface type These bits indicate 10 to reflect that both memory and I/O cards are supported. 5, 4 Reserved 0 is returned when read...
CHAPTER 17 COMPACTFLASH CONTROLLER (ECU) 17.4.2 IF_STAT_REG (Index: 0x01) Name Reserved PWRON RDY/BSY Reserved BVD1 Reset Undefined Undefined Undefined Name Function Reserved 1 is returned when read PWRON CompactFlash card power status 0 : Off 1 : On RDY/BSY CompactFlash card ready/busy status. This bit indicates the current status of RDY/BSY# (CF_BUSY#) signal from a CompactFlash card.
CHAPTER 17 COMPACTFLASH CONTROLLER (ECU) 17.4.3 PWRRSETDRV (Index: 0x02) Name Reserved Reserved PWREN Reserved Reserved Reserved Reserved Reset Name Function Output enable. If this bit is cleared to 0, the CompactFlash interface outputs from the V 4181 are driven to high impedance state and the CF_DEN# and CF_AEN# outputs are driven as high.
CHAPTER 17 COMPACTFLASH CONTROLLER (ECU) 17.4.4 ITGENCTREG (Index: 0x03) Name RI_EN CRDRST CRDTYP Reserved IRQSEL3 IRQSEL2 IRQSEL1 IRQSEL0 Reset Name Function RI_EN Ring indicate enable. This bit is used to switch the function of the STSCHG#/RI# signal from the I/O card. The ring indicator function cannot be used in the V 4181 so that 0 must be written to this bit.
CHAPTER 17 COMPACTFLASH CONTROLLER (ECU) 17.4.7 ADWINENREG (Index: 0x06) Name IOWEN1 IOWEN0 Reserved MWEN4 MWEN3 MWEN2 MWEN1 MWEN0 Reset Name Function 7, 6 IOWEN(1:0) I/O window enables. Generates the card enable signals to the card when an I/O access occurs within the corresponding I/O address window. 0 : Does not generate 1 : Generates I/O addresses are output from the system bus directly to the card.
CHAPTER 17 COMPACTFLASH CONTROLLER (ECU) 17.4.9 IOADSLBnREG (Index: 0x08, 0x0C) Remark n = 0, 1 IOADSLB0REG (0x08): for Window 0 IOADSLB1REG (0x0C): for Window 1 Name STARTA7 STARTA6 STARTA5 STARTA4 STARTA3 STARTA2 STARTA1 STARTA0 Reset Name Function 7 to 0 STARTA(7:0) I/O window start address bits 7 to 0 Low-order address bits used to determine the start address of an I/O address window.
CHAPTER 17 COMPACTFLASH CONTROLLER (ECU) 17.4.11 IOSLBnREG (Index: 0x0A, 0x0E) Remark n = 0, 1 IOSLB0REG (0x0A): for Window 0 IOSLB1REG (0x0E): for Window 1 Name STOPA7 STOPA6 STOPA5 STOPA4 STOPA3 STOPA2 STOPA1 STOPA0 Reset Name Function 7 to 0 STOPA(7:0) I/O window stop address bits 7 to 0 Low-order address bits used to determine the stop address of an I/O address window.
CHAPTER 17 COMPACTFLASH CONTROLLER (ECU) 17.4.19 DTGENCLREG (Index: 0x16) Name Reserved Reserved SWCDINT CDRSMEN Reserved Reserved CFGRSTEN DLY16INH Reset Name Function 7, 6 Reserved 0 is returned when read SWCDINT Software card detect interrupt request 1 : Generates interrupt request This bit is valid when the CD_EN bit is set to 1 in the CRDSTATREG register.
CHAPTER 17 COMPACTFLASH CONTROLLER (ECU) 17.4.20 GLOCTRLREG (Index: 0x1E) Name Reserved Reserved Reserved Reserved Reserved EXWRBK Reserved Reserved Reset Name Function 7 to 3 Reserved 0 is returned when read EXWRBK Card status change interrupt request acknowledgement. 0 : Reading of the CDSTCHGREG register Each bit of the register is cleared after read.
CHAPTER 17 COMPACTFLASH CONTROLLER (ECU) 17.4.22 VOLTSELREG (Index: 0x2F) Name Reserved Reserved Reserved Reserved Reserved Reserved VCCEN1 VCCEN0 Reset Name Function 7 to 2 Reserved 0 is returned when read 1, 0 VCCEN(1:0) Card connection status 01 : 3.3 V card connected 10 : No card connected Caution Do not perform any write to this bit.
CHAPTER 17 COMPACTFLASH CONTROLLER (ECU) 17.5 Memory Mapping of CompactFlash Card (1) Memory window In the V 4181, memory windows can be placed at any address in the ISA memory space. The start address of a memory window is output without modification to the V 4181’s ADD pins.
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CHAPTER 17 COMPACTFLASH CONTROLLER (ECU) (2) I/O window In the V 4181, the I/O window can be mapped to any address within the external ISA I/O space’s lower 64 KB. The start address of a window is output without modification to the V 4181’s ADD pins.
CHAPTER 17 COMPACTFLASH CONTROLLER (ECU) 17.6 Controlling Bus When CompactFlash Card Is Used Access to the CompactFlash card is made via the ISA bridge. The address, data, and command signals operate based on external ISA cycles. The operations of the signals that control the bus size and wait state (MEMCS16#, IOCS16#, and IORDY) can be set in the ECU.
CHAPTER 18 LED CONTROL UNIT (LED) 18.1 General This unit switches ON and OFF of LEDs at a regular interval. The interval can be set via software. 18.2 Register Set The LED registers are listed below. Table 18-1. LED Registers Physical address Register symbol Function...
CHAPTER 18 LED CONTROL UNIT (LED) 18.2.1 LEDHTSREG (0x0B00 0240) Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved RTCRST Other resets Name Reserved Reserved Reserved HTS4 HTS3 HTS2 HTS1 HTS0 RTCRST Other resets Note Note Note Note Note Name Function 15 to 5 Reserved...
CHAPTER 18 LED CONTROL UNIT (LED) 18.2.2 LEDLTSREG (0x0B00 0242) Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved RTCRST Other resets Name Reserved LTS6 LTS5 LTS4 LTS3 LTS2 LTS1 LTS0 RTCRST Note Note Note Note Note Note Note Other resets Name Function 15 to 7...
CHAPTER 18 LED CONTROL UNIT (LED) 18.2.3 LEDCNTREG (0x0B00 0248) Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved RTCRST Other resets Name Reserved Reserved Reserved Reserved Reserved LEDHLB LEDSTOP LEDENABLE RTCRST Other resets Note Note Name Function 15 to 3 Reserved 0 is returned when read LEDHLB...
CHAPTER 18 LED CONTROL UNIT (LED) 18.2.4 LEDASTCREG (0x0B00 024A) Name ASTC15 ASTC14 ASTC13 ASTC12 ASTC11 ASTC10 ASTC9 ASTC8 RTCRST Other resets Name ASTC7 ASTC6 ASTC5 ASTC4 ASTC3 ASTC2 ASTC1 ASTC0 RTCRST Other resets Name Function 15 to 0 ASTC(15:0) LED auto stop time count This register is used to set the number of ON/OFF times prior to automatic stopping of LED blink.
CHAPTER 18 LED CONTROL UNIT (LED) 18.2.5 LEDINTREG (0x0B00 024C) Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved RTCRST Other resets Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved LEDINT RTCRST Other resets Name Function 15 to 1 Reserved 0 is returned when read LEDINT Auto stop interrupt request.
CHAPTER 18 LED CONTROL UNIT (LED) 18.3 Operation Flow Start Register initial setting • LEDHTSREG: 0x0010 (LED ON time available) Register • LEDLTSREG: 0x0020 (LED OFF time available) Note initial setting • LEDCNTREG: 0x0002 • LEDASTCREG: 0x04B0 Set LEDHTSREG LED blinking time setting •...
CHAPTER 19 SERIAL INTERFACE UNIT 1 (SIU1) 19.1 General The SIU1 is a serial interface that conforms to the RS-232-C communication standard and is equipped with two one-channel interfaces, one for transmission and one for reception. This unit is functionally compatible with the NS16550 except for the additional clock control logic to permit the 16650 core clock source to be stopped.
CHAPTER 19 SERIAL INTERFACE UNIT 1 (SIU1) 19.3.4 SIUIE_1 (0x0C00 0011: LCR7 = 0) Name Reserved Reserved Reserved Reserved RTCRST Other resets Name Function 7 to 4 Reserved 0 is returned when read Modem status interrupt 1 : Enable 0 : Prohibit Receive status interrupt 1 : Enable 0 : Prohibit...
CHAPTER 19 SERIAL INTERFACE UNIT 1 (SIU1) 19.3.6 SIUIID_1 (0x0C00 0012: Read) Name IIR7 IIR6 Reserved Reserved IIR3 IIR2 IIR1 IIR0 RTCRST Other resets Name Function 7, 6 IIR(7:6) Becomes 11 when FCR0 bit = 1 5, 4 Reserved 0 is returned when read IIR3 Pending of the character timeout interrupt request (in FIFO mode) 1 : No pending...
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CHAPTER 19 SERIAL INTERFACE UNIT 1 (SIU1) Table 19-3. Interrupt Function SIUIID_1 register Interrupt set/reset function Note Bit 3 Bit 2 Bit 1 Priority level Interrupt type Interrupt source Interrupt reset control Highest (1st) Receive line Overrun error, parity error, framing error, Read line status register status or break interrupt...
CHAPTER 19 SERIAL INTERFACE UNIT 1 (SIU1) 19.3.7 SIUFC_1 (0x0C00 0012: Write) Name FCR7 FCR6 Reserved Reserved FCR3 FCR2 FCR1 FCR0 RTCRST Other resets Name Function 7, 6 FCR(7:6) Receive FIFO trigger level 11 : 14 bytes 10 : 8 bytes 01 : 4 bytes 00 : 0 bytes 5, 4...
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CHAPTER 19 SERIAL INTERFACE UNIT 1 (SIU1) • FIFO interrupt modes When receive FIFO is enabled and receive interrupt requests are enabled, receive interrupts can occur as described below. 1. When the FIFO is reached to the specified trigger level, a receive data ready interrupt request is notified to the CPU.
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CHAPTER 19 SERIAL INTERFACE UNIT 1 (SIU1) When transmit FIFO is enabled and transmit interrupts are enabled, transmit interrupt requests can occur as described below. 1. When the transmit FIFO becomes empty, a transmit holding register empty interrupt request occurs. This interrupt request is cleared when a character is written to the transmit holding register (from one to 16 characters can be written to the transmit FIFO during servicing of this interrupt), or when the SIUIID_1 register is read.
CHAPTER 19 SERIAL INTERFACE UNIT 1 (SIU1) 19.3.9 SIUMC_1 (0x0C00 0014) Name Reserved Reserved Reserved MCR4 MCR3 MCR2 MCR1 MCR0 RTCRST Other resets Name Function 7 to 5 Reserved 0 is returned when read MCR4 Use of diagnostic testing (local loopback) 1 : Enable 0 : Disable MCR3...
CHAPTER 19 SERIAL INTERFACE UNIT 1 (SIU1) 19.3.10 SIULS_1 (0x0C00 0015) Name LSR7 LSR6 LSR5 LSR4 LSR3 LSR2 LSR1 LSR0 RTCRST Other resets Name Function LSR7 Error detection (FIFO mode) 1 : Parity error, framing error, or break is detected. 0 : No error LSR6 Transmit block empty...
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CHAPTER 19 SERIAL INTERFACE UNIT 1 (SIU1) LSR7 bit is valid only in FIFO mode, and it indicates always 0 in 16450 mode. The value of LSR4 bit becomes 1 when the spacing status (0) of receive data input is held longer than the time required for transmission of one word (start bit + data bits + parity bit + stop bit).
CHAPTER 19 SERIAL INTERFACE UNIT 1 (SIU1) 19.3.11 SIUMS_1 (0x0C00 0016) Name MSR7 MSR6 MSR5 MSR4 MSR3 MSR2 MSR1 MSR0 RTCRST Undefined Undefined Undefined Undefined Other resets Undefined Undefined Undefined Undefined Name Function MSR7 DCD1# signal status 1 : Low level 0 : High level MSR6 RI signal (internal) status...
CHAPTER 19 SERIAL INTERFACE UNIT 1 (SIU1) 19.3.14 SIUACTMSK_1 (0x0C00 001C) Name Reserved Reserved RxDMSK RTSMSK DCDMSK DTRMSK Reserved TxWRMSK RTCRST Other resets Name Function 7, 6 Reserved 0 is returned when read RxDMSK Mask for notification of change on RxD1 1 : Mask 0 : Unmask RTSMSK...
CHAPTER 19 SERIAL INTERFACE UNIT 1 (SIU1) 19.3.15 SIUACTTMR_1 (0x0C00 001E) Name SIUTMO7 SIUTMO6 SIUTMO5 SIUTMO4 SIUTMO3 SIUTMO2 SIUTMO1 SIUTMO0 RTCRST Other resets Name Function 7 to 0 SIUTMO(7:0) SIU activity timeout period 11111111 : 255 x 30.5 µ s 11111110 : 254 x 30.5 µ...
CHAPTER 20 SERIAL INTERFACE UNIT 2 (SIU2) 20.1 General The SIU2 is a serial interface that conforms to the RS-232-C communication standard and is equipped with two one-channel interfaces, one for transmission and one for reception. This unit can be also used as an interface in the IrDA format by means of register setting.
CHAPTER 20 SERIAL INTERFACE UNIT 2 (SIU2) 20.3.4 SIUIE_2 (0x0C00 0001: LCR7 = 0) Name Reserved Reserved Reserved Reserved RTCRST Other resets Name Function 7 to 4 Reserved 0 is returned when read Modem status interrupt 1 : Enable 0 : Prohibit Receive status interrupt 1 : Enable 0 : Prohibit...
CHAPTER 20 SERIAL INTERFACE UNIT 2 (SIU2) 20.3.6 SIUIID_2 (0x0C00 0002: Read) Name IIR7 IIR6 Reserved Reserved IIR3 IIR2 IIR1 IIR0 RTCRST Other resets Name Function 7, 6 IIR(7:6) Becomes 11 when FCR0 bit = 1 5, 4 Reserved 0 is returned when read IIR3 Pending of the character timeout interrupt request (in FIFO mode) 1 : No pending...
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CHAPTER 20 SERIAL INTERFACE UNIT 2 (SIU2) Table 20-3. Interrupt Function SIUIID_2 register Interrupt set/reset function Note Bit 3 Bit 2 Bit 1 Priority level Interrupt type Interrupt source Interrupt reset control Highest (1st) Receive line Overrun error, parity error, framing error, Read line status register status or break...
CHAPTER 20 SERIAL INTERFACE UNIT 2 (SIU2) 20.3.7 SIUFC_2 (0x0C00 0002: Write) Name FCR7 FCR6 Reserved Reserved FCR3 FCR2 FCR1 FCR0 RTCRST Other resets Name Function 7, 6 FCR(7:6) Receive FIFO trigger level 11 : 14 bytes 10 : 8 bytes 01 : 4 bytes 00 : 0 bytes 5, 4...
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CHAPTER 20 SERIAL INTERFACE UNIT 2 (SIU2) • FIFO interrupt modes When receive FIFO is enabled and receive interrupt requests are enabled, receive interrupts can occur as described below. 1. When the FIFO is reached to the specified trigger level, a receive data ready interrupt request is notified to the CPU.
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CHAPTER 20 SERIAL INTERFACE UNIT 2 (SIU2) When transmit FIFO is enabled and transmit interrupts are enabled, transmit interrupt requests can occur as described below. 1. When the transmit FIFO becomes empty, a transmit holding register empty interrupt request occurs. This interrupt request is cleared when a character is written to the transmit holding register (from one to 16 characters can be written to the transmit FIFO during servicing of this interrupt), or when the SIUIID_2 register is read.
CHAPTER 20 SERIAL INTERFACE UNIT 2 (SIU2) 20.3.9 SIUMC_2 (0x0C00 0004) Name Reserved Reserved Reserved MCR4 MCR3 MCR2 MCR1 MCR0 RTCRST Other resets Name Function 7 to 5 Reserved 0 is returned when read MCR4 Use of diagnostic testing (local loopback) 1 : Enable 0 : Disable MCR3...
CHAPTER 20 SERIAL INTERFACE UNIT 2 (SIU2) 20.3.10 SIULS_2 (0x0C00 0005) Name LSR7 LSR6 LSR5 LSR4 LSR3 LSR2 LSR1 LSR0 RTCRST Other resets Name Function LSR7 Error detection (FIFO mode) 1 : Parity error, framing error, or break is detected. 0 : No error LSR6 Transmit block empty...
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CHAPTER 20 SERIAL INTERFACE UNIT 2 (SIU2) LSR7 bit is valid only in FIFO mode, and it indicates always 0 in 16450 mode. The value of LSR4 bit becomes 1 when the spacing status (0) of receive data input is held longer than the time required for transmission of one word (start bit + data bits + parity bit + stop bit).
CHAPTER 20 SERIAL INTERFACE UNIT 2 (SIU2) 20.3.11 SIUMS_2 (0x0C00 0006) Name MSR7 MSR6 MSR5 MSR4 MSR3 MSR2 MSR1 MSR0 RTCRST Undefined Undefined Undefined Undefined Other resets Undefined Undefined Undefined Undefined Name Function MSR7 DCD2# signal status 1 : Low level 0 : High level MSR6 RI signal (internal) status...
CHAPTER 20 SERIAL INTERFACE UNIT 2 (SIU2) 20.3.14 SIURESET_2 (0x0C00 0009) Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved RESET RTCRST Other resets Name Function 7 to 1 Reserved 0 is returned when read SIURESET SIU2 reset 1 : Reset 0 : Release reset This register is used to reset SIU2 forcibly.
CHAPTER 20 SERIAL INTERFACE UNIT 2 (SIU2) 20.3.16 SIUACTMSK_2 (0x0C00 000C) Name Reserved Reserved RxDMSK RTSMSK DCDMSK DTRMSK Reserved TxWRMSK RTCRST Other resets Name Function 7, 6 Reserved 0 is returned when read RxDMSK Mask for notification of change on RxD2 1 : Mask 0 : Unmask RTSMSK...
CHAPTER 20 SERIAL INTERFACE UNIT 2 (SIU2) 20.3.17 SIUACTTMR_2 (0x0C00 000E) Name SIUTMO7 SIUTMO6 SIUTMO5 SIUTMO4 SIUTMO3 SIUTMO2 SIUTMO1 SIUTMO0 RTCRST Other resets Name Function 7 to 0 SIUTMO(7:0) SIU activity timeout period 11111111 : 255 x 30.5 µ s 11111110 : 254 x 30.5 µ...
The LCD controller may be disabled to allow connection of an external LCDC with integrated frame buffer RAM such as NEC Electronics’ µ PD16661. When the internal LCD controller is disabled by setting the LCDGPMODE register in the GIU, the SHCLK, LOCLK, VPLCD, and VPBIAS pins are redefined as follows:...
CHAPTER 21 LCD CONTROLLER Table 21-2. Redefining LCD Interface Pins When LCD Controller Is Disabled Redefined function Default function LCDCS# SHCLK MEMCS16# LOCLK VPGPIO1 VPLCD VPGPIO0 VPBIAS 21.2 LCD Module Features • Resolutions Horizontal: Up to 320 pixels (the number of pixels must be multiplies of 8) Vertical: Up to 320 pixels Color:...
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CHAPTER 21 LCD CONTROLLER Figure 21-1. LCD Controller Block Diagram memory interface controller unit MGCLK LCD Controller MBAGP interface MGCLK Color Pixel Pixel FIFOs lookup packing modulation Data (8 bits) 256 x 18 slave palette registers interface Data Data (4 bits) (4 bits) Shift clock Data (4 bits)
CHAPTER 21 LCD CONTROLLER 21.3 LCD Controller Specification 21.3.1 Panel configuration and interface (1) View rectangle and horizontal/vertical blank Most parameters of the LCD controller are described using a coordinate system. The x coordinate increases as a point moves to the right. The y coordinate increases as a point moves down. The origin is (0, 0). The size of the bounding box is specified by Vtotal and Htotal.
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CHAPTER 21 LCD CONTROLLER (2) Load clock The edge positions of the load clock, LOCLK, are programmable. Each row in the rectangle specified with (0, 0) and (Htotal–1, Vvisible–1) must have two LOCLK edges. The remaining rows in the frame rectangle form the vertical blank.
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CHAPTER 21 LCD CONTROLLER (3) Frame clock The edge positions of the frame clock, FLM, are also programmable. There must be exactly two FLM edges inside the bounding box. The first FLM edge is defined by the FLMHS(7:0) bits of the FHSTARTREG register and the FLMS(8:0) bits of the FVSTARTREG register.
CHAPTER 21 LCD CONTROLLER (4) Shift clock The shift clock (SHCLK) edges can be programmed only indirectly. The SHCLK is also output in rows of the vertical blank if the DummyL bit of the VRVISIBREG register is 1. The position of SHCLK edges are controlled by the Panelcolor and PanDbus bits of the LCDCFGREG0 register.
CHAPTER 21 LCD CONTROLLER 21.3.3 Palette The Col(1:0) bits of the LCDCFGREG0 register indicate the desired color depth. If they are set to 0, then a monochrome image can be displayed on a monochrome panel. If they are set 1, then a 4-shade gray scale image can be displayed on a monochrome panel.
CHAPTER 21 LCD CONTROLLER 21.3.5 Panel power ON/OFF sequence Some panels use several power supplies, and these supplies and interface logic signals must be turn on or off in sequences specified by the manufacturers. The LCD controller has signals to control these power supplies. Each power supply is controlled via the VPBIAS or VPLCD pin.
CHAPTER 21 LCD CONTROLLER 21.3.6 Operation of LCD controller Figure 21-5. Monochrome Panel LOCLK (Output) SHCLK (Output) FPD3 W−4 W−4 (Output) FPD2 W−3 W−3 (Output) FPD1 W−2 W−2 (Output) FPD0 W−1 W−1 (Output) SHCLK x W/4 pulses Remark W: panel width (Hact(5:0) x 8) The polarity (order of rising and falling edges) of the LOCLK and the SHCLK are programmable via the LPPOL and SCLKPOL bits.
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CHAPTER 21 LCD CONTROLLER Figure 21-7. Load Clock (LOCLK) LOCLK (Output) TH−1 H−1 TH−1 Pixel row LOCLK x H pulses LOCLK x (TH−H) pulses Remark H: panel height (Vact) TH: panel height + dummy lines (Vtotal) Remark Dummy lines are inserted when needed. For example, some panels can display only 240 lines, but has 242 line cycles.
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CHAPTER 21 LCD CONTROLLER Figure 21-9. LCD Timing Parameters LOCLK (Output) (Output) SHCLK (Output) FPD(7:0) Invalid ... W−2, W−1 (Output) The polarity of the FLM is programmable through the FLMPOL bit. In this diagram the first edge is a rising edge. The two FLM edges are on the same row in this diagram, but they need not be.
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CHAPTER 21 LCD CONTROLLER Table 21-3. LCD Controller Parameters Symbol Definition gclk period This parameter is not one of the timing parameters, but all timing parameters is calculated based on this. gclk is controlled by the Pre-scal field. Tg = 1 / (frequency of gclk) Shift clock high level width Color: T1 = Tg x HpckH 4-bit bus monochrome: T1 = Tg x (HpckH + HpckL)
CHAPTER 21 LCD CONTROLLER 21.4.1 HRTOTALREG (0x0A00 0400) Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reset Name Htot7 Htot6 Htot5 Htot4 Htot3 Htot2 Htot1 Htot0 Reset Name Function 15 to 8 Reserved 0 is returned when read 7 to 0 Htot(7:0) Number of horizontal total columns.
CHAPTER 21 LCD CONTROLLER 21.4.3 LDCLKSTREG (0x0A00 0404) Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reset Name LCS7 LCS6 LCS5 LCS4 LCS3 LCS2 LCS1 LCS0 Reset Name Function 15 to 8 Reserved 0 is returned when read 7 to 0 LCS(7:0) X coordinate of the first edge of the LOCLK.
CHAPTER 21 LCD CONTROLLER 21.4.5 VRTOTALREG (0x0A00 0408) Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Vtot8 Reset Name Vtot7 Vtot6 Vtot5 Vtot4 Vtot3 Vtot2 Vtot1 Vtot0 Reset Name Function 15 to 9 Reserved 0 is returned when read 8 to 0 Vtot(8:0) Vertical total number of lines including vertical retrace period 21.4.6 VRVISIBREG (0x0A00 040A)
CHAPTER 21 LCD CONTROLLER 21.4.7 FVSTARTREG (0x0A00 040C) Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved FLMS8 Reset Name FLMS7 FLMS6 FLMS5 FLMS4 FLMS3 FLMS2 FLMS1 FLMS0 Reset Name Function 15 to 9 Reserved 0 is returned when read 8 to 0 FLMS(8:0) Y coordinate of the first FLM edge 21.4.8 FVENDREG (0x0A00 040E)
CHAPTER 21 LCD CONTROLLER 21.4.9 LCDCTRLREG (0x0A00 0410) Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reset Name FIFOC2 FIFOC1 FIFOC0 Reserved ContCkE LPPOL FLMPOL SCLKPOL Reset Name Function 15 to 8 Reserved 0 is returned when read 7 to 5 FIFOC(2:0) FIFO control.
CHAPTER 21 LCD CONTROLLER 21.4.11 LCDCFGREG0 (0x0A00 0414) Name MOD7 MOD6 MOD5 MOD4 MOD3 MOD2 MOD1 MOD0 Reset Name Softreset Reserved Pre-scal1 Pre-scal0 Col1 Col0 Panelcolor PanDbus Reset Name Function 15 to 8 MOD(7:0) LCD M signal configuration. These bits specify the number of lines between M toggles.
CHAPTER 21 LCD CONTROLLER 21.4.12 LCDCFGREG1 (0x0A00 0416) Name Reserved Reserved HpckL5 HpckL4 HpckL3 HpckL2 HpckL1 HpckL0 Reset Name Reserved Reserved HpckH5 HpckH4 HpckH3 HpckH2 HpckH1 HpckH0 Reset Name Function 15, 14 Reserved 0 is returned when read 13 to 8 HpckL(5:0) Number of gclk cycles for hpck low level width 7, 6...
CHAPTER 21 LCD CONTROLLER 21.4.17 FHSTARTREG (0x0A00 0424) Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reset Name FLMHS7 FLMHS6 FLMHS5 FLMHS4 FLMHS3 FLMHS2 FLMHS1 FLMHS0 Reset Name Function 15 to 8 Reserved 0 is returned when read 7 to 0 FLMHS(7:0) X coordinate of the first FLM edge.
CHAPTER 21 LCD CONTROLLER 21.4.19 PWRCONREG1 (0x0A00 0430) Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reset Name Reserved Reserved Reserved Biason4 Biason3 Biason2 Biason1 Biason0 Reset Name Function Reserved 0 is returned when read 14 to 5 Reserved Write 0 when write.
CHAPTER 21 LCD CONTROLLER 21.4.22 CPINDCTREG (0x0A00 047E) Name PalPage3 PalPage2 PalPage1 PalPage0 Reserved Reserved PalRDI PalWRI Reset Name PalIndex7 PalIndex6 PalIndex5 PalIndex4 PalIndex3 PalIndex2 PalIndex1 PalIndex0 Reset Name Function 15 to 12 PalPage(3:0) Palette page select used in 4 bpp mode 11, 10 Reserved 0 is returned when read...
CHAPTER 22 PLL PASSIVE COMPONENTS The V 4181 requires several external passive components for proper operation, which are connected to VDD_PLL as illustrated in Figure 22-1. Figure 22-1. Example of Connection of PLL Passive Components VDD_LOGIC VDD_PLL 4181 GND_PLL GND_LOGIC Remarks 1.
CHAPTER 23 COPROCESSOR 0 HAZARDS The V 4110 CPU core avoids contention of its internal resources by causing a pipeline interlock in such cases as when the contents of the destination register of an instruction are used as a source in the succeeding instruction. Therefore, instructions such as NOP must not be inserted between instructions.
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CHAPTER 23 COPROCESSOR 0 HAZARDS Table 23-1. Coprocessor 0 Hazards Operation Source Destination Source name No. of Destination name No. of cycles cycles − MTC0 CPU general-purpose register − MFC0 CPU general-purpose register TLBR Index, TLB PageMask, EntryHi, EntryLo0, EntryLo1 TLBWI Index or Random, PageMask, TLBWR...
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CHAPTER 23 COPROCESSOR 0 HAZARDS Cautions 1. If the setting of the K0 bit in the Config register is changed by executing an MTC0 instruction within the kseg0 or ckseg0 area, the change is reflected one to three instructions later from the MTC0 instruction.
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CHAPTER 23 COPROCESSOR 0 HAZARDS (8) CACHE Index Store Tag Source: The confirmation of registers containing information necessary for executing this instruction. (9) Coprocessor usable test Source: The confirmation of modes set by the bits of the CP0 registers in the “Source” column. Examples 1.
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CHAPTER 23 COPROCESSOR 0 HAZARDS Table 23-2 indicates examples of calculation. Table 23-2. Calculation Example of CP0 Hazard and Number of Instructions Inserted Contending Number of Destination Source internal instructions Formula resource inserted TLBWR/TLBWI TLBP TLB Entry 5 – (2 + 1) TLBWR/TLBWI Load or store using newly modified TLB TLB Entry...
APPENDIX A RESTRICTIONS ON V 4181 A.1 RSTSW# During HALTimer Operation The V 4181 ignores the RSTSW# signal even if it is asserted while the HALTimer is operating (counting). If the 4181 is started while the RSTSW# signal is low, the RSTSW reset sequence is not executed and the V 4181 continues operating until the HALTimer is reset.
APPENDIX A RESTRICTIONS ON V 4181 A.2 RSTSW# in Hibernate Mode The V 4181 may release the self-refresh mode of DRAM when the RSTSW# signal is asserted in the Hibernate mode. As a result, the DRAM data may be lost. (1) With EDO DRAM When the RSTSW# signal goes low, the RAS# and CAS# signals go high and the self-refresh mode is released.
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APPENDIX A RESTRICTIONS ON V 4181 (2) With SDRAM When the RSTSW# signal goes low, the CLKEN (CKE) signal goes high. While the CLKEN signal is high, the self-refresh mode of SDRAM may be released. However, because the SDCLK signal is kept low, this problem does not occur in SDRAM that requires the rising edge of the SDCLK signal to release the self-refresh mode.