LG CED-8042B Manual page 14

• Pin Description
Pin No. Symbol
2 SE I
3 FE I
4 VC I
5 VPCO1 O
6 VPCO2 O
7 VCTL I
8 FILO O
9 FILI I
10 PCO O
11 CLTV I
12 A V 1
SS
13 RFAC I
14 BIAS I
15 ASYI I
16 ASYO O
17 A V 1
DD
22 D V 1
DD
23 D V 1
SS
24 ASYE I
25 PSSL I
26 WDCK O
27 LRCK O
28 LRCKI I
29 DA16 O
30 PCMDI I
31 DA15 O
32 BCKI I
33 DA14 O
34 DA13 O
35 DA12 O
38 DA11 O
39 DA10 O
40 DA09 O
I/O
Slide Error input
Focus Error input
Center voltage input
1, Z, 0 Output of VCO2 charge pump for vari-pitch EFM PLL
1, Z, 0 Output 2 of VCO2 charge pump for vari-pitch EFM PLL
ON/OFF switching by Command £§E
Input of VCO2 control voltage for vari-pitch EFM PLL
Analog Output of Filter for master PLL (slave = digital PLL)
Input of filter for master PLL
1, Z, 0 Output of charge pump for master PLL
VCO control voltage lnput
Analog GND
EFM signal input
Asymmetry circuit constant current input
Asymmetry comparator circuit voltage input
1, 0 EFM full-swing output (L=V
Analog power supply
Digital power supply
Digital GND
Asymmetry circuit ON/OFF (L=OFF, H=ON)
Input used to switch the audio data output mode. (L=serial, H=parallel)
1, 0 D/A interface for 48-bit slot. Word clock f=2Fs
1, 0 D/A interface for 48-bit slot. LR clock f=Fs
LR clock input to DAC (48-bit slot)
1, 0 Outputs DA16 (MSB) when PSSL=1, or serial data output from the 48-bit slot (2's
complements, MSB first) when PSSL=0.
Audio data input to DAC (48-bit slot)
1, 0 Outputs DA15 when PSSL=1, or bit clock output from the 48-bit slot when PSSL=0.
Bit clock input to DAC (48-bit slot)
1, 0 Outputs DA14 when PSSL=1, or serial data output from the 64-bit slot (2's
complements, LSB first) when PSSL=0.
1, 0 Outputs DA13 when PSSL=1, or bit clock output from the 64-bit slot when PSSL=0.
1, 0 Outputs DA12 when PSSL=1, or LR clock output from the 64-bit slot when PSSL=0.
1, 0 Outputs DA11 when PSSL=1, or GTOP when PSSL=0.
1, 0 Outputs DA10 when PSSL=1, or XUGF when PSSL=0.
1, 0 Outputs DA9 when PSSL=1, or XPLCK when PSSL=0.
Description
, H=V )
SS DD
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