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EN 130
9.
EM5A NTSC
9.11 Synchronization (Diagram B2, B3 & B4)
The HIP video processor provides the vertical and horizontal
sync pulses V
and H
A50
incoming CVBS signal. These pulses are then fed to the
PICNIC, where they are doubled to be synchronous with the
120 Hz picture. The outgoing pulses, V
to the HOP, which supplies the vertical and horizontal drive
pulses.
9.12 Horizontal (Line) Deflection (Diagram A3)
9.12.1 Principle
T ON
T OFF
T7421 conducting
3406
2492
LINEDRIVE 1
(HOP)
6406
EW_DRIVE
(HOP)
The HOP (located on the SSB) generates the line-drive pulses
(LINEDRIVE1), which have a frequency of 31468 Hz (T = 31,77
s.)
When the LINEDRIVE1 signal is high, TS7409 and TS7408 will
conduct. A constant DC voltage will be applied across L5410,
causing a linearly increasing current through this coil. The
secondary voltage of L5410 has a negative polarity so that
TS7421 will block.
When the set is switched 'on,' the current through L5410 is
supplied by the 5V2 Standby supply (via D6407), and taken
over by the +11D voltage (via D6408) of the main supply.
When the LINEDRIVE1 signal becomes low, TS7409 and
TS7408 will block. The voltage polarity across the primary
winding of L5410 will invert. The positive voltage on the
secondary winding will now drive TS7421 into conductivity.
Because of the storage time of the line transistor (TS7421),
Circuit Descriptions and Abbreviation List
. They are synchronized with the
A50
and H
, are fed
D100
D100
COLD
6408
MAIN SUPPLY +11D
STANDBY SUPPLY +5V2
6407
3416
3411
2412
2414
7409
3414
7408
2415
3407
3404
3486
3412
1
7450-B
3
5
8
6
4
3490
6615
2
3487
Figure 9-18 Line deflection circuitry
The V
D100
V
signal. The OTC is synchronized on the HFB pulse from the
D
CRT and on the V
of CC/OSD/EPG.
When no CVBS is offered to the video processor, the HIP
switches 'off' the V
generated by the PICNIC (to assure a stable OSD.)
HOT
141V
3409
5410
5411
2417
3417
141V
3488
+8VS
3418
3492
+8VB
3484
3481
7486
7487
1
5
3483
7482
2
4
L5410 cannot transfer its energy immediately to the secondary
side. This may result in high voltage peaks on the collector of
TS7409 and TS7408. To prevent these peaks from damaging
the transistors, a 'snubber' circuit (C2414, C2412 and R3411)
will suppress them.
When the LINEDRIVE1 signal is high again, the sequence
described above starts again. Circuit L5411 and R3409 will
increase the switch 'off' time of the line transistor.
The line stage is started via a 'slow start' principle. During start-
up, the HOP generates line drive pulses with a small TON and
a high frequency (50 kHz.) T
gradually increased until the frequency is 31468 Hz (normal
condition.)
The time interval from start to normal condition takes about 150
ms.
pulse from the PICNIC is inverted by TS7304 to the
from the HOP, for the synchronization
SYNC
and H
pulses, and the pulses are
A50
A50
Linearity Correction
*1
5
S-correction
*2
5430
X
Y
X
X > Y
1
Deflection centre
7421
2420
2425
6423
2421
2
4
3
1
6480
2426
6422
7480
ARC
PROT
3479
CL 26532041_077.eps
is constant and T
OFF
Caused by
serial losses in
the line output stage
LINE
1417
1
DEFL. COIL.
2
2430
LINEARITY
3431
COIL.
(*1)
5421
2431
2433
(*2)
5422
170402
is
ON
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