Panasonic KX-NS500AG Service Manual page 106

KX-NS500AG
Pin No Pin Name
R4 VCC(IO)
R5 HCK_CPU
R6 DHW_CPU
R7 UHW_CPU
R8 VCCINT
R9 GND
R10 VCCINT
R11 GND
R12 VCCINT
R13 GND
R14 CDC_DO
R15 CDC_CK_O
R16 NC
R17 NIRQ_EXT_I[1]
R18 HWCLK[2]
R19 HWCLK[3]
R20 NCS_BASE_O
R21 HWCLK[6]
R22 HWCLK[5]
T1 CLK24M
T2 GND+
T3 GPIO0[1]
T4 HWCLK[7]
T5 NC
T6 VCCA
T7 FSYNC[7]
T8 MC_UHW_O[3]
T9 NETREF_I[3]
T10 NETREF_I[2]
T11 MC_DHW_O[0]
T12 NC
T13 NC
T14 NC
T15 CDC_CS_O
T16 CDC_DI
T17 PT_TXB_O[1]
T18 PT_TXB_O[0]
T19 VCC(IO)
T20 GND
T21 GND+
T22 GND+
U1 NRST_I
U2 NIRQ_O[1]
U3 GND
U4 VCC(IO)
U5 GNDA
U6 VCC(PLL)
U7 NC
U8 NC
U9 MC_DHW_O[3]
U10 NC
U11 NC
U12 NC
U13 NC
U14 UHW_RMT
U15 NC
U16 NC
U17 NC
U18 VCCA
U19 PT_RXA_I[1]
U20 PT_RXA_I[0]
U21 HWCLK[1]
U22 HWCLK[0]
V1 NC
V2 NC
V3 NC
V4 NC
I/O Function
- VCC
- (reserved)
O DOWN high way to CPU
I UP High way from CPU
- VCC
- GND
- VCC
- GND
- VCC
- GND
O RMT card CODEC data
O RMT card CODEC clock
- No Connection
I IRQ from BASE card
O High Way clock output
O High Way clock output
O BASE card CPU bus chip select
O High Way clock output
O High Way clock output
I CPU clock(24MHz)
I GND
I/O SERIAL DSR
O High Way clock output
- No Connection
- VCC
O frame sync output
I UP High Way from EXP card
I NETREF from EXP card
I NETREF from EXP card
O DOWN High Way to EXP card
- No Connection
- No Connection
- No Connection
O RMT card CODEC chip select
I RMT card CODEC data
O DPT#0 output data
O DPT#0 output data
- VCC
- GND
I GND
I GND
I FPGA reset
O INT(FPGA#1)
- GND
- VCC
- GND
- VCC
- No Connection
- No Connection
O DOWN High Way to EXP card
- No Connection
- No Connection
- No Connection
- No Connection
I UP High Way from RMT card
- No Connection
- No Connection
- No Connection
- VCC
I DPT#0 data input
I DPT#0 data input
O High Way clock output
O High Way clock output
- No Connection
- No Connection
- No Connection
- No Connection
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