Page 1 SH7095 Hardware User Manual...
Page 2 Hitachi’s permission. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user’s unit according to this document.
Page 3: Table Of Contents
Contents Section 1 Overview and Pin Functions ............. SH7095 Features..................... 1.1.1 Features of the SH7095 ................. Block Diagram....................Description of Pins ..................1.3.1 Pin Arrangement .................. 1.3.2 Pin Functions..................Section 2 CPU ....................Register Configuration ..................2.1.1 General Registers .................
Page 4 4.1.1 Types of Exception Processing and Priority Order........53 4.1.2 Exception Processing Operations ............. 54 4.1.3 Exception Processing Vector Table ............55 Resets......................57 4.2.1 Types of Resets ..................57 4.2.2 Power-On Reset ................... 57 4.2.3 Manual Reset..................58 Address Errors ....................59 4.3.1 Sources of Address Errors ..............
Page 5 5.3.2 Interrupt Priority Level Setting Register B (IPRB) ........5.3.3 Vector Number Setting Register WDT (VCRWDT) ........5.3.4 Vector Number Setting Register A (VCRA) ..........5.3.5 Vector Number Setting Register B (VCRB)..........5.3.6 Vector Number Setting Register C (VCRC)..........5.3.7 Vector Number Setting Register D (VCRD) ..........
Page 6 7.1.3 Pin Configuration ................. 120 7.1.4 Register Configuration................121 7.1.5 Address Map ..................122 Description of Registers..................124 7.2.1 Bus Control Register 1 (BCR1) ............... 124 7.2.2 Bus Control Register 2 (BCR2) ............... 126 7.2.3 Wait Control Register (WCR) ..............128 7.2.4 Individual Memory Control Register (MCR)..........
Page 7 Waits between Access Cycles ................190 7.10 Bus Arbitration ....................191 7.10.1 Master Mode ..................193 7.10.2 Slave Mode..................195 7.10.3 Partial-Share Master Mode..............196 7.10.4 External Bus Address Monitor ..............199 7.10.5 Master and Slave Coordination ............... 199 7.11 Other Topics....................200 7.11.1 Resets ....................
Page 8 9.2.4 DMA Channel Control Registers 0 and 1 (CHCR0 and CHCR1)....227 9.2.5 DMA Vector Number Registers 0 and 1 (VCRDMA0, VCRDMA1)....231 9.2.6 DMA Request/Response Selection Control Registers 0 and 1 (DRCR0, DRCR1)................232 9.2.7 DMA Operation Register (DMAOR)............233 Operation .......................
Page 9 11.1.4 Register Configuration ................287 11.2 Register Descriptions ..................288 11.2.1 Free-Running Counter (FRC)..............288 11.2.2 Output Compare Registers A and B (OCRA and OCRB)......288 11.2.3 Input Capture Register (ICR) ..............289 11.2.4 Timer Interrupt Enable Register (TIER)............ 289 11.2.5 Free-Running Timer Control/Status Register (FTCSR) ........
Page 10 12.4.4 System Reset With WDTOVF..............321 12.4.5 Internal Reset With the Watchdog Timer........... 321 Section 13 Serial Communication Interface ............323 13.1 Overview ....................... 323 13.1.1 Features ....................323 13.1.2 Block Diagram..................324 13.1.3 Pin Configuration ................. 324 13.1.4 Register Configuration................325 13.2 Register Descriptions..................
Page 11 14.5.2 Clearing the Module Standby Function............. 383 Section 15 Electrical Characteristics ..............385 15.1 Absolute Maximum Ratings ................385 15.2 DC Characteristics................... 386 15.3 AC Characteristics................... 388 15.3.1 Clock Timing ..................388 15.3.2 Control Signal Timing................392 15.3.3 Bus Timing ..................398 15.3.4 DMAC Timing ..................
Page 12: Section 1 Overview And Pin Functions
Section 1 Overview and Pin Functions SH7095 Features The SH7095 is a family of new generation single-chip RISC microprocessors that integrate a Hitachi-original CPU, a multiplier, cache memory, and peripheral functions required for system configuration. The CPU features a RISC-type instruction set. Most instructions can be executed in one clock cycle, which greatly improves instruction execution speed.
Page 13 Generates an interrupt when the CPU or DMAC generates an address, data, and controller (UBC) a bus cycle with specified conditions (address, data, CPU/peripheral cycle, instruction fetch/data access, read/write, byte/word/longword access) • Simplifies configuration of a self-debugger Clock/Phase Locked Loop (PLL): • Built-in clock pulse generator 2 Hitachi...
Page 14 Write-through type of writing data • LRU replacement algorithm • 2 kbytes of the cache can be used as 2-kbyte internal RAM Direct Memory Access Controller (DMAC) (2 Channels): • Permits DMA transfer between external memory, external I/O, on-chip peripheral modules Hitachi 3...
Page 15 Serial Communication Interface (SCI) (1 Channel): • Asynchronous or clocked synchronous mode is selectable • Simultaneous transmit and receive (full duplex) • On-chip baud rate generator in each channel • Multiprocessor communication function Package: • 144-pin plastic QFP (FP-144A) 4 Hitachi...
Page 16: Block Diagram
Block Diagram Figure 1.1 is a block diagram of the SH7095. Figure 1.1 Block Diagram Hitachi 5...
Page 17: Description Of Pins
Description of Pins 1.3.1 Pin Arrangement Note: Do not connect anything to pins labeled N.C Figure 1.2 Pin Arrangement (144-Pin Plastic QFP) 6 Hitachi...
Page 18: Pin Functions
1.3.2 Pin Functions Table 1.2 shows the pin functions of the SH7095. Table 1.1 Pin Functions Pin No. Pin Name Pin Description Data bus Data bus Data bus Power Data bus Ground Data bus Data bus Data bus Data bus...
Page 19 Address bus Power Address bus Ground Address bus Address bus Address bus Address bus Address bus Power Address bus Ground Address bus Address bus Address bus Power Address bus Ground Address bus Address bus Address bus Power Address bus 8 Hitachi...
Page 20 CASHL/DQMUL/WE2 Third byte selection signal for memory CASLH/DQMLU/WE1 Power Least significant byte selection signal for CASLL/DQMLL/WE0 memory Ground Read pulse Synchronous DRAM clock enable control Hardware wait request WAIT — Reserved pin (do not connect anything to it) Hitachi 9...
Page 21 Clock pause acknowledge output CKPACK Clock pause request input CKPREQ/CKM Power EXTAL Pin for connecting clock pulse generator Ground XTAL Pin for connecting clock pulse generator Operating mode pin CKIO System clock input/output Operating mode pin Operating mode pin 10 Hitachi...
Page 22 External interrupt source input External interrupt source input IRL1 External interrupt source input IRL0 Data bus Data bus Power Data bus Ground Data bus Data bus Data bus Data bus Power Data bus Ground Data bus Data bus Data bus Hitachi 11...
Page 23 12 Hitachi...
Page 24: Section 2 Cpu
R0 functions as an index register in the indirect indexed register addressing mode and indirect indexed GBR addressing mode. In some instructions, R0 functions as a fixed source register or destination register. R15 functions as a hardware stack pointer (SP) during exception processing. Figure 2.1 General Registers Hitachi 13...
Page 25: Control Registers
System registers consist of four 32-bit registers: high and low multiply and accumulate registers (MACH and MACL), the procedure register (PR), and the program counter (PC) (figure 2.3). The multiply and accumulate registers store the results of multiply and accumulate operations. The Hitachi 14...
Page 26: Initial Values Of Registers
Data Format in Registers Register operands are always longwords (32 bits) (figure 2.4). When the memory operand is only a byte (8 bits) or a word (16 bits), it is sign-extended into a longword when loaded into a register. Hitachi 15...
Page 27: Data Format In Registers
Consequently, AND instructions with immediate data always clear the upper 24 bits of the destination register. Word or longword immediate data is not located in the instruction code: it is stored in a memory table. An immediate data transfer instruction (MOV) accesses the memory table using the PC Hitachi 16...
Page 28: Immediate Data Format
(table 2.2). Immediate data is sign-extended for arithmetic operations or zero-extended for logic operations. It also is handled as longword data. Table 2.2 Sign Extension of Word Data SH7095 Series CPU Description Example of Conventional CPU Data is sign-extended to 32 MOV.W...
Page 29 T bit in the status register is kept to a minimum to improve the processing speed. Table 2.4 T Bit SH7095 Series CPU Description Example of Conventional CPU T bit is set when R0 ≥ R1. The...
Page 30: Addressing Modes
(table 2.6). Table 2.6 Absolute Address Accessing Classification SH7095 Series CPU Example of Conventional CPU Absolute address MOV.L @(disp,PC),R1 MOV.B @H'12345678,R0 MOV.B @R1,R0 ....
Page 31 Rn. 1 is subtracted for a addressing byte operation, 2 for a word operation, and 4 for a Word: Rn – 2 longword operation. → Longword: → Rn – 4 (Instruction executed with Rn after calculation) Hitachi 20...
Page 32 × 2 quadrupled for a longword operation. Longword: GBR + disp × Indirect indexed @(R0, GBR) The effective address is the GBR value plus the R0. GBR + R0 GBR addressing Hitachi 21...
Page 33 8-bit displacement (disp), doubled, and added to the PC value. disp:12 The effective address is the PC value sign-extended PC + disp × 2 with a 12-bit displacement (disp), doubled, and added to the PC value. Hitachi 22...
Page 34: Instruction Format
The instruction format table, table 2.9, refers to the source operand and the destination operand. The meaning of the operand depends on the instruction code. The symbols are used as follows: • xxxx: Instruction code • mmmm: Source register • nnnn: Destination register • iiii: Immediate data • dddd: Displacement Hitachi 23...
Page 35 Indirect pre- STC.L SR,@-Rn system register decrement register — nnnn: PC relative BRAF using Rn m format mmmm: Direct registerControl register or Rm,SR system register mmmm: Indirect post- Control register or LDC.L @Rm+,SR increment register system register Hitachi 24...
Page 36 R0 (Direct register) MOV.B register with @(disp,Rn),R0 displacement nd4 format R0 (Direct register) nnnndddd: Indirect MOV.B register with R0,@(disp,Rn) displacement nmd format mmmm: Direct registernnnndddd: Indirect MOV.L register with Rm,@(disp,Rn) displacement mmmmdddd: Indirect nnnn: Direct registerMOV.L register with @(disp,Rm),Rn displacement Hitachi 25...
Page 37 Indirect indexed iiiiiiii: AND.B Immediate #imm,@(R0,GBR) R0 (Direct register) AND iiiiiiii: #imm,R0 Immediate — iiiiiiii: TRAPA #imm Immediate ni format nnnn: Direct registerADD iiiiiiii: #imm,Rn Immediate Note: In multiply/accumulate instructions, nnnn is the source register. Hitachi 26...
Page 38: Instruction Set
Decrement and test EXTS Sign extension EXTU Zero extension Multiply/accumulate, double-length multiply/accumulate operation Double-length multiplication MULS Signed multiplication MULU Unsigned multiplication Negation NEGC Negation with borrow Binary subtraction SUBC Binary subtraction with borrow SUBV Binary subtraction with underflow check Hitachi 27...
Page 39 Conditional branch, conditional branch with delay (T = 0) Conditional branch, conditional branch with delay (T = 1) Unconditional branch BRAF Unconditional branch Branch to subroutine procedure BSRF Branch to subroutine procedure Unconditional branch Branch to subroutine procedure Return from subroutine procedure Hitachi 28...
Page 40 (memory → register) is the same as the register used by the next instruction. Hitachi 29...
Page 41 • The destination register of the load instruction (memory → register) and the register used by the next instruction are the same. 2. Depending on the operand size, displacement is scaled ×1, ×2, or ×3. For details, see the SH7000/SH7600 series programming manual. Hitachi 30...
Page 42 (disp × 4 + Rm) → Rn — MOV.L @(disp,Rm),Rn 0101nnnnmmmmdddd Rm → (R0 + Rn) — MOV.B Rm,@(R0,Rn) 0000nnnnmmmm0100 Rm → (R0 + Rn) — MOV.W Rm,@(R0,Rn) 0000nnnnmmmm0101 Rm → (R0 + Rn) — MOV.L Rm,@(R0,Rn) 0000nnnnmmmm0110 Hitachi 31...
Page 43 0000nnnn00101001 Rm → Swap the bottom — SWAP.B Rm,Rn 0110nnnnmmmm1000 two bytes → Rn Rm → Swap two — SWAP.W Rm,Rn 0110nnnnmmmm1001 consecutive words → Rn Rm: Middle 32 bits of — XTRCT Rm,Rn 0010nnnnmmmm1101 Rn → Rn Hitachi 32...
Page 44 0010nnnnmmmm0111 MSB of Rm → M, result M ^ Q → T 0 → M/Q/T DIV0U 0000000000011001 Signed operation of 2 to 4 — DMULS.L Rm,Rn 0011nnnnmmmm1101 Rn × Rm → MACH, MACL 32 × 32 → 64 Hitachi 33...
Page 45 × 16 → 32 bit Unsigned operation 1 to 3 — MULU.W Rm,Rn 0010nnnnmmmm1110 of Rn × Rm → MAC 16 × 16 → 32 bit 0–Rm → Rn — Rm,Rn 0110nnnnmmmm1011 0–Rm–T → Rn, Borrow NEGC Rm,Rn 0110nnnnmmmm1010 Borrow → T Hitachi 34...
Page 46 #imm,@(R0,GBR) 11001100iiiiiiii result is 0, 1 → T result Rn ^ Rm → Rn — Rm,Rn 0010nnnnmmmm1010 R0 ^ imm → R0 — #imm,R0 11001010iiiiiiii (R0 + GBR) ^ imm → — XOR.B #imm,@(R0,GBR) 11001110iiiiiiii (R0 + GBR) Hitachi 35...
Page 47 Rn<<2 → Rn — SHLL2 0100nnnn00001000 Rn>>2 → Rn — SHLR2 0100nnnn00001001 Rn<<8 → Rn — SHLL8 0100nnnn00011000 Rn>>8 → Rn — SHLR8 0100nnnn00011001 Rn<<16 → Rn — SHLL16 Rn 0100nnnn00101000 Rn>>16 → Rn — SHLR16 Rn 0100nnnn00101001 Hitachi 36...
Page 48 0000nnnn00000011 Rn + PC → PC Delayed branch, Rn → PC — 0100nnnn00101011 Delayed branch, PC → PR, — 0100nnnn00001011 Rn → PC Delayed branch, PR → PC — 0000000000001011 Note: One state when it does not branch. Hitachi 37...
Page 49 GBR,Rn 0000nnnn00010010 VBR → Rn — VBR,Rn 0000nnnn00100010 Rn–4 → Rn, SR → (Rn) — STC.L SR,@–Rn 0100nnnn00000011 Rn–4 → Rn, GBR → (Rn) — STC.L GBR,@–Rn 0100nnnn00010011 Rn–4 → Rn, VBR → (Rn) — STC.L VBR,@–Rn 0100nnnn00100011 Hitachi 38...
Page 50 • Contention occurs between instruction fetch and data access • The destination register of the load instruction (memory → register) and the register used by the next instruction are the same. Hitachi 39...
Page 51: Operation Code Map
01MD DIV1 Rm,Rn DMULU.L Rm,Rn CMP/HI Rm,Rn CMP/GT Rm,Rn 0011 Rn 10MD SUB Rm,Rn SUBC Rm,Rn SUBV Rm,Rn 0011 Rn 11MD ADD Rm,Rn DMULS.L Rm,Rn ADDC Rm,Rn ADDV Rm,Rn 0100 Rn 0000 SHLL Rn DT Rn SHAL Rn Hitachi 40...
Page 52 NEGC Rm,Rn NEG Rm,Rn 0110 Rn 11MD EXTU.B Rm,Rn EXTU.W Rm,Rn EXTS.B Rm,Rn EXTS.W Rm,Rn 0111 Rn ADD #imm:8,Rn 1000 00MD Rn disp MOV.B R0, MOV.W R0, @(disp:4,Rn) @(disp:4,Rn) 1000 01MD Rm disp MOV.B MOV.W @(disp:4, @(disp:4, Rm),R0 Rm),R0 Hitachi 41...
Page 53: Processing States
State Transitions The CPU has five processing states: reset, exception processing, bus release, program execution, and power-down. Figure 2.6 shows the transitions between the states. See section 14, Power- Down Mode, for more information on the power-down mode. Hitachi 42...
Page 54 Reset State: The CPU resets in the reset state. This occurs when the RES pin level goes low. When the NMI pin is high, the result is a power-on reset; when it is low, a manual reset will occur. Hitachi 43...
Page 55: Power-Down State
For NMI interrupts, the CPU returns to ordinary program execution state through the exception processing state after the oscillator Hitachi 44...
Page 56 MAC.L, MAC.W, MUL.L, MULS, and MULU instructions (all of which are multiplication instruction) or any instructions that access the MACH and MACL registers (CLRMAC, LDS MACH/MACL, STS MACH/MACL). When module standby functions of DMAC are used, set the DMA master enable bit in the DMAC to 0. Hitachi 45...
Page 57 MSTP0 bits (MULT to affected MSTP 4–0 function of SBYCR module is of SBYCR (SH7095 set to 1 halted. halted and to 0 only) module initialized. Notes: 1. Differs depending on peripheral module and pin. 2. The DMAC, MULT, DIV registers and the specified interrupt vectors maintain their settings.
Page 58: Section 3 Operating Mode
Operating Mode of the On-chip Clock Pulse Generator 3.1.1 Clock Pulse Generator The block diagram of the on-chip clock pulse generator is shown in figure 3.1. Figure 3.1 Block Diagram of Clock Pulse Generator Hitachi 47...
Page 59 LSI affects the interface margin with peripheral devices. The on-chip PLL circuit 1 synchronizes external clocks with clocks provided into the LSI. The PLL circuit 1 can also make the phase difference between the clocks 90 degrees, enabling high-speed interface with SDRAM. 48 Hitachi...
Page 60: Clock Operating Mode
When one of clock modes 4 to 6 is selected, the clock pause function can modify the frequency of clocks input from the CKIO pin or can stop the sending of clock signals. When setting clock modes 4—6, the PLL circuit stops. Hitachi 49...
Page 61: Bus Width Of The Cs0 Area
3.3. Do not switch the MD4 and MD3 pins while they are operating. Switching them will cause operating errors. Table 3.3 Bus Width of the CS0 Area Function 8-bit bus width is selected. 16-bit bus width is selected. 32-bit bus width is selected. Illegal setting 50 Hitachi...
Page 62: Switching Between Master And Slave Modes
See section 7, Bus State Controller, for more information about the master and slave modes. Table 3.4 Switching between the Master and Slave Modes Operating Mode Level applied Slave mode Master mode Cache Control Register See section 8, Cache. Hitachi 51...
Page 63 52 Hitachi...
Page 64: Section 4 Exception Processing
PC Notes: 1. Delay branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, BRAF. 2. Instructions that rewrite the PC: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA, BF/S, BT/S, BSRF, BRAF. Hitachi 53...
Page 65: Exception Processing Operations
SR’s interrupt mask bits (I3–I0). For address error and instruction exception processing, the I3–I0 bits are not affected. The start address is then fetched from the exception processing vector table and the program begins running from that address. 54 Hitachi...
Page 66: Exception Processing Vector Table
× 4) (Reserved by system) H'00000014–H'00000017 Slot illegal instruction H'00000018–H'0000001B (Reserved by system) H'0000001C–H'0000001F H'00000020–H'00000023 CPU address error H'00000024–H'00000027 DMA address error H'00000028–H'0000002B Interrupts H'0000002C–H'0000002F User break H'00000030–H'00000033 (Reserved by system) H'00000034–H'00000037 H'0000007C–H'0000007F Trap instruction (user vector) H'00000080–H'00000083 H'000000FC–H'000000FF Hitachi 55...
Page 67 5, Interrupt Controller, and table 5.4, Interrupt Exception Processing Vectors and Priorities. 4. Vector numbers are set in the on-chip vector number register. See section 5.3, Description of Registers, section 9, Direct Memory Access Controller, and section 10, Division Unit, for more information. 56 Hitachi...
Page 68: Resets
(when the PLL circuit is halted) or for 20 clock cycles (when the PLL circuit is running). During power-on reset, CPU internal status and all registers of on-chip peripheral modules are initialized. See appendix A, Pin States, for the status of individual pins during the power-on reset status. Hitachi 57...
Page 69: Manual Reset
In the manual reset status, manual reset exception processing starts when the NMI pin is kept low and the RES pin is first kept low for a set period of time and then returned to high. The CPU will then operate the same as described for power-on resets. 58 Hitachi...
Page 70: Address Errors
Word or byte data accessed in on-chip peripheral None (normal) module space at addresses H'FFFFFE00 to H'FFFFFEFF Notes: 1. Address errors do not occur during the synchronous DRAM mode register write cycle. 2. 16-byte DMAC transfers use longword accesses. Hitachi 59...
Page 71: Address Error Exception Processing
Number of Sources NMI pin (external input) User break User break controller IRL0–IRL15 (external input) On-chip peripheral module Direct memory access controller (DMAC) Division Serial communications interface (SCI) A/D converter Free running timer Watchdog timer (WDT) Bus state controller (BSC) 60 Hitachi...
Page 72: Interrupt Priority Level
I3–I0 is H'F (level 15). Next, the start address of the exception service routine is fetched from the exception processing vector table for the accepted interrupt, that address is jumped to and execution begins. For more information about interrupt exception processing, see section 5.4, Interrupt Operation. Hitachi 61...
Page 73: Exceptions Triggered By Instructions
The exception service routine start address is fetched from the exception processing vector table that corresponds to the vector number specified in the TRAPA instruction. That address is jumped to and the program starts executing. The jump that occurs is not a delay branch. 62 Hitachi...
Page 74: Illegal Slot Instructions
Not accepted Not accepted Immediately after an interrupt-disabled instruction Accepted Not accepted Notes: 1. Delay branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, BRAF 2. Interrupt-disabled instructions: LDC, LDC.L, STC, STC.L, LDS, LDS.L, STS, STS.L Hitachi 63...
Page 75: Immediately After A Delay Branch Instruction
General illegal instruction SP → Start address of illegal instruction 32 bits 32 bits SP → Address of instruction after executed instruction Interrupt 32 bits 32 bits SP → Jump destination address of delay branch instruction Illegal slot instruction 32 bits 32 bits 64 Hitachi...
Page 76: Notes On Use
This means the write data stacked will be undefined. 4.8.4 Accessing Registers during a Manual Reset Do not enter a manual reset during accesses of the bus state controller (BSC) or user break controller (UBC) or else write errors may result. Hitachi 65...
Page 77 66 Hitachi...
Page 78: Section 5 Interrupt Controller (Intc)
5.1.2 Block Diagram Figure 5.1 is a block diagram of the INTC. Hitachi 67...
Page 79 A and B FRT: Free-running timer VCRWDT: Vector number setting register WDT SCI: Serial communications interface VCRA–D: Vector number setting registers A–D WDT: Watchdog timer Status register REF: Refresh request within bus state controller Figure 5.1 INTC Block Diagram 68 Hitachi...
Page 80: Pin Configuration
External vector number input pins D7–D0 Input external vector number 5.1.4 Register Configuration The INTC has the eight registers shown in table 5.2. These registers determine various INTC functions including setting interrupt priority, and controlling external interrupt input signal detection. Hitachi 69...
Page 81: Interrupt Sources
(UBC) is satisfied. User break interrupt exception processing sets the interrupt mask level bits (I3–I0) in the status register (SR) to level 15. For more information about the user break interrupt, see section 6, User Break Controller. 70 Hitachi...
Page 82: Irl Interrupts
IRL interrupt exception processing sets the interrupt mask level bits (I3 to I0) in the status register (SR) to the priority level value of the IRL interrupt that was accepted. Table 5.3 IRL Interrupt Priority Levels and Auto Vector Numbers Priority Vector IRL3 IRL2 IRL1 IRL0 Level Number Hitachi 71...
Page 83 Figure 5.2 Example of Connections for External Vector Mode Interrupts Figure 5.3 Example of Connections for Auto Vector Mode Interrupts 72 Hitachi...
Page 84 Figure 5.4 shows the interrupt fetch cycle for the external vector mode. During this cycle, CS0– CS3 stay high. A26–A4 output undefined values. The WAIT pin is sampled, but programmable waits are not valid. Figure 5.4 External Vector Mode Interrupt Vector Fetch Cycle Hitachi 73...
Page 85: On-Chip Peripheral Module Interrupts
A reset assigns priority level 0 to on-chip peripheral module interrupts. If the same priority level is assigned to two or more interrupt sources and interrupts from those sources occur simultaneously, their priority order is the default priority order indicated at the right in table 5.4. 74 Hitachi...
Page 86 — IRL10 — — IRL9 — — IRL8 — — IRL7 — — IRL6 — — IRL5 — — IRL4 — — IRL3 — — IRL2 — — IRL1 — — DIVU OVFI 0–15 (0) IPRA (15–12) 0–127 Hitachi 75...
Page 87: Description Of Registers
0 to 15 for on-chip peripheral module interrupts. IPRA is initialized to H'0000 on reset. It is not initialized in standby mode. Unless otherwise specified, ‘reset’ refers to both power- on and manual resets throughout this manual. 76 Hitachi...
Page 88: Interrupt Priority Level Setting Register B (Iprb)
Interrupt priority level setting register B (IPRB) is a 16-bit read/write register that assigns priority levels from 0 to 15 to on-chip peripheral module interrupts. IPRB is initialized to H'0000 on reset. It is not initialized in standby mode. Hitachi 77...
Page 89 0 (the lowest); H'F is level 15 (the highest). When two on-chip peripheral modules are assigned to the same bits (DMAC0 and DMAC1, or WDT and DRAM refresh control unit), those two modules have the same priority. A reset initializes IPRA and IPRB to H'0000. They are not initialized by the standby mode. 78 Hitachi...
Page 90: Vector Number Setting Register Wdt (Vcrwdt)
The vector number setting register A (VCRA) is a 16-bit read/write register that sets the SCI receive-error interrupt and receive-data-full interrupt vector numbers (0–127). VCRA is initialized to H'0000 on reset. It is not initialized in standby mode. Hitachi 79...
Page 91: Vector Number Setting Register B (Vcrb)
H'0000 on reset. It is not initialized in standby mode. Bit: Bit name: — STXV6 STXV5 STXV4 STXV3 STXV2 STXV1 STXV0 Initial value: R/W: Bit: Bit name: — STEV6 STEV5 STEV4 STEV3 STEV2 STEV1 STEV0 Initial value: R/W: 80 Hitachi...
Page 92: Vector Number Setting Register C (Vcrc)
Bits 6 to 0—Free-running timer (FRT) output-compare interrupt vector number (FOCV6– FOCV0): These bits set the vector number for the free-running timer (FRT) output-compare interrupt (OCI). There are seven bits, so the value can be set between 0 and 127. Hitachi 81...
Page 93: Vector Number Setting Register D (Vcrd)
Vector number setting register D Overflow interrupt (FRT) Reserved As table 5.6 shows, two on-chip peripheral module interrupts are assigned to each register. Set the vector numbers by setting the corresponding 7-bit groups (bits 14 to 8 and bits 6 to 0) with values 82 Hitachi...
Page 94: Interrupt Control Register (Icr)
Note: When NMI input is high: 1; when NMI input is low: 0 • Bit 15—NMI Input Level (NMIL): Sets the level of the signal input at the NMI pin. This bit can be read to determine the NMI pin level. This bit cannot be modified. Hitachi 83...
Page 95: Interrupt Operation
IPRB). Lower-priority interrupts are held pending. If two of these interrupts have the same priority level or if multiple interrupts occur within a single module, the interrupt with the highest default priority or the highest priority within its IPR setting unit (as indicated in table 5.4) is selected. 84 Hitachi...
Page 96 (D7–D0). The CPU reads the start address of the exception service routine from the exception vector table for the accepted interrupt, jumps to that address, and starts executing the program there. This jump is not a delay branch. Hitachi 85...
Page 97 I3-I0: Status register interrupt mask bit. Note: The vector number is only read from an external source when an external vector number is specified for the IRL interrupt vector number. Figure 5.5 Interrupt Sequence Flowchart 86 Hitachi...
Page 98: Stack After Interrupt Exception Processing
Table 5.8 indicates the interrupt response time, which is the time from the occurrence of an interrupt request until interrupt exception processing starts and fetching of the first instruction of the interrupt service routine begins. Figure 5.7 shows the pipeline when an IRL interrupt is accepted. Hitachi 87...
Page 99 + m4 Note: m1–m4 are the number of states needed for the following memory accesses m1: SR save (longword write) m2: PC save (longword write) m3: Vector address read (longword read) m4: Fetch first instruction of interrupt service routine 88 Hitachi...
Page 100: Sampling Of The Irl Pins (0-3)
When an external vector is fetched, the interrupt source can also be cleared when the external vector fetch cycle is detected. Figure 5.8 is a block diagram of the interrupt response procedure. Figure 5.9 shows interrupt response timing. Hitachi 89...
Page 101: Notes On Use
As shown in figure 5.10, the point at which the NMI request is cleared is the state following the decoding stage for the instruction that replaces the interrupt exception processing. 90 Hitachi...
Page 102 LDC instruction is used to enable another overlapping interrupt by changing the SR value. A read instruction for synchronization and a minimum of 4 instructions should thus be executed between the source clear and the LDC instruction. Hitachi 91...
Page 103 Figure 5.11 Pipeline Operation during Return with RTE Figure 5.12 Pipeline Operation when Interrupts are Enabled by Changing the SR 92 Hitachi...
Page 104 LDC instruction is used to enable another overlapping interrupt by changing the SR value. A read instruction for synchronization and a minimum of 2 instructions should thus be executed between the source clear and the LDC instruction. Figure 5.13 Pipeline Operation during Return with RTE Hitachi 93...
Page 105 Figure 5.14 Pipeline Operation when Interrupts are Enabled by Changing the SR 94 Hitachi...
Page 106: Section 6 User Break Controller
Use break interrupt generated upon satisfying break conditions. A user-designed user break interrupt exception processing routine can be run. • Select either to break in the instruction fetch cycle before the instruction is executed or after. • Compatible with SH7000 series UBCs during power-on resets. Hitachi 95...
Page 107: Block Diagram
Break address register BH/L BAMRBH/L: Break address mask register BH/L BDRBH/L: Break data register BH/L BDMRBH/L: Break data mask register BH/L BBRB: Break bus cycle register B BRCR: Break control register Figure 6.1 User Break Controller Block Diagram 96 Hitachi...
Page 108: Register Configuration
Notes: 1. Initializes by power-on reset. Values held for standby; manual resets produce undefined values. 2. No byte access permitted. SH7000 Series UBC Compatibility: When set in the SH7000-series-compatible mode, SH7000 series UBC registers on the SH7095 are as shown in table 6.2. Table 6.2 SH7000 Series and SH7095 UBCs SH7000 Series...
Page 109: Register Descriptions
BARAL stores the lower bits (bits 15 to 0). A power-on reset initializes both BARAH and BARAL to H'0000. • BARAH Bits 15 to 0—Break Address A 31 to 16 (BAA31 to BAA16): These bits store the upper bit values (bits 31 to 16) of the address of the channel A break condition. 98 Hitachi...
Page 110: Break Address Mask Register A (Bamra)
BARAL are masked. A power-on reset initializes BAMRAH and BAMRAL to H'0000. • BAMRAH Bits 15 to 0—Break Address Mask A 31 to 16 (BAMA31 to BAMA16): These bits specify whether bits 31–16 (BAA31 to BAA16) of the channel A break address set in BARAH are masked or not. Hitachi 99...
Page 111: Break Bus Cycle Register A (Bbra)
A break conditions: CPU cycle/peripheral cycle. Instruction fetch/data access. Read/write. Operand size. A power-on reset initializes BBRA to H'0000. • Bits 15 to 8—Reserved bits: These bits always read 0. The write value should always be 0. 100 Hitachi...
Page 112 Break only on read cycles Break only on write cycles Break on both read and write cycles • Bits 1 and 0—Operand Size Select A (SZA1, SZA0): These bits select bus cycle operand size as a channel A break condition. Hitachi 101...
Page 113: Break Address Register B (Barb)
The channel B break address mask register has the same bit configuration as BAMRA. 6.2.6 Break Data Register B (BDRB) BDRBH: Bit: Bit name: BDB31 BDB30 BDB29 BDB28 BDB27 BDB26 BDB25 BDB24 Initial value: R/W: Bit: Bit name: BDB23 BDB22 BDB21 BDB20 BDB19 BDB18 BDB17 BDB16 Initial value: R/W: 102 Hitachi...
Page 114: Break Data Mask Register B (Bdmrb)
(bits 15–0) of the data that is the break condition for break channel B. 6.2.7 Break Data Mask Register B (BDMRB) BDMRBH: Bit: Bit name: BDMB31 BDMB30 BDMB29 BDMB28 BDMB27 BDMB26 BDMB25 BDMB24 Initial value: R/W: Bit: Bit name: BDMB23 BDMB22 BDMB21 BDMB20 BDMB19 BDMB18 BDMB17 BDMB16 Initial value: R/W: Hitachi 103...
Page 115: Bus Break Register B (Bbrb)
3. The bus cycle of the external bus master when the bus is released cannot be included in the data bus conditions. 6.2.8 Bus Break Register B (BBRB) The channel B bus break register has the same bit configuration as BBRA. 104 Hitachi...
Page 116: Break Control Register (Brcr)
The BRCR: Determines whether to use channels A and B as two independent channels or as sequential conditions. Selects SH7000 series compatible mode/SH7095 mode. Selects whether to break before or after instruction execution during the instruction fetch cycle. Enables/disables external bus.
Page 117 Chip-external bus cycle not included in break conditions (initial value) Chip-external bus cycle included in break conditions. • Bit 12—UBC mode (UMD): Selects SH7000 series-compatible mode or SH7095 mode. Bit 12: UMD Description Compatible mode for SH7000-series UBCs (initial value) SH7095 mode •...
Page 118 Do not include data bus conditions in the channel B conditions (initial value) Include data bus conditions in the channel B conditions. • Bit 2—Instruction break select (PCBB): Selects whether to place the channel B instruction fetch cycle break before or after instruction execution Hitachi 107...
Page 119: Operation
The appropriate condition match flag (CMFCA, CMHPA, CMFCB, CMFPB) can be used to check if the set conditions match or not. The flags are set by the matching of the conditions, but they are not reset. 0 must first be written to them before they can be used again. 108 Hitachi...
Page 120: Break On Instruction Fetch Cycle
6.3. This means that when address H'00001003 is set without specifying the size condition, for example, the bus cycle in which the break condition is satisfied is as follows (where other conditions are met): Longword access at H'00001000 Word access at H'00001002 Byte access at H'00001003 Hitachi 109...
Page 121: Break On External Bus Cycle
Break on Instruction Fetch (After Execution): The program counter (PC) value saved to the stack in user break interrupt exception processing is the address executed after the one that matches the break condition. The fetched instruction is executed and the user break interrupt 110 Hitachi...
Page 122: Use Examples
Address = H'00037226, address mask H'00000000 Bus cycle = CPU, instruction fetch (before execution), read, word B ch: Address = H'0003722E, address mask H'00000000 Data H'00000000, data mask H'00000000 Bus cycle = CPU, instruction fetch (before execution), read, word Hitachi 111...
Page 123 Break on CPU Data Access Cycle: Register settings: BARA = H'00123456, BAMRA = H'00000000, BBRA = H'0064 BARB = H'000ABCDE, BAMRB = H'000000FF, BBRB = H'006A BDRB = H'0000A512, BDMRB = H'00000000 BRCR = H'1000 112 Hitachi...
Page 124: Notes On Use
Since the CPU uses a pipeline structure, the order of the instruction fetch cycle and memory cycle is fixed, so sequential conditions means that the sequential conditions will be satisfied when the respective channel conditions are met in the order the bus cycles occur. Hitachi 113...
Page 125: Sh7000-Series Compatibility Mode
SH7095 mode. For data access cycles, the address is always compared to 32 bits in the SH7000-series compatible mode, but in SH7095 mode is compared as shown in table 6.3. This produces the differences in break conditions shown in table 6.4.
Page 126 Table 6.4 Differences in Break Conditions SH7000 Series Match Determination Compatible Mode SH7095 Mode Conditions match when set for instruction Breaks if instruction is Does not break if fetch cycle/before-execution overrun fetched and instruction is overrun not executed (as during...
Page 127 116 Hitachi...
Page 128: Section 7 Bus State Controller (Bsc)
— Burst transfer during reads, high-speed page mode for consecutive accesses. — Generates a Tp cycle to ensure RAS precharge time. • Direct interface to synchronous DRAM — Multiplexes row/column addresses output. — Burst read, single write. — Bank active mode. Hitachi 117...
Page 129: Block Diagram
— In slave mode, the external bus is accessed when a bus use request is output and a bus use permission is received. • Refresh counter can be used as an interval timer — Interrupt request generated upon compare match (CMI interrupt request signal). 7.1.2 Block Diagram Figure 7.1 shows the BSC block diagram. 118 Hitachi...
Page 130 WCR: Wait control register RTCNT: Refresh timer counter BCR: Bus control register RTCOR: Refresh time constant register MCR: Individual memory control register RTCSR: Refresh timer control/status register Figure 7.1 BSC Block Diagram Hitachi 119...
Page 131: Pin Configuration
CASHL, DQMUL, (D23–D16). When synchronous DRAM is used, connected to DQM pin for the second byte. When pseudo SRAM is used, connected to WE pin for the second byte. For basic interface, indicates writing to the second byte. 120 Hitachi...
Page 132: Register Configuration
The size of the registers themselves is 16 bits. If read as 32 bits, the top 16 bits are 0. In order to prevent writing mistakes, 32-bit writes are accepted only when the top 16 bits of write data is H'A55A; no other writes are performed. Initialize the reserved bits. Hitachi 121...
Page 133: Address Map
7.1.5 Address Map The SH7095 address map, which has a memory space of 256 Mbytes, is divided into four spaces. The types and data width of devices that can be connected are specified for each space. The overall space address map is listed in table 7.3. Since the spaces of the cache area and the cache- through area are the same, the maximum memory space that can be connected is 128 Mbytes.
Page 134 H'E0001000 to H'FFFF7FFF Reserved H'FFFF8000 to H'FFFFBFFF For setting 16 kbytes synchronous DRAM mode H'FFFFC000 to H'FFFFFDFF Reserved 15.5 kbytes H'FFFFFE00 to H'FFFFFFFF On-chip peripheral 512 bytes module Note: Do not access reserved spaces. Accessing them will cause operating errors. Hitachi 123...
Page 135: Description Of Registers
1, the data is rearranged into little Endian before transfer when the CS2 space is read or written to. It is used when handling data with little Endian processors or running programs written with little Endian in mind. Bit 12 (ENDIAN) Description Big Endian, as in other areas (Initial value) Little Endian 124 Hitachi...
Page 136 Bits 5–4—Long Wait Specification of Area 0 (A0LW1–A0LW0): When the basic memory interface setting is area 0, the wait specifications of these fields are effective when the bit that specifies the wait in the wait control registers specifies long wait (i.e., 11). Hitachi 125...
Page 137: Bus Control Register 2 (Bcr2)
Do not access any space other than CS0 until the register initialization ends. • Bits 15–8—Reserved bits: These bits always read 0. The write value should always be 0. 126 Hitachi...
Page 138 Reserved (do not set) Byte (8 bits) size Word (16 bits) size Longword (32 bits) size (Initial value) • Bits 1–0—Reserved bits: These bits always read 0. Note: The bus size of area 0 is specified by the mode input pin. Hitachi 127...
Page 139: Wait Control Register (Wcr)
External wait input disabled without wait External wait input enabled with one wait External wait input enabled with two waits Complies with the long wait specification of bus control register 1 (BCR1). External wait input is enabled (Initial value). 128 Hitachi...
Page 140 W31 and W30: Bit 7 (W31) Bit 6 (W30) Description 2 cycles 3 cycles 4 cycles Reserved (do not set) When the setting is for 3 or more cycles, external wait input is enabled. Hitachi 129...
Page 141: Individual Memory Control Register (Mcr)
CE is asserted before BS is asserted. When synchronous DRAM is connected, specifies the number of cycles after a bank active (ACTV) command is issued until a read or write command (READ, READA, WRIT, WRITA) is issued. Bit 14 (RCD) Description 1 cycle (Initial value) 2 cycles 130 Hitachi...
Page 142 Bit 10 (BE) Description Burst disabled (Initial value) High-speed page mode during DRAM interface is enabled. Data is continuously transferred in static column mode during pseudo SRAM interface. During synchronous DRAM access, burst is always enabled regardless of this bit. Hitachi 131...
Page 143 4-Mbit DRAM (256k × 16 bits) Reserved (do not set) Reserved (do not set) Reserved (do not set) 2-Mbit DRAM (128k × 16 bits) Note: Reserved. Do not set when SZ bit in MCR is 0 (16-bit bus width). 132 Hitachi...
Page 144 When set for self refresh, self-refresh mode is entered immediately unless the SH7095 is in the middle of an synchronous DRAM or pseudo SRAM area access. If it is, self-refresh mode is entered when the access ends. Refresh requests from the interval timer are ignored during self refresh.
Page 145: Refresh Timer Control/Status Register (Rtcsr)
Bit 6—Compare Match Interrupt Enable (CMIE): Enables or disables an interrupt request caused by the CMF bit of the RTSCR when CMF is set to 1. Bit 6 (CMIE) Description Disables an interrupt request caused by CMF (Initial value) Enables an interrupt request caused by CMF 134 Hitachi...
Page 146: Refresh Timer Counter (Rtcnt)
The 8-bit counter RTCNT counts up with input clocks. The clock select bit of RTCSR selects an input clock. RTCNT values can always be read/written by the CPU. When RTCNT matches RTCOR, RTCNT is cleared. Returns to 0 after it counts up to 255. • Bits 15–8 always read 0. Hitachi 135...
Page 147: Refresh Time Constant Register (Rtcor)
BCR2 (for the CS1–CS3 spaces) or using the mode pins (for the CS0 space). Since the data width of devices connected to the respective spaces is specified statically, however, the data width cannot be changed for each access cycle. 136 Hitachi...
Page 148 (4n + 2 address), instruction fetches are performed in longword units from 4n address. Figures 7.2–7.4 show the relationship between device data widths and access units. Figure 7.2 32-Bit External Devices and Their Access Units (Ordinary) Figure 7.3 16-Bit External Devices and Their Access Units (Ordinary) Hitachi 137...
Page 149: Connections To Little Endian Devices
Endian. The relationship between device data width and access unit for little Endian is shown in figures 7.5 and 7.6. When sharing memory or the like with a little Endian bus master, the SH7095 connects D31–D24 to the least significant bytes of the other bus master and D7–D0 to the most significant bytes, when the bus width is 32 bits.
Page 150: Accessing Ordinary Space
For 32-bit devices, WE3 specifies writing to a 4n address and WE0 specifies writing to a 4n+3 address. For 16-bit devices, WE1 specifies writing to a 2n address and WE0 specifies writing to a 2n+1 address. For 8-bit devices, only WE0 is used. Hitachi 139...
Page 151 The RD signal must be used to control data output of external devices so that conflicts do not occur between trace information for emulators or the like output from the SH7095 and external device read data. In other words, when data buses are provided with buffers, the RD signal must be used for data output in the read direction.
Page 152 Figure 7.8 Example of 32-Bit Data Width SRAM Connection Hitachi 141...
Page 153 Figure 7.9 Example of 16-Bit Data Width SRAM Connection Figure 7.10 Example of 8-Bit Data Width SRAM Connection 142 Hitachi...
Page 154: Wait State Control
When the wait is specified by software using WCR, the wait input WAIT signal from outside is sampled. Figure 7.12 shows the WAIT signal sampling. A 2-cycle wait is specified as a software wait. The sampling is performed when the Tw state shifts to T2 state, so there is no effect even Hitachi 143...
Page 155 (such as ordinary space and burst ROM) that have a 8-bit bus width (byte size). Control waits in such cases with software only. Figure 7.12 Wait State Timing of Ordinary Space Access (Wait States from WAIT Signal) 144 Hitachi...
Page 156: Synchronous Dram Interface
2-Mbit (128k × 16), 4-Mbit (256k × 16), and 16-Mbit (1M × 16, 2M × 8, and 4M × 4) synchronous DRAMs can be connected directly to the SH7095. All of these are internally divided into two banks. Since synchronous DRAM can be selected by the CS signal, areas CS2 and CS3 can be connected using a common RAS or other control signal.
Page 157 Figure 7.13 Synchronous DRAM 32-bit Device Connection 146 Hitachi...
Page 158: Address Multiplex
(A0) specifies word address. The A0 of the synchronous DRAM is thus connected to the A1 pin of the SH7095, the rest of the connection proceeding in the same order, beginning with the A1 pin to the A2 pin.
Page 159: Burst Read
DRAM by another CS space are possible. Depending on the TRP specification in the MCR, the SH7095 determines the number of Tap cycles and does not issue a command to the same bank during that period.
Page 160 Synchronous DRAM CAS latency is up to 3 cycles, but the CAS latency of the bus state controller can be specified up to 4. This is so that circuits containing latches can be installed between synchronous DRAMs and the SH7095. Hitachi 149...
Page 161 Figure 7.15 Basic Burst Read Timing (Auto Precharge) 150 Hitachi...
Page 162: Single Read
When the data width is 16 bits, the number of burst transfers during a read is 8. BS is asserted and data fetched in cache-through and other DMA read cycles in the 8 cycles from Td1 to Td8 only in Hitachi 151...
Page 163: Write
Tc to perform an auto precharge. In the write cycle, the write data is output simultaneously with the write command. When writing with an auto precharge, the bank is precharged after the completion of the write command within the synchronous DRAM, so no 152 Hitachi...
Page 164 Trw1 to wait until the precharge is started up. The number of cycles in the Trw1 cycle can be specified using the TRWL bit of the MCR. Figure 7.18 Basic Write Cycle Timing (Auto Precharge) Hitachi 153...
Page 165: Bank Active
READ command, synchronous DRAMs, however, have a 2 cycle latency during reads for the DQMxx signals that specify bytes. If the Tc cycle is performed immediately without inserting a Tnop cycle, the DQMxx signal for the Td1 cycle data output cannot be specified. This is why the 154 Hitachi...
Page 166 DQMxx signal is set after the Tc cycle. When the SH7095 is set to the bank active mode, the access will start with figure 7.19 or figure 7.22 and repeat figure 7.20 or figure 7.23 for as long as the same row address continues to be accessed when only accesses to the respective banks of the CS3 space are considered.
Page 167 Figure 7.20 Burst Read Timing (Bank Active, Same Row Address) 156 Hitachi...
Page 168 Figure 7.21 Burst Read Timing (Bank Active, Different Row Addresses) Hitachi 157...
Page 169 Figure 7.22 Write Timing (No Precharge) 158 Hitachi...
Page 170 Figure 7.23 Write Timing (Bank Active, Same Row Address) Hitachi 159...
Page 171: Refreshes
Auto refreshes can be performed by setting the MCR’s RMD bit to 0 and the RFSH bit to 1. When the synchronous DRAM is not accessed for a long period of time, set the RFSH bit and RMODE bit both to 1 to start up the self-refresh mode, which uses low consumption power to maintain data. 160 Hitachi...
Page 172 During a manual reset, no refresh request is occurred, since there is no RTCNT count-up. To perform a refresh properly, make the manual reset period shorter than the refresh cycle interval and set RTCNT to (RTCOR – 1) so that the refresh is performed immediately after the manual reset is cleared. Hitachi 161...
Page 173 RTCNT value is set to RTCOR – 1, the refresh can be started immediately. If the standby function of the SH7095 is used after the self refresh is set to enter the standby mode, the self-refresh state continues; the self-refresh state will also be maintained after returning from a standby using an NMI.
Page 174: Power-On Sequence
Write any data in word size to the following addresses to set for the burst read single write supported by the SH7095, a CAS latency of 1 to 3, a sequential wrap type, and a burst length of 8 or 4 (depending on whether the width is 16 bits or 32 bits).
Page 175 Because the address counter within the synchronous DRAM is not initialized when the auto refresh is used during single read or write accesses, it must always be an auto-refresh cycle. 164 Hitachi...
Page 176: Phase Shift By Pll
When the internal clock of the SH7095 and external clock are synchronized, signal transmission from the SH7095 to the synchronous DRAM has a 1 cycle margin. The transmission of read data from the synchronous DRAM to the SH7095, however, is much tighter: only 1/2 cycle, including...
Page 177 When the phase of the internal clock of the SH7095 is delayed using a PLL that delays the phase 90 degrees relative to external clocks, transmission from the SH7095 to the synchronous DRAM and transmission from the SH7095 to the synchronous DRAM each takes 3/4 cycle.
Page 178 Phase Shifted 90° by PLL b. Phase Shift Using PLL is 0 Figure 7.28 Phase Shift with the PLL Hitachi 167...
Page 179: Dram Interface
When the DRAM and other memory enable bits (DRAM2–DRAM0) of BCR1 are set to 010, CS3 space becomes DRAM space, and a DRAM interface function can be used to directly connect the SH7095 to the DRAM. The data width of an interface can be 16 or 32 bits (figures 7.29 and 7.30). Two-CAS 16-bit DRAMs can be connected, since CAS is used to control byte access.
Page 180 Figure 7.29 Example of a DRAM Connection (32-Bit Data Width) Hitachi 169...
Page 181: Address Multiplex
Address Multiplex When CS3 space is set to DRAM, addresses are always multiplexed. This allows DRAMs that require multiplexing of row and column addresses to be connected directly to SH7095 microprocessors without additional multiplexing circuits. There are four ways of multiplexing, which can be selected using the MCR’s AMX1–AMX0 bits.
Page 182: Basic Timing
Tp is the precharge cycle, Tr is the RAS assert cycle, Tc1 is the CAS assert cycle and Tc2 is the read data fetch cycle. When accesses are consecutive, the Tp cycle of the next access overlaps the Tc2 cycle of the previous access, so accesses can be performed at a minimum of 3 cycles each. Hitachi 171...
Page 183: Wait State Control
Wait State Control When the clock frequency is raised, 1 cycle may not always be sufficient for all states to end, as the basic access does. Setting bits in the WCR and MCR enable the state to be lengthened. Figure 172 Hitachi...
Page 184 Figure 7.33 shows the timing of wait state control using the WAIT pin. In either case, when consecutive accesses occur, the Tp of one access overlaps with the Tc2 of the previous access. Figure 7.32 Wait State Timing Hitachi 173...
Page 185: Burst Access
Select ordinary access or high-speed page mode by setting the burst enable bit (BE) in the MCR. Figure 7.34 shows the timing of burst operation in the high- speed page mode. When performing burst access, cycles can be inserted using the wait state control function. 174 Hitachi...
Page 186 When this function is used and the BE bit of the MCR is set to 1, setting the MCR’s RASD bit (which specifies the RAS down mode) to 1 places the SH7095 in RAS down mode, which leaves the RAS asserted. Since the CASHH, CASHL, CASLH and CASLL signals are shared with the WE3, WE2, WE1 and WE0 of ordinary space, however, write cycles to ordinary space during RAS down will simultaneously start up an erroneous write access to the DRAM.
Page 187: Refresh Timing
RMODE and RFSH bits of the MCR, then set the CKS2–CKS0 bits. When a clock is selected with the CKS2–CKS0 bits, RTCNT starts counting up from the value at that time. The RTCNT value is constantly compared to the RTCOR value and a request for a refresh is made 176 Hitachi...
Page 188: Power-On Sequence
(usually 8) are requested. The bus state controller does not perform any special operations for the power-on reset, so the required power- on sequence must be implemented by the initialization program executed after a power-on reset. Hitachi 177...
Page 189: Pseudo-Sram Interface
SRAM interface function can be used to directly connect the SH7095 to a pseudo SRAM. The interface data width is 16 or 32 bits. The refresh and output enable signals of the connected pseudo SRAM are multiplexed. The signals used for connecting pseudo SRAM are the CE, OE, WE3, WE2, WE1, and WE0 signals.
Page 190 Figure 7.36 Example of Pseudo-SRAM Connection (1-M pseudo SRAM) Hitachi 179...
Page 191 Figure 7.37 Example of Pseudo-SRAM Connection (4-M pseudo SRAM) 180 Hitachi...
Page 192: Basic Timing
Tc1 is the write data output, BS is the assert cycle and Tc2 is the read data fetch cycle. When accesses are consecutive, the precharge cycle Tp of the next access overlaps the Tc2 cycle of the previous access, so accesses can be performed in a minimum of 3 cycles each. Hitachi 181...
Page 193: Wait State Control
When the clock frequency is raised, 1 cycle may not always be sufficient for all states to end, as the basic access does. Setting bits in the WCR and MCR enable the state to be lengthened. Figure 7.39 shows an example of lengthening a state using settings. The Tp cycle that ensures sufficient 182 Hitachi...
Page 194 MCR is set to 0 for a pseudo-SRAM interface, but when set to 1, the number of cycles from the CE assert to the BS assert or write data output becomes 2. Figure 7.39 Wait State Timing Hitachi 183...
Page 195: Burst Access
Select between ordinary access and burst mode using static column mode by setting the burst enable bit (BE) in the MCR. Figure 7.41 shows the timing of burst operation using static column mode. When performing burst access, cycles can be inserted using the wait state control function. 184 Hitachi...
Page 196: Refresh
RTCNT and the RMODE and RFSH bits of the MCR, then set the CKS2–CKS0 bits. When a clock is selected with the CKS2–CKS0 bits, RTCNT starts counting up from the value at that time. The RTCNT value is constantly compared to the RTCOR value and a request for a refresh is Hitachi 185...
Page 197 SRAM so that the auto refresh is performed in the correct interval. This ensures a correct self refresh clear and data holding. When time is required between clearing the self refresh and starting the auto-refresh mode, this time must be reflected in the initial RTCNT setting. 186 Hitachi...
Page 198: Power-On Sequence
16 accesses for cache fills. Limited support of nibble access was thus added to alleviate this problem. When connecting to an 8-bit width ROM, a maximum of 4 consecutive accesses are performed; when connecting to a 16-bit width ROM, a maximum of 2 consecutive accesses are Hitachi 187...
Page 199 When one or more wait states are set for a burst ROM access, the WAIT pin is sampled. When the burst ROM is set and 0 indicated for waits, there are 2 access cycles from the second time on. Figure 7.46 shows the timing. Figure 7.44 Burst ROM Nibble Access (2 Wait States) 188 Hitachi...
Page 200 8-bit bus-width byte access 16-bit bus-width longword access 16-bit bus-width word access 16-bit bus-width byte access 32-bit bus-width longword access 32-bit bus-width word access 32-bit bus-width byte access Figure 7.45 Data Width and Burst ROM Access (1 Wait State) Hitachi 189...
Page 201: Waits Between Access Cycles
SH7095. When the SH7095 is writing continuously, if the format is always to have the direction of the data from the SH7095 to other memory, there are no particular problems. Neither is there any particular problem if the following read access is to the same CS space, since data is output from the same data buffer.
Page 202: Bus Arbitration
1 wait cycle is inserted even when 0 is specified for waits between access cycles. When the SH7095 shifts to a read cycle immediately after a write, the write data becomes high impedance when the clock rises, but the RD signal, which indicates the read cycle data output enable, is not asserted until the clock falls.
Page 203 Even when there does not appear to be an ongoing bus cycle when seen from outside the SH7095, it cannot be determined whether or not the bus will be released immediately when a bus control signal such as a CSn signal is seen, since an internal bus cycle, such as inserting a wait between access cycles, may have been started.
Page 204: Master Mode
PC save and SR save cycles during interrupt processing, which are all independent accesses. Because the CPU on the SH7095 is connected to cache memory by a dedicated internal bus, cache memory can be read even when the bus is being used by another bus master on the chip or externally.
Page 205 When a refresh request occurs while the BGR is asserted and the bus released, BGR is negated even when the BRLS signal is asserted to request the slave to release the bus. When the SH7095 is being used in the slave mode, the bus is released as soon as the bus access cycle ends, so there is no need to request that the bus be released when a refresh request occurs.
Page 206: Slave Mode
Since refresh control is handled by the master mode device, any refresh control setting performed in the slave mode is ignored. Figure 7.49 shows an example of master mode and slave mode connections. Hitachi 195...
Page 207: Partial-Share Master Mode
There is a buffer for addresses and control signals and a buffer for data located between the partial-share master and the master. They are controlled by a buffer control circuit. The buffers latch signals synchronous to the clock rise and match timing, so 196 Hitachi...
Page 208 DRAM. Other spaces always have the bus themselves, so there is no precharge of CS3 space memory upon release after a CS2 space bus request, even when DRAM, synchronous DRAM or pseudo SRAM is connected to the CS3 space. Partial-share master mode does not refresh CS2 (it is ignored). Hitachi 197...
Page 209 Figure 7.50 Master and Partial-Share Master Connections 198 Hitachi...
Page 210: External Bus Address Monitor
When using standby operation to lower power consumption, burdens must also be shared. This SH7095 was designed with the idea that the master mode device would handle all controls, such as initialization, refresh and standby control. When a 2-processor structure of connected master and slave is used, all processing except for direct accesses to memory are controlled by the master.
Page 211: Other Topics
When a manual reset is performed, any executing bus cycles are completed, and then the SH7095 waits for an access. When a cache fill or 16-byte DMAC transfer is executing, the CPU or DMAC that is the bus master ends the access in a longword unit, since the access request is canceled by the manual reset.
Page 212 DMA transfer thus starts up in the next read cycle without waiting for the end of the write cycle. When both the source address and destination address of the DMA are external spaces to the chip, however, it must wait until the completion of the previous write cycle before starting the next read cycle. Hitachi 201...
Page 213: Emulator
7.11.3 Emulator When using the SH7095’s emulator, operation differs from real chip operation in the following ways. To get trace data with the emulator, all accesses performed by the CPU and DMAC must be output externally. It is not possible to completely analyze program execution or the contents of the data accessed with only traces of access cycles performed exterior to the chip.
Page 214: Section 8 Cache
The SH7095 incorporates 4-kbyte of 4-way cache memory of an instruction/data combination type. The SH7095 can also be used as 2-kbyte RAM and 2-kbyte cache memory (instruction/data combination type) by setting the values of the cache control register CCR (two-way cache mode).
Page 215: Cache Control Register (Ccr)
Bits 7 and 6—Way Specification (W1 to W0): W1 and W0 specify the way when an address array is directly accessed by address specification. 00: Way 0 (Initial value) 01: Way 1 10: Way 2 11: Way 3 204 Hitachi...
Page 216: Address Space And The Cache
The address space is divided into six partial spaces. The cache access operation is specified by addresses. Table 8.2 lists the partial spaces and their cache operations. For more information on address spaces, see section 7, Bus State Controller. Note that the spaces of the cache area and cache-through area are the same. Hitachi 205...
Page 217: Cache Operation
CPU’s pipeline structure. From address comparison to data read requires 1 cycle; since the address and data operate as a pipeline, consecutive reads can be performed at each cycle with no waits. 206 Hitachi...
Page 218 EX: Instruction execution MA: Memory Access WB: Write back Figure 8.3 Reading during a Cache Hit Hitachi 207...
Page 219 CPU. The internal address bus and internal data bus also function as pipelines, just like the cache bus. EX: Instruction execution MA: Memory Access WB: Write back Figure 8.4 Reading during a Cache Miss 208 Hitachi...
Page 220: Writing
The write address is output to the internal address bus 1 cycle later than the cache address bus. The write data is similarly output to the internal data bus 1 cycle later than the cache data bus. The CPU waits until the writes onto the internal bus are completed. Figure 8.5 Writing Hitachi 209...
Page 221: Cache-Through Access
8.7. EX: Instruction execution MA: Memory Access WB: Write back Figure 8.6 Reading Cache-Through Areas 210 Hitachi...
Page 222: The Tas Instruction
Six bits of data are used as the LRU information. The bits indicate the access order for 2 ways, as shown in figure 8.8. When the value is 1, access occurred in the direction of the appropriate arrow in the figure. The direction of the arrow can be determined by reading the bit. All the arrows show Hitachi 211...
Page 223 When the memory access is aborted by a reset during replacement or the like, the cache contents and memory contents may be out of sync, so always do a purge. Figure 8.8 LRU Information and Access Sequence 212 Hitachi...
Page 224: Cache Initialization
16 bytes are purged in each write, so a purge of 256 bytes of consecutive areas can be accomplished in 16 writes. Access sizes when associative purges are performed should be longword. A purge of 1 line requires 2 cycles. Hitachi 213...
Page 225: Data Array Access
The address array of the cache can be accessed so that the contents fetched to the cache can be checked for purposes of program debugging or the like. The address array is mapped on H'60000000 to H'600003FF. Since all of the ways are mapped to the same address, ways are 214 Hitachi...
Page 226: Cache Use
The address array write function can be used to initialize each line, but it is simpler to initialize it once by writing 1 to the CP bit of the CCR. Figure 8.12 shows how to initialize the cache. Hitachi 215...
Page 227: Purge Of Specific Lines
8.5.2 Purge of Specific Lines Since the SH7095 has no snoop function (for monitoring data rewrites), specific lines of cache must be purged when the contents of cache memory and external memory differ as a result of an operation. For instance, when a DMA transfer is performed to the cache area, cache lines corresponding to the rewritten address area must be purged.
Page 228: Cache Data Coherency
8.5.3 Cache Data Coherency The SH7095’s cache memory has a snoop function. This means that when data is shared with a bus master other than the CPU, software must be used to ensure the coherency of data. To this end, the cache-through are can be used, the break function of can be used in the external bus cycle, or a cache purge can be performed with program logic.
Page 229: Two-Way Cache Mode
Standby: Disable the cache before entering the standby mode for power-down operation. After returning from power-down, initialize the cache before using it. Cache Control Register: Changing the CCR’s contents also changes cache operation. The SH7095 makes full use of pipeline operations, so it is difficult to synchronize access. For this 218 Hitachi...
Page 230 Hitachi 219...
Page 231 220 Hitachi...
Page 232: Section 9 Direct Memory Access Controller (Dmac)
Section 9 Direct Memory Access Controller (DMAC) Overview The SH7095 includes a two-channel direct memory access controller (DMAC). The DMAC can be used in place of the CPU to perform high-speed data transfers between external devices equipped with DACK (transfer request acknowledge signal), external memories, memory-mapped external devices, and on-chip peripheral modules (except for the DMAC, BSC and UBC).
Page 233: Block Diagram
Selectable bus modes: Cycle-steal mode or burst mode • Selectable channel priority levels: Fixed or round-robin mode • CPU can be asked for interrupt when data transfer-ends 9.1.2 Block Diagram Figure 9.1 is a block diagram of the DMAC. 222 Hitachi...
Page 234 VCRDMAn: DMA vector register DEIn: Request for interrupt at end of DMA transfer to CPU RXI: Receive-data-full interrupt transfer request of on-chip SCI TXI: Transmit-data-full interrupt transfer request of on-chip SCI n 0 to 1 Figure 9.1 DMAC Block Diagram Hitachi 223...
Page 235: Pin Configuration
1 to external device 9.1.4 Register Configuration Table 9.2 summarizes the DMAC registers. The DMAC has a total of 13 registers. Each channel has six control registers. One control register is shared by all channels. 224 Hitachi...
Page 236: Register Descriptions
3. Access DRCR0 and DRCR1 in byte units. Access all other registers in longword unit. Register Descriptions 9.2.1 DMA Source Address Registers 0 and 1 (SAR0 and SAR1) Bit: … Bit name: … Initial value: — — — … — — — — R/W: … Hitachi 225...
Page 237: Dma Destination Address Registers 0 And 1 (Dar0 And Dar1)
32 bits, including the top eight bits. The number of transfers is 1 when the setting is H'00000001, 16,777,215 when the setting is H'00FFFFFF and 16, 777,216 (the maximum) when H'00000000 is set. During a DMA transfer, these registers indicate the remaining transfer count. 226 Hitachi...
Page 238: Dma Channel Control Registers 0 And 1 (Chcr0 And Chcr1)
DM1 and DM0 are ignored when transfers are made from memory-mapped external devices, on-chip peripheral modules, or external memory to external devices with DACK). DM1 and DM0 are initialized to 00 by resets and the standby mode. Values are held during a module standby. Hitachi 227...
Page 239 TS1 and TS0 are initialized to 00 by resets and in the standby mode. Values are held during a module standby. Bit 11: TS1 Bit 10: TS0 Description Byte unit (initial value) Word (2-byte) unit Longword (4-byte) unit 16-byte unit (4 longword transmissions) 228 Hitachi...
Page 240 Bit 5—DREQ Level Bit (DL): Selects active high signal or active low signal for the DREQ signal. The DL bit is initialized to 0 by reset and in the standby mode. Values are held during a module standby. Hitachi 229...
Page 241 To clear the TE bit, read 1 from it and then write 0. When the TE bit is set, setting the DE bit to 1 will not enable a transfer. The TE bit is initialized to 0 by reset and in the standby mode. Values are held during a module standby. 230 Hitachi...
Page 242: Dma Vector Number Registers 0 And 1 (Vcrdma0, Vcrdma1)
24 bits. These bits are initialized to H'000000XX (last eight bits are undefined) by a reset and in the standby mode. Values are held during a module standby. • Bits 31–8—Reserved bits: Only write 0 to these bits. They always read 0. Hitachi 231...
Page 243: Dma Request/Response Selection Control Registers 0 And 1 (Drcr0, Drcr1)
(SCI))* TXI (transmit-data-empty interrupt transfer request of the on- chip SCI)* Reserved (setting disabled) Note: For RX2 and TX1, set for dual transfer mode. The DREQ settings in the CHCR are DS = 1 and DL = 0. 232 Hitachi...
Page 244: Dma Operation Register (Dmaor)
DMA channel control register (CHCR) is set to 1. To clear the AE bit, read 1 from it and then write 0 carried out in the DMAC transfer being executed when the address error arose. AE is initialized to 0 by a reset or in the standby mode. Hitachi 233...
Page 245: Operation
Transfers can be requested in three modes: auto-request, external request, and on-chip module request. A transfer can be in either the single address mode or the dual address mode. The bus mode can be either burst or cycle-steal. 234 Hitachi...
Page 246: Dma Transfer Flow
When an address error occurs in the DMAC or an NMI interrupt is generated, the transfer is aborted. Transfers are also aborted when the DE bit of the CHCR or the DME bit of the DMAOR are changed to 0. Figure 9.2 is a flowchart illustrating this procedure. Hitachi 235...
Page 247 0 and the DE and DME bits are then set to 1. In burst mode, DREQ = level detection (external request), or cycle-steal mode. In burst mode, DREQ = edge detection (external request), or auto-request mode in burst mode. Figure 9.2 DMA Transfer Flow 236 Hitachi...
Page 248: Dma Transfer Requests
Choose one of the modes shown in table 9.4 according to the application system. When DMA transfer is enabled (DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0), a transfer is performed upon input of a DREQ. Hitachi 237...
Page 249 (TXI) of the SCI (table 9.6). If the DMA transfer is enabled (DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0), the DMA transfer starts upon the input of a transfer request signal. 238 Hitachi...
Page 250: Channel Priority
Fixed Priority Mode: In this mode, the priority levels among the channels remain fixed. When PR is set to 0, the priority, high to low, is channel 0 > channel 1. Figure 9.3 shows an example of a transfer in burst mode. Hitachi 239...
Page 251 0 transfer is requested after the first two transfers end. The DMAC operates as follows: Transfer requests are generated simultaneously to channels 1 and 0. Channel 1 has a higher priority, so the channel 1 transfer begins first (channel 0 waits for transfer). 240 Hitachi...
Page 252: Dma Transfer Types
DMAC takes to access the transfer source and transfer destination. The actual transfer operation timing varies with the DMAC bus mode used: cycle-steal mode or burst mode. Hitachi 241...
Page 253 Figure 9.6 shows an example of a transfer between an external memory and an external device with DACK. The external device outputs data to the data bus while that data is written in external memory in the same bus cycle. 242 Hitachi...
Page 254 DACK and memory-mapped external devices; and 2) transfers between external devices with DACK and external memory. Transfer requests for both of these must be in the external request (DREQ). Figure 9.7 shows the DMA transfer timing for the single address mode. Hitachi 243...
Page 255 The transfer data are temporarily stored in the DMAC. Figure 9.8 shows an example of a transfer between two external memories in which data is read from one memory in the read cycle and written to the other memory in the following write cycle. 244 Hitachi...
Page 256 SCI (see table 9.6). The dual address mode outputs the DACK in either the read cycle or write cycle. The CHCR controls the cycle of DACK output. Figure 9.9 shows the DMA transfer timing in the dual address mode. Hitachi 245...
Page 257 The CPU may take the bus twice when an acknowledge signal is output during the write cycle or in the single address mode. Figure 9.10 shows an example of DMA transfer timing in the cycle-steal mode (dual address mode, DREQ level detection). 246 Hitachi...
Page 258 Relationship of Request Modes and Bus Modes by DMA Transfer Category: Table 9.8 shows the relationship between request modes, bus modes, and the like by DMA transfer category. Hitachi 247...
Page 259 1, channel 0, channel 1, channel 0. Since channel 1 is in burst mode, it will not give the bus to the CPU. This example is illustrated in Figure 9.12. 248 Hitachi...
Page 260: Number Of Bus Cycles
0.5 cycles before the address output ends. (see figure 9.11.) The output timing of the acknowledge signal varies with the settings of the connected memory space. The output timing of acknowledge signals in the memory spaces is shown in figure 9.13. Figure 9.13 Example of DACK Output Timing Hitachi 249...
Page 261 0.5 cycles before the address output ends. When multiple addresses are output in a single access to align data for synchronous DRAM, DRAM, pseudo-SRAM, and burst ROM, an acknowledge signal is output to those addresses as well. 250 Hitachi...
Page 262 L: LSB side H: MSB side Figure 9.16 DACK Output in Ordinary Space Accesses (AM = 0, longword access to 16-bit external device) Figure 9.17 DACK Output in Ordinary Space Accesses (AM = 0, longword access to 8-bit external device) Hitachi 251...
Page 263 When AM = 1, the acknowledge signal is output across the row address and column address of the DMAC write (figure 9.21). Figure 9.19 DACK Output in Synchronous DRAM Burst Read (Auto-precharge, AM = 0) 252 Hitachi...
Page 264 (figure 9.22). When the row address is different from the previous address, the acknowledge signal is output across the precharge, row address, read command, wait and read address (figure 9.23). Hitachi 253...
Page 265 (figure 9.25). Since the synchronous DRAM read has only bursts, during a single read an invalid address is output; the acknowledge signal is output on the same timing. At this time, the acknowledge signal is extended until the write address is output after the invalid read. 254 Hitachi...
Page 266 (figure 9.26). When the row address is different from the previous address, the acknowledge signal is output across the precharge, row address, wait and column address (figure 9.27). Hitachi 255...
Page 267 Acknowledge Signal Output when External Memory Is Set as DRAM: When external memory is set as DRAM and a row address is output during a read or write, the acknowledge signal is output across the row address and column address (figures 9.28–9.30). 256 Hitachi...
Page 268 Figure 9.28 DACK Output in Normal DRAM Accesses (AM = 1 or 0) Figure 9.29 DACK Output in DRAM Burst Accesses (Same Row Address, AM = 1 or 0) Hitachi 257...
Page 269 SRAM , the acknowledge signal is output synchronous to the DMAC address for both reads and writes (figures 9.31–9.33). Figure 9.31 DACK Output in Normal Pseudo SRAM Accesses (AM = 1 or 0) 258 Hitachi...
Page 270 (Different Row Address, AM = 1 or 0) Acknowledge Signal Output When External Memory Is Set as Burst ROM: When external memory is set as burst ROM, the acknowledge signal is output synchronous to the DMAC address (no dual writes allowed) (figure 9.34). Hitachi 259...
Page 271: Dreq Pin Input Detection Timing
Cycle Steal Mode Edge Detection Requests can be detected 2 cycles after DACK output. After that point, the request is input to DREQ. (When input prior to that point, requests are sometimes detected by internal state, sometimes not.) 260 Hitachi...
Page 272 CPU cycle. Figure 9.35 DREQ Pin Input Detection Timing in Cycle Steal Mode with Edge Detection (1) Figures 9.36 and 9.37 show are examples of how to change the bus width of an external device. Hitachi 261...
Page 273 Figure 9.36 Changing the Bus Size of a 16-Bit External Device Notes: 1. Request detection When a write (dual) occurs at DACK output, the cycle is a DMAC read. Otherwise, the cycle is a CPU cycle. Figure 9.37 Changing the Bus Size of an 8-Bit External Device 262 Hitachi...
Page 274 Requests can be detected 2 cycles after DACK output. After that point, the request is input to DREQ. (When input prior to that point, requests are sometimes detected by internal state, sometimes not.) DACK is output synchronous to all 4 transfers (figure 9.38). Hitachi 263...
Page 275 3 cycles from the bus cycle prior to the DMAC read cycle, the next DMA transfer is not performed; if request output is stopped within 2 cycles of DACK output, the next DMA transfer may sometimes be performed. See Examples of Handling of Request Signal Acceptance later in this section (9.3.7). 264 Hitachi...
Page 276 Notes: 1. Request detection Request detection not established. Figure 9.40 Changing the Bus Size of a 16-Bit External Device Notes: 1. Request detection Request detection not established. Figure 9.41 Changing the Bus Size of an 8-Bit External Device Hitachi 265...
Page 277 DACK output timing: DMAC write cycle Bus cycle: Basic bus cycle Note: Request detection Figure 9.42 Timing of DREQ Pin Input Detection in Cycle Steal Mode with Level Detection (2) The next request can be detected 2 cycles after DACK output (figure 9.42). 266 Hitachi...
Page 278 3 cycles from the bus cycle prior to the DMAC read cycle, the next DMA transfer is not performed; if request output is stopped within 2 cycles of DACK output, the next DMA transfer may sometimes be performed. Hitachi 267...
Page 279 Note: When transferring alternately on ch0 and ch1 by round robin or the like, the next request signal is detected only 2 cycles after the first acknowledge signal of each transfer (figure 9.45). 268 Hitachi...
Page 280 DREQ input is detected by edge and when detected by level. When DREQ input is detected by edge, once a request is detected, DMA transfers continue until the conditions for ending the transfers are met, regardless of the state of the REQ pin thereafter. Hitachi 269...
Page 281 Bus cycle: Basic bus cycle Note: Request detection (The points when the 1st through 4th acceptances occur vary with the type of wait.) Figure 9.46 Timing of DREQ Pin Input Detection in Burst Mode with Level Detection (1) 270 Hitachi...
Page 282 2 cycles of the output of this acknowledge signal, the third request in figure 9.48 is accepted. This means that 3 DMA transfers are executed even when the request for the first acknowledge signal drops out. Hitachi 271...
Page 283: Dma Transfer-End
This means that when DMAC operation is emulated, the timing is somewhat different, which may have other ramifications. 9.3.8 DMA Transfer-End The DMA transfer ending conditions vary when channels ending individually and when both channels ending together. 272 Hitachi...
Page 284 To avoid this, keep its DE bit at 0. In the dual address mode, the DMA transfer will be halted after the completion of the following write cycle even when the address error occurs in the initial read cycle. SAR, DAR and TCR are updated by the final transfer. Hitachi 273...
Page 285: Examples Of Use
When the cache is used as the on-chip RAM, the DMAC cannot access this RAM. Set to standby mode after the DME bit of the DMAOR is set to 0. Do not access the DMAC, BSC, and UBC on-chip peripheral modules. 274 Hitachi...
Page 286 Do not access the cache (address array, data array, associative purge area). To detect the DREQ pin in single address mode, use edge detection. Hitachi 275...
Page 287 276 Hitachi...
Page 288: Section 10 Division Unit
Completes operation execution in 39 cycles • Controls enables/disables of over/underflow interrupts • Even during the division process, instructions not accessing the division unit can be parallel processed 10.1.2 Block Diagram Figure 10.1 shows a block diagram of the division unit. Hitachi 277...
Page 289: Register Configuration
Dividend register L for 32 bits DVDNTH: Dividend register H DVDNTL: Dividend register L DVCR: Division control register VCRDIV: Vector number setting register DIV Figure 10.1 Division Unit Block Diagram 10.1.3 Register Configuration Table 10.1 lists the register configuration of the division unit. 278 Hitachi...
Page 290: Description Of Registers
… The dividend register L for 32-bits (DVDNT) is a 32-bit read/write register in which the 32-bit dividend used for 32 bit / 32 bit division operations is written. When 32 bit / 32 bit division is run, Hitachi 279...
Page 291: Division Control Register (Dvcr)
Note: Always set the OVFIE bit before starting up the operation whenever doing interrupt processing for overflows. • Bit 0: Overflow flag (OVF). Flag indicating an overflow has occurred. Bit 0: OVF Function No overflow has occurred (initial value) Overflow has occurred. 280 Hitachi...
Page 292: Vector Number Setting Register (Vcrdiv)
When the DVDNT register is set with a dividend value, the previous DVDNTH value is lost and the MSB of the DVDNT register is expanded to the entire DVDNTH. Hitachi 281...
Page 293: Dividend Register L (Dvdntl)
This unit finishes a single operation in 39 cycles (starting from the setting of the value in the DVDNT). When an overflow occurs, however, the operation ends in 6 cycles. See section 10.3.3, Handling of Overflows, for more information. Note that the operation is signed. 282 Hitachi...
Page 294: Handling Of Overflows
6 cycles set in DVDNTH and the maximum value H'7FFFFFFF and minimum value H'80000000 set in DVDNTL. In the SH7095, the maximum value is resulted when a positive quotient overflows; the minimum value is when a negative quotient overflows. The first three cycles of the 6 cycles executed when an overflow occurs are used for flag setting within the division unit and the next three for division.
Page 295: Overflow Flag
Sets the maximum for overflows to the overflow generation is detected* plus side or minimum value for overflows to the minus side Note: In division processing, the operation intermediate result is written for cycles up to detection of overflow generation. 284 Hitachi...
Page 296: Section 11 16-Bit Free-Running Timer
11.1 Overview The SH7095 has a 1-channel, 16-bit free-running timer (FRT) on-chip. The FRT is based on a 16-bit free-running counter (FRC) and can output two types of independent waveforms. The FRT can also measure the width of input pulses and the cycle of external clocks.
Page 297: Block Diagram
FICR: Input capture register (16 bits) TCR: Timer control/status register (8 bits) TIER: Timer interrupt enable register (8 bits) FTCSR: Free running timer control register (8 bits) TOCR: Timer output compare control register (8 bits) Figure 11.1 FRT Block Diagram 286 Hitachi...
Page 298: Pin Configuration
Notes: 1. Bits 7 to 1 are read-only. The only value that can be written is a 0, which is used to clear flags. Bit 0 can be read or written. 2. OCRA and OCRB have the same address. The OCRS bit of the TOCR is used to switch between them. Hitachi 287...
Page 299: Register Descriptions
Because the OCR is a 16-bit register, data transfers involving the CPU go through a temporary register (TEMP). See section 11.3, CPU Interface, for more detailed information. The OCR is initialized to H'FFFF by a reset, in the standby mode, and when the module standby function is used. 288 Hitachi...
Page 300: Input Capture Register (Icr)
Bit 7: Input capture interrupt enable (ICIE). Selects enable/disable for interrupts by the ICF (ICI) when the input capture flag (ICF) of the FTCSR is set to 1. Bit 7: ICIE Description Disables interrupt requests (ICI) from the ICF (initial value) Enables interrupt requests (ICI) from the ICF Hitachi 289...
Page 301: Free-Running Timer Control/Status Register (Ftcsr)
Bit name: — — — OCFA OCFB CCLRA Initial value: R/W: R/(W)* — — — R/(W)* R/(W)* R/(W)* Note: For bits 7, and 3 to 1, the only value that can be written is 0 (for clearing the flags). 290 Hitachi...
Page 302 OCRB match. This flag is cleared by the software and set by the hardware. It cannot be set by software. Bit 2 (OCFB) Description Clear conditions: When OCFB = 1, OCFB is read and then 0 written to it (initial value) Set conditions: When FRC value becomes equal to OCRB Hitachi 291...
Page 303: Timer Control Register (Tcr)
Bit 7: Input edge select (IEDG). IEDG selects whether to capture the input capture input (FTI) on the falling edge or rising edge. Bit 7: IEDG Description Captures input on falling edge (initial value) Captures input on rising edge 292 Hitachi...
Page 304: Timer Output Compare Control Register (Tocr)
Bit 4: Output compare register select (OCRS). These bits share the same address as OCRA and OCRB. The OCRS bit controls which register is selected when reading/writing to this address. It does not affect the operation of OCRA and OCRB. Bit 4 (OCRS) Description Selects OCRA register (initial value) Selects OCRB register Hitachi 293...
Page 305 Bit 0: Output level B (OLVLB). Selects the output level that is output to the output compare B output pin upon compare match B (signal indicating match of FRC and OCRB). Bit 0 (OLVLB) Description Outputs 0 on compare match B (initial value) Outputs 1 on compare match B 294 Hitachi...
Page 306: Cpu Interface
Figure 11.2 and 11.3 show the flow of data when FRC is accessed. Other registers function the same way. When reading OCRA and OCRB, however, data is transferred directly to the CPU without passing through TEMP for both the upper and lower bytes. Hitachi 295...
Page 307 Note: For a CPU writing [H'AA55] to FRC Figure 11.2 FRC Access Operation (Write) 296 Hitachi...
Page 308 Note: For an FRC reading from a CPU [H'AA55] Figure 11.3 FRC Access Operation (Read) Hitachi 297...
Page 309: Operation
The external clock begins counting on the rising edge. The pulse width of the external clock must be at least 6 system clocks (φ). A smaller pulse width results in operation that is not always accurate. Figures 11.5 shows the timing. Figure 11.5 Count Timing (External Clock Operating) 298 Hitachi...
Page 310: Output Timing For Output Compare
Note: ↓ Indicates instruction execution by software Figure 11.6 Output Timing for Output Compare A 11.4.3 FRC Clear Timing The FRC can be cleared on compare match A. Figure 11.7 shows the timing. Figure 11.7 Compare Match A Clear Timing Hitachi 299...
Page 311: Input Capture Input Timing
When the FICR is read (upper byte read) and the input capture signal is input, the input capture signal is delayed one cycle of the clock that drives the timer. Figure 11.9 shows the timing. Note: When FICR is read and input capture input is input Figure 11.9 Input Capture Signal Timing 300 Hitachi...
Page 312: Input Capture Flag (Icf) Set Timing
(at the timing for updating the count value that matched the FRC). After OCRA or OCRB matches the FRC, no compare match signal is generated until the increment lock is generated. Figure 11.11 shows the timing for OCFA and OCFB. Hitachi 301...
Page 313: Timer Overflow Flag (Ovf) Set Timing
Figure 11.12 OVF Setting Timing 11.5 Interrupt Sources There are four FRT interrupt sources of three types (ICI, OCIA/OCIB, and OVI). Table 11.3 lists priorities for interrupt sources and clearing resets. The interrupt enable bits of the TIER are used to 302 Hitachi...
Page 314: Interrupt Sources
Set the CCLRA bit of the FTCSR to 1. OLVLA and OLVLB bits are inverted by software whenever a compare match occurs. Figure 11.13 Example of Pulse Output 11.7 Notes on Use Be aware that the following contention and operations occur when the FRT is operating: Hitachi 303...
Page 315 Contention between FRC Writes and Increments When an increment occurs with the timing shown in figure 11.15 during the write cycle for the lower byte of the FRC, no increment is performed and the counter write takes priority. 304 Hitachi...
Page 316 Contention between OCR Writes and Compare Matches When a compare match occurs with the timing shown in figure 11.16, during the write cycle for the lower byte of the OCRA and OCRB, the OCR write takes priority and the compare match signal is disabled. Hitachi 305...
Page 317 FRC clock is generated, causing the FRC to begin incrementing. The FRC will also start incrementing when switching between an internal clock and an external clock. 306 Hitachi...
Page 318 Table 11.4 Internal Clock Switching and FRC Operation Timing of Rewrite of CKS1 and CKS0 Bits FRC Operation Low to low switch Low to high switch Hitachi 307...
Page 319 Timer Output (FTOA, FTOB) During a reset that occurs while the power supply is coming up, the timer outputs (FTOA, FTOB) will be unreliable until the oscillation stabilizes. The initial value is output after the oscillation settling time has elapsed. 308 Hitachi...
Page 320: Section 12 Watchdog Timer (Wdt)
12.1 Overview The SH7095 microprocessor has a single-channel watchdog timer (WDT) for monitoring system operations. If a system becomes uncontrolled and the timer counter overflows without being rewritten correctly by the CPU, an overflow signal (WDTOVF) is output externally. The WDT can simultaneously generate an internal reset signal for the entire chip.
Page 321: Block Diagram
(power-on or manual resets). Figure 12.1 WDT Block Diagram 12.1.3 Pin Configuration Table 12.1 lists the pin configuration. Table 12.1 Pin Configuration Abbreviation Function Watchdog timer overflow WDTOVF Outputs the counter overflow signal in the watchdog mode 310 Hitachi...
Page 322: Register Configuration
WT/IT bit of the WTCSR. The WTCNT is initialized to H'00 by a reset and when the TME bit is cleared to 0. It is not initialized in the standby mode. Bit: Bit name: Initial value: R/W: Hitachi 311...
Page 323: Watchdog Timer Control/Status Register (Wtcsr)
Interval timer mode: interval timer interrupt (ITI) request to the CPU when WTCNT overflows (initial value) Watchdog timer mode: WDTOVF signal output externally when WTCNT overflows. Section 12.2.3, Reset Control/Status Register (RSTCSR), describes in detail what happens when WTCNT overflows in the watchdog timer mode. 312 Hitachi...
Page 324: Reset Control/Status Register (Rstcsr)
Register Access, for details. RSTCR is initialized to H'1F by input of a reset signal from the RES pin, but is not initialized by the internal reset signal generated by the overflow of the WDT. It is initialized to H'1F in standby mode. Hitachi 313...
Page 325: Register Access
Bits 4 to 0: Reserved. These bits always read as 1, and can not be modified. 12.2.4 Register Access The watchdog timer’s WTCNT, WTCSR, and RSTCSR registers differ from other registers in that they are more difficult to write. The procedures for writing and reading these registers are given below. 314 Hitachi...
Page 326 RSTS bits, respectively. The WOVF bit is not affected. Writing 0 to the WOVF bit Address: H'FFFFFE82 H'A5 H'00 Writing to the RSTE and RSTS bits Address: H'FFFFFE82 H'5A Write data Figure 12.3 Writing to the RSTCSR Hitachi 315...
Page 327: Operation
When a watchdog reset is generated simultaneously with input at the RES pin, the software distinguishes the RES reset from the watchdog reset by checking the WOVF bit in the RSTCSR. The RES reset takes priority. The WOVF bit is cleared to 0. 316 Hitachi...
Page 328 WT/IT: Timer mode select bit TME: Timer enable bit Note: Internal reset signal occurs only when the RSTE bit is set Figure 12.4 Operation in the Watchdog Timer Mode Hitachi 317...
Page 329: Operation In The Interval Timer Mode
H'FF to H'00) the system clock (φ) is presumed to be stable and usable; clock signals are supplied to the entire chip and the standby mode ends. For details on the standby mode, see section 2.5.2, Power Down States. 318 Hitachi...
Page 330: Timing Of Setting The Overflow Flag (Ovf)
When the WTCNT overflows the WOVF bit of the RSTCSR is set to 1 and a WDTOVF signal is output. When the RSTE bit is set to 1, WTCNT overflow enables an internal reset signal to be generated for the entire chip (figure 12.7). Figure 12.7 Timing of Setting the WOVF Bit and Internal Reset Hitachi 319...
Page 331: Notes On Use
CKS2 to CKS0. 12.4.3 Changing Watchdog Timer/Interval Timer Modes To prevent incorrect operation, always stop the watchdog timer (by clearing the TME bit to 0) before switching between interval timer mode and watchdog timer mode. 320 Hitachi...
Page 332: System Reset With Wdtovf
Internal Reset With the Watchdog Timer If the RSTE bit is cleared to 0 in the watchdog timer mode, the LSI will not reset internally when a WTCNT overflow occurs, but the WTCNT and WTCSR in the WDT will reset. Hitachi 321...
Page 333 322 Hitachi...
Page 334: Section 13 Serial Communication Interface
Section 13 Serial Communication Interface 13.1 Overview The SH7095 has a serial communication interface (SCI) that supports both asynchronous and clocked synchronous serial communication. It also has a multiprocessor communication function for serial communication among two or more processors. 13.1.1 Features Select asynchronous or clock synchronous as the serial communications mode.
Page 335: Block Diagram
Pin Configuration Table 13.1 summarizes the SCI pins by channel. Table 13.1 SCI Pins Pin Name Abbreviation Input/Output Function Serial clock pin Input/output Clock input/output Receive data pin Input Receive data input Transmit data pin Output Transmit data output 324 Hitachi...
Page 336: Register Configuration
The RSR is then ready to receive the next data. This double buffering allows the SCI to receive data continuously. The CPU can read but not write the RDR. The RDR is initialized to H'00 by a reset or in standby or module standby modes. Hitachi 325...
Page 337: Transmit Shift Register
Bit: Bit name: Initial value: R/W: 13.2.5 Serial Mode Register The serial mode register (SMR) is an eight-bit register that specifies the SCI serial communication format and selects the clock source for the baud rate generator. 326 Hitachi...
Page 338 The O/E setting is used only in asynchronous mode and only when the parity enable bit (PE) is set to 1 to enable parity addition and check. The O/E setting is ignored in the clocked synchronous mode, or in the asynchronous mode when parity addition and check is disabled. Hitachi 327...
Page 339 Bits 1 and 0: Clock select 1 and 0 (CKS1 and CKS0). These bits select the internal clock source of the on-chip baud rate generator. Four clock sources are available. φ/4, φ/16, φ/64 and φ/256. For further information on the clock source, bit rate register settings, and baud rate, see section 13.2.8, Bit Rate Register. 328 Hitachi...
Page 340: Serial Control Register
Transmit-data-empty interrupt request (TXI) is disabled (initial value). The TXI interrupt request can be cleared by reading TDRE after it has been set to 1, then clearing TDRE to 0, or by clearing TIE to 0. Transmit-data-empty interrupt request (TXI) is enabled Hitachi 329...
Page 341 Receiver enabled. Serial reception starts when a start bit is detected in the asynchronous mode, or synchronous clock input is detected in the clocked synchronous mode. Select the receive format in the SMR before setting RE to 1. 330 Hitachi...
Page 342 (CKE1 = 1). Select the SCI operating mode in the serial mode register (SMR) before setting CKE1 and CKE0. For further details on selection of the SCI clock source, see table 13.9 in section 13.3, Operation. Hitachi 331...
Page 343: Serial Status Register
Note: The only value that can be written is a 0 to clear the flag. • Bit 7: Transmit data register empty (TDRE). Indicates that the SCI has loaded transmit data from the TDR into the TSR and serial transmit new data can be written in the TDR. 332 Hitachi...
Page 344 Serial receiving cannot continue while ORER is set to 1. In the clocked synchronous mode, serial transmitting is disabled. • Bit 4: Framing error (FER). Indicates that data reception ended abnormally due to a framing error in the asynchronous mode. Hitachi 333...
Page 345 Bit 2: Transmit end (TEND). Indicates that when the last bit of a serial character was transmitted, the TDR did not contain valid data, so transmission has ended. TEND is a read- only bit and cannot be written. 334 Hitachi...
Page 346 The MPBT setting is ignored in the clocked synchronous mode, when a multiprocessor format is not selected, or when the SCI is not transmitting. Bit 0: MPBT Description Multiprocessor bit value in transmit data is 0 (initial value). Multiprocessor bit value in transmit data is 1. Hitachi 335...
Page 347: Bit Rate Register (Brr)
The CPU can always read and write the BRR. The BRR is initialized to H'FF by a reset or in standby mode. Bit: Bit name: Initial value: R/W: Table 13.3 shows examples of BRR settings in the asynchronous mode; table 13.4 shows examples of BBR settings in the clocked synchronous mode. 336 Hitachi...
Page 348 2400 0.16 0.00 0.16 0.00 4800 –2.34 0.00 0.16 0.00 9600 –2.34 0.00 0.16 0.00 19200 –2.34 0.00 — — — 0.00 31250 0.00 — — — 0.00 –1.70 38400 — — — 0.00 — — — 0.00 Hitachi 337...
Page 349 0.16 0.00 0.46 1200 0.16 0.16 0.00 -0.08 2400 0.16 0.16 0.00 0.46 4800 –1.36 0.16 0.00 -0.61 9600 1.73 –2.34 0.00 1.55 19200 1.73 –2.34 0.00 -2.68 31250 0.00 0.00 2.40 2.50 38400 1.73 –2.34 0.00 -2.68 338 Hitachi...
Page 350 N: BRR setting for baud rate generator (0 ≤ N ≤ 255) φ: φ frequency (MHz) n: baud rate generator clock source (n = 0, 1, 2, 3) (for the clock sources and values of n, see table 13.6.) Hitachi 339...
Page 351 Table 13.6 Maximum Bit Rates for Various Frequencies with Baud Rate Generator (Asynchronous Mode) Settings (MHz) Maximum Bit Rate (bits/s) 31250 4.9152 38400 62500 9.8304 76800 93750 14.7456 115200 125000 19.6608 153600 156250 187500 24.576 192000 28.7 224218 340 Hitachi...
Page 352: Operation
(SMR), as shown in table 13.9. The SCI clock source is selected by the C/A bit in the serial mode register (SMR) and the CKE1 and CKE0 bits in the serial control register (SCR), as shown in table 13.10. Hitachi 341...
Page 353 — When an internal clock is selected, the SCI operates using the on-chip baud rate generator, and outputs a synchronous clock signal to external devices. — When an external clock is selected, the SCI operates on the input synchronous clock. The on-chip baud rate generator is not used. 342 Hitachi...
Page 354 External Inputs a clock with frequency 16 times the bit rate Clocked synch- 1 Internal Outputs the synchronous clock ronous mode External Inputs the synchronous clock Note: Select the function in combination with the pin function controller (PFC). Hitachi 343...
Page 355: Operation In Asynchronous Mode
The SCI samples each data bit on the eighth pulse of a clock with a frequency 16 times the bit rate. Receive data is latched at the center of each bit. Example: 8-bit data with parity and two stop bits Figure 13.2 Data Format in Asynchronous Communication 344 Hitachi...
Page 356 C/A bit in the serial mode register (SMR) and bits CKE1 and CKE0 in the serial control register (SCR) (table 13.9). When an external clock is input at the SCK pin, it must have a frequency equal to 16 times the desired bit rate. Hitachi 345...
Page 357 (SCR) to 1. Also set RIE, TIE, TEIE and MPIE as necessary. Setting TE or RE enables the SCI to use the TxD or RxD pin. The initial states are the mark transmit state, and the idle receive state (waiting for a start bit). 346 Hitachi...
Page 358 1); if so, write data in TDR, then clear TDRE to 0. When the DMAC is started by a transmit-data-empty interrupt request (TXI) in order to write data in TDR, the TDRE bit is checked and cleared automatically. To output a break at the end of serial transmission, clear TE to 0 in SCR. Hitachi 347...
Page 359 Note: Circled numbers refer to the preceding procedure. Figure 13.5 Sample Flowchart for Transmitting Serial Data 348 Hitachi...
Page 360 1 bits (marking). If the transmit-end interrupt enable bit (TEIE) in the SCR is set to 1, a transmit-end interrupt (TEI) is requested. Figure 13.6 shows an example of SCI transmit operation in the asynchronous mode. Hitachi 349...
Page 361 To continue receiving serial data. read the RDRF and RDR bits and clear RDRF to 0 before the stop bit of the current frame is received. If the DMAC is started by a receive-data-full interrupt (RXI) to read RDR, the RDRF bit is cleared automatically so this step is unnecessary. 350 Hitachi...
Page 362 Note: Circled numbers refer to the preceding procedure. Figure 13.7 Sample Flowchart for Receiving Serial Data Hitachi 351...
Page 363 Note: Circled numbers refer to the preceding procedure. Figure 13.7 Sample Flowchart for Receiving Serial Data (cont) In receiving, the SCI operates as follows: The SCI monitors the receive data line. When it detects a start bit (0), the SCI synchronizes internally and starts receiving. 352 Hitachi...
Page 364 RDRF is still set to 1 in SSR from RSR into RDR Framing error Stop bit is 0 Receive data loaded from RSR into RDR Parity error Parity of receive data differs from Receive data loaded from even/odd parity setting in SMR RSR into RDR Hitachi 353...
Page 365: Multiprocessor Communication
Processors with IDs not matching the received data skip further incoming data until they again receive data with the multiprocessor bit set to 1. Multiple processors can send and receive data in this way. Figure 13.9 shows the example of communication among processors using the multiprocessor format. 354 Hitachi...
Page 366 To output a break at the end of serial transmission. set the data register (DR) of the port to 0, then clear TE to 0 in SCR and set the TxD pin function as output port with the PFC. Hitachi 355...
Page 367 Note: Circled numbers refer to the preceding procedure. Figure 13.10 Sample Flowchart for Transmitting Multiprocessor Serial Data 356 Hitachi...
Page 368 If TDRE is 1, the SCI sets the TEND bit in the SSR to 1, outputs the stop bit, then continues output of 1 bits in the marking state. If the transmit-end interrupt enable bit (TEIE) in the SCR is set to 1, a transmit-end interrupt (TEI) is requested at this time. Hitachi 357...
Page 369 1. When a framing error occurs, the RxD pin can be read to detect the break state. SCI status check and data receiving: read SSR, check that RDRF is set to 1, then read data from the receive data register (RDR). 358 Hitachi...
Page 370 Figure 13.12 Sample Flowchart for Receiving Multiprocessor Serial Data Hitachi 359...
Page 371 Figure 13.12 Sample Flowchart for Receiving Multiprocessor Serial Data (cont) 360 Hitachi...
Page 372 Figure 13.13 shows an example of SCI receive operation using a multiprocessor format. Example: Own ID does not match data, 8-bit data with multiprocessor bit and one stop bit Figure 13.13 SCI Receive Operation Hitachi 361...
Page 373: Clocked Synchronous Operation
The transmitter and receiver are also double buffered, so continuous transmitting or receiving is possible by reading or writing data while transmitting or receiving is in progress. Figure 13.14 shows the general format in clocked synchronous serial communication. 362 Hitachi...
Page 374 After loading the data from the TDR into the TSR, the SCI sets the TDRE bit to 1 and starts transmitting. If the transmit-data-empty interrupt enable bit (TIE) in the SCR is set to 1, the SCI requests a transmit-data-empty interrupt (TXI) at this time. Hitachi 363...
Page 375 (TSR). Clearing RE to 0, however, does not initialize the RDRF, PER, FER, and ORER flags and receive data register (RDR), which retain their previous contents. Figure 13.16 is a sample flowchart for initializing the SCI. The procedure for initializing the SCI is listed below. 364 Hitachi...
Page 376 The procedure for transmitting serial data is listed below. SCI status check and transmit data write. read the serial status register (SSR), check that the TDRE bit is 1, then write transmit data in the transmit data register (TDR) and clear TDRE to 0. Hitachi 365...
Page 377 ORER, PER, and FER are cleared to 0. If PER or FER is set to 1, the RDRF bit will not be set and both transmitting and receiving will be disabled. Figure 13.19 shows an example of the SCI receive operation. The procedure for receiving serial data is listed below: 366 Hitachi...
Page 378 7) of the current frame is received. If the DMAC is started by a receive-data-full interrupt (RXI) to read RDR, the RDRF bit is cleared automatically so this step is unnecessary. Figure 13.18 Sample Flowchart for Serial Receiving Hitachi 367...
Page 379 Receive data is shifted into the RSR in order from the LSB to the MSB. After receiving the data, the SCI checks that RDRF is 0 so that receive data can be loaded from the RSR into the 368 Hitachi...
Page 380 0 before the MSB (bit 7) of the current frame is transmitted. When the DMAC is started by a transmit-data-empty interrupt request (TXI) to write data in TDR, the TDRE bit is checked and cleared automatically. When the DMAC is started by a receive-data-full interrupt (RXI) to read RDR, the RDRF bit is cleared automatically. Hitachi 369...
Page 381 Note: In switching from transmitting or receiving to simultaneous transmitting and receiving, clear both TE and RE to 0, then set both TE and RE to 1. Figure 13.20 Sample Flowchart for Serial Transmitting 370 Hitachi...
Page 382: Sci Interrupt Sources And The Dmac
If new data is written in the TDR when TDRE is 0, however, the old data stored in the TDR will be lost because the data has not yet been transferred to the TSR. Before writing transmit data to the TDR, be sure to check that TDRE is set to 1. Hitachi 371...
Page 383 SCI operates on a base clock of 16 times the bit rate frequency. In receiving, the SCI synchronizes internally with the falling edge of the start bit, which it samples on the base clock. Receive data is latched on the rising edge of the eighth base clock pulse. See figure 13.21. 372 Hitachi...
Page 384 From equation (1), if F = 0 and D = 0.5 the receive margin is 46.875%, as given by equation 2. Equation 2. D = 0.5, F = 0 M = (0.5 – 1/(2 × 16)) × 100% = 46.875% This is a theoretical value. A reasonable margin to allow in system designs is 20–30%. Hitachi 373...
Page 385 Caution for Clocked Synchronous Internal Clock Mode: When receiving, RDRF is 1 when RE is set to zero 1.5 clocks after the rising edge of the RxD D7 bit SCK output, but it cannot be copied to RDR. 374 Hitachi...
Page 386: Section 14 Power-Down Modes
14.1.1 Power-Down Modes In addition to the sleep mode and standby mode, the SH7095 also has a third power-down mode, the module standby function, which halts the DMAC, multiplication unit, division unit, free- running timer, and SCI on-chip peripheral modules.
Page 387: Register
14.1.2 Register Table 14.2 lists the register configuration. Table 14.2 Register Configuration Name Abbreviation Initial Value Address Standby control register SBYCR H'60 H'FFFFFE91 376 Hitachi...
Page 388: Description Of Register
When the clock halts, the DMAC retains its pre-halt state. When MSTP4 is cleared to 0 and the DMAC begins running again, its starts operating from its pre-halt state. Set this bit while the DMAC is halting since this bit cannot be set while the DMAC is operating (transferring). Hitachi 377...
Page 389 SCI is halted. When the clock halts, all SCI registers except the interrupt vector, which holds the previous value, are initialized. When MSTP0 is cleared to 0 and the SCI begins running again, its starts operating from its initial state. 378 Hitachi...
Page 390: Sleep Mode
SLEEP instruction is executed. In the standby mode, power consumption is greatly reduced by halting not only the CPU, but the clock and on-chip peripheral modules as well. CPU register contents are held, and some on-chip peripheral modules are initialized. Hitachi 379...
Page 391: Canceling The Standby Mode
NMI exception processing begins. Cancellation by a Power-On Reset: A power-on reset cancels the standby mode. Cancellation by a Manual Reset: A manual reset cancels the standby mode. 380 Hitachi...
Page 392: Standby Mode Cancellation By Nmi
When the clock is input from the CKIO pin, the clock frequency can be modified or the clock stopped. The SH7095 has a CKPREQ/CKM pin. The clock pause function is used as described below. Note that the clock pauses are not accepted while the watchdog timer (WDT) is operating (i.e., when the timer enable bit (TME) of the WDT’s timer control/status register (WTCSR) is 1).
Page 393 The standby state, all internal functions and all pin states during clock pause are equivalent to those of the normal standby mode. Figure 14.2 shows the timing chart of the clock pause function. Figure 14.2 Clock Pause Function Timing 382 Hitachi...
Page 394: Notes On Standby Mode
14.4.5 Notes on Standby Mode (1) Disable the cache before transitting to the standby mode when the SH7095 enters the standby mode during using the cache. Initialize the cache beforehand when the cache is used after returning to the standby mode. The value of the on-chip RAM is not held in the standby mode although the cache is used as the on-chip RAM.
Page 395 384 Hitachi...
Page 396: Section 15 Electrical Characteristics
–0.3 to +7.0 Input voltage –0.3 to V + 0.3 Operating temperature Topr -200 to +75 ˚C Storage temperature Tstg –55 to +125 ˚C Caution: Operating the chip in excess of the absolute maximum rating may result in permanent damage. Hitachi 385...
Page 397: Dc Characteristics
Output low All output pins — — = 1.6 mA level voltage Input — — Vin = 0 V capaci- f = 1 MHz — — tance Ta = 25°C All other input — — pins (D31–D0) 386 Hitachi...
Page 398 Output low-level permissible current (total) — — Output high-level permissible current (per pin) –I — — Output high-level permissible current (total) –∑ I — — Caution: To ensure LSI reliability, do not exceed the value for output current given in table 15.3. Hitachi 387...
Page 399: Ac Characteristics
15.4 OSC2 Software standby oscillation settling time 2 t — 15.5 OSC3 PLL synchronization settling time — µs 15.6 Notes: 1. With PLL circuit 1 operating. 2. With PLL circuit 1 not used. Figure 15.1 CKIO Input Timing 388 Hitachi...
Page 400 Note: External clock input from EXTAL pin. Figure 15.2 EXTAL Clock Input Timing Note: Oscillation settling time when on-chip clock pulse generator is used. Figure 15.3 Oscillation Settling Time at Power-On Hitachi 389...
Page 401 Note: Oscillation settling time when on-chip clock pulse generator is used. Figure 15.4 Oscillation Settling Timing at Standby Return (via RESET) Note: Oscillation settling time when on-chip clock pulse generator is used. Figure 15.5 Oscillation Settling Timing at Standby Return (via NMI) 390 Hitachi...
Page 402 Figure 15.6 PLL Synchronization Settling Timing Hitachi 391...
Page 403: Control Signal Timing
The RES, NMI and /IRL3-/IRL0 signals are asynchronous inputs, but when the setup times shown here are provided, the signals are considered to have produced changes at clock fall. If the setup times are not provided, recognition is delayed until the next clock fall. 392 Hitachi...
Page 404 BOFF2 15.12 Bus buffer on time 2 (PLL on, 1/4 cycle delay) 3/4 tcyc 3/4 tcyc + 18 ns BON2 Bus tri-state delay time 3 (PLL off) 15.11, BOFF3 15.13 Bus buffer on time 3 (PLL off) BON3 Hitachi 393...
Page 405 Figure 15.7 Reset Input Timing Figure 15.8 Interrupt Signal Input Timing (With PLL1 Off) 394 Hitachi...
Page 406 Figure 15.9 Interrupt Signal Input Timing (With PLL1 On) Figure 15.10 Bus Release Timing (Master Mode With PLL1 On) Hitachi 395...
Page 407 Figure 15.11 Bus Release Timing (Master Mode With PLL1 Off) Figure 15.12 Bus Release Timing (Slave Mode, With PLL1 On) 396 Hitachi...
Page 408 Figure 15.13 Bus Release Timing (Slave Mode, With PLL1 Off) Hitachi 397...
Page 409: Bus Timing
Write data delay time 1 15.15, 15.27, 15.41, 15.53 Write data hold time 1 — 15.15, 15.27, 15.41, WDH1 15.53 Data buffer on time — 15.15, 15.27, 15.41, 15.53 Data buffer off time — 15.15, 15.27, 15.41, 15.53 398 Hitachi...
Page 410 Address input hold time — 15.71 AHIN BS input setup time — 15.71 BS input hold time — 15.71 Read write input setup time — 15.71 Read write input hold time — 15.71 Address hold time 1 — 15.15 Hitachi 399...
Page 411 1/4 tcyc + 3 — 15.15, 15.27, 15.41, WDH1 15.53 Data buffer on time — 1/4 tcyc + 18 ns 15.15, 15.27, 15.41, 15.53 Data buffer off time — 1/4 tcyc + 18 ns 15.15, 15.27, 15.41, 15.53 400 Hitachi...
Page 412 BS input hold time 1/4 tcyc + 3 — 15.71 Read write input setup time t 15 - 1/4 tcyc — 15.71 Read write input hold time 1/4 tcyc + 3 — 15.71 Address hold time 1 — 15.15 Hitachi 401...
Page 413 WDH1 15.61 Write data hold time 2 15.17 WDH2 Write data hold time 3 15.61 WDH3 DACK delay time 1 — 15.16, 15.38, 15.47, DACD1 15.60, 15.67 DACK delay time 3 — 15.16, 15.38, 15.47, DACD3 15.60, 15.67 402 Hitachi...
Page 414 Data buffer on time — 15.17, 15.39, 15.48, 15.61 Data buffer off time — 15.17, 15.39, 15.48, 15.61 Note: When a master and slave are connected with the PLL off, the external address monitor will not function properly at 28.7 MHz. Hitachi 403...
Page 415 Write data hold time 2 — 15.17 WDH2 Write data hold time 3 — 15.61 WDH3 DACK delay time 1 — 15.16, 15.38, 15.47, DACD1 15.60, 15.67 DACK delay time 3 — 15.16, 15.38, 15.47, DACD3 15.60, 15.67 404 Hitachi...
Page 416 Data buffer off time — 15.17, 15.39, 15.48, 15.61 Address hold time 1 — 15.15 Note: When a master and slave are connected with the PLL off, the external address monitor will not function properly at 28.7 MHz. Hitachi 405...
Page 417 Dotted lines indicate a synchronous DRAM is connected. is defined by the faster of CSn and RD. RDH2 The DACKn waveform shown is for the case where active high has been specified. Figure 15.14 Basic Read Cycle (No Waits, PLL On) 406 Hitachi...
Page 418 Notes: 1. Dotted lines indicate a synchronous DRAM is connected. The DACKn waveform shown is for the case where active high has been specified. Figure 15.15 Basic Write Cycle (No Waits, PLL On) Hitachi 407...
Page 419 Dotted lines indicate a synchronous DRAM is connected. is defined by the faster of CSn and RD. RDH2 The DACKn waveform shown is for the case where active high has been specified. Figure 15.16 Basic Read Cycle (No Waits, PLL Off) 408 Hitachi...
Page 420 Notes: 1. Dotted lines indicate a synchronous DRAM is connected. The DACKn waveform shown is for the case where active high has been specified. Figure 15.17 Basic Write Cycle (No Waits, PLL Off) Hitachi 409...
Page 421 Notes: 1. Dotted lines indicate a synchronous DRAM is connected. The DACKn waveform shown is for the case where active high has been specified. Figure 15.18 Basic Bus Cycle (1 Wait Cycle) 410 Hitachi...
Page 422 Notes: 1. Dotted lines indicate a synchronous DRAM is connected. The DACKn waveform shown is for the case where active high has been specified. Figure 15.19 Basic Bus Cycle (External Wait Input) Hitachi 411...
Page 423 Dotted lines indicate a synchronous DRAM in another CS space is connected. The DACKn waveform shown is for the case where active high has been specified. Figure 15.20 Synchronous DRAM Read Bus Cycle (PLL On, 4 Bursts, CAS Latency =1, RCD = 1 Cycle) 412 Hitachi...
Page 424 Note: Dotted lines indicate a synchronous DRAM in another CS space is connected. Figure 15.21 Synchronous DRAM Single Read Bus Cycle (RCD = 1 Cycle, CAS Latency = 1 Cycle, Bursts = 4, PLL On) Hitachi 413...
Page 425 Dotted lines indicate a synchronous DRAM in another CS space is connected. The DACKn waveform shown is for the case where active high has been specified. Figure 15.22 Synchronous DRAM Read Bus Cycle (RCD = 2 Cycle, CAS Latency = 2 Cycle, Bursts = 4) 414 Hitachi...
Page 426 Note: 1. The DACKn waveform shown is for the case where active high has been specified. Figure 15.23 Synchronous DRAM Read Bus Cycle (Bank Active, Same Row Access, CAS Latency = 1 Cycle) Hitachi 415...
Page 427 Note: 1. The DACKn waveform shown is for the case where active high has been specified. Figure 15.24 Synchronous DRAM Read Bus Cycle (Bank Active, Same Row Access, CAS Latency = 1 Cycle) 416 Hitachi...
Page 428 The DACKn waveform shown is for the case where active high has been specified. Figure 15.25 Synchronous DRAM Read Bus Cycle (Bank Active, Different Row Access, TRP = 1 Cycle, RCD = 1 Cycle, CAS Latency = 1 Cycle) Hitachi 417...
Page 429 The DACKn waveform shown is for the case where active high has been specified. Figure 15.26 Synchronous DRAM Read Bus Cycle (Bank Active, Different Row Access, TRP = 2 Cycles, RCD = 1 Cycle, CAS Latency = 1 Cycle) 418 Hitachi...
Page 430 Dotted lines indicate a synchronous DRAM in another CS space is accessed. The DACKn waveform shown is for the case where active high has been specified. Figure 15.27 Synchronous DRAM Read Bus Cycle (RCD = 1 Cycle, TRWL = 1 Cycle, PLL On) Hitachi 419...
Page 431 Dotted lines indicate a synchronous DRAM in another CS space is accessed. The DACKn waveform shown is for the case where active high has been specified. Figure 15.28 Synchronous DRAM Read Bus Cycle (RCD = 2 Cycles, TRWL = 2 Cycles) 420 Hitachi...
Page 432 Note: 1. The DACKn waveform shown is for the case where active high has been specified. Figure 15.29 Synchronous DRAM Write Bus Cycle (Bank Active, Same Row Access) Hitachi 421...
Page 433 Note: 1. The DACKn waveform shown is for the case where active high has been specified. Figure 15.30 Synchronous DRAM Consecutive Write Cycle (Bank Active, Same Row Access) 422 Hitachi...
Page 434 Note: 1. The DACKn waveform shown is for the case where active high has been specified. Figure 15.31 Synchronous DRAM Write Bus Cycle (Bank Active, Different Row Access, TRP = 1 Cycle, RCD = 1 Cycle) Hitachi 423...
Page 435 Note: 1. The DACKn waveform shown is for the case where active high has been specified. Figure 15.32 Synchronous DRAM Write Bus Cycle (Bank Active, Different Row Access, TRP = 2 Cycles, RCD = 2 Cycles) 424 Hitachi...
Page 436 Figure 15.33 Synchronous DRAM Mode Register Write Cycle (TRP = 1 Cycle) Hitachi 425...
Page 437 Figure 15.34 Synchronous DRAM Mode Register Write Cycle (TRP = 2 Cycles) 426 Hitachi...
Page 438 Note: Always put in a precharge cycle before the auto-refresh cycle. The TRP determines how many cycles prior it should be placed. Figure 15.35 Synchronous DRAM Auto Refresh Cycle (TRAS = 2 Cycles) Hitachi 427...
Page 439 Figure 15.36 Synchronous DRAM Auto-Refresh Cycle (Shown From Precharge Cycle, TRP = 1 Cycle, TRAS = 2 Cycles) 428 Hitachi...
Page 440 Note: Always put in a precharge cycle before the auto-refresh cycle. The TRP determines how many cycles prior it should be placed. Figure 15.37 Synchronous DRAM Self-Refresh Cycle (TRAS = 2) Hitachi 429...
Page 441 The DACKn waveform shown is for the case where active high has been specified. Figure 15.38 Synchronous DRAM Read Bus Cycle (RCD = 1 Cycle, CAS Latency = 1 Cycle, TRP = 1 Cycle, Bursts = 4, PLL = Off) 430 Hitachi...
Page 442 Dotted lines indicate a synchronous DRAM in another CS space is connected. The DACKn waveform shown is for the case where active high has been specified. Figure 15.39 Synchronous DRAM Write Bus Cycle (RCD = 1 Cycle, TRP = 1 Cycle, PLL = Off) Hitachi 431...
Page 443 RD and CASxx rise. RDH5 The DACKn waveform shown is for the case where active high has been specified. Figure 15.40 DRAM Read Cycle (TRP = 1 Cycle, RCD = 1 Cycle, No Waits, PLL = On) 432 Hitachi...
Page 444 Note: 1. The DACKn waveform shown is for the case where active high has been specified. Figure 15.41 DRAM Write Cycle (TRP = 1 Cycle, RCD = 1 Cycle, No Waits, PLL = On) Hitachi 433...
Page 445 Note: 1. The DACKn waveform shown is for the case where active high has been specified. Figure 15.42 DRAM Bus Cycle (TRP = 2 Cycles, RCD = 2 Cycles, 1 Wait) 434 Hitachi...
Page 446 Note: 1. The DACKn waveform shown is for the case where active high has been specified. Figure 15.43 DRAM Bus Cycle (TRP = 1 Cycle, RCD = 1 Cycle, External Wait Input) Hitachi 435...
Page 447 RD and CASxx rise. RDH5 The DACKn waveform shown is for the case where active high has been specified. Figure 15.44 DRAM Burst Read Cycle (TRP = 1 Cycle, RCD = 1 Cycle, No Waits, PLL On) 436 Hitachi...
Page 448 Note: 1. The DACKn waveform shown is for the case where active high has been specified. Figure 15.45 DRAM Burst Write Cycle (TRP = 1 Cycle, RCD = 1 Cycle, No Waits, PLL On) Hitachi 437...
Page 449 Figure 15.46 DRAM CAS-Before-RAS Refresh Cycle (TRP = 1 Cycle, TRAS = 2 Cycles, PLL On) 438 Hitachi...
Page 450 RD and CASxx rise. RDH5 The DACKn waveform shown is for the case where active high has been specified. Figure 15.47 DRAM Bus Cycle (TRP = 1 Cycle, RCD = 1 Cycle, No Waits, PLL On) Hitachi 439...
Page 451 Note: 1. The DACKn waveform shown is for the case where active high has been specified. Figure 15.48 DRAM Write Cycle (TRP = 1 Cycle, RCD = 1 Cycle, No Waits, PLL Off) 440 Hitachi...
Page 452 RD and CASxx rise. RDH5 The DACKn waveform shown is for the case where active high has been specified. Figure 15.49 DRAM Burst Read Cycle (TRP = 1 Cycle, RCD = 1 Cycle, No Waits, PLL Off) Hitachi 441...
Page 453 Note: 1. The DACKn waveform shown is for the case where active high has been specified. Figure 15.50 DRAM Burst Write Cycle (TRP = 1 Cycle, RCD = 1 Cycle, No Waits, PLL Off) 442 Hitachi...
Page 454 Figure 15.51 DRAM CAS-Before-RAS Refresh Cycle (TRP = 1 Cycle, TRAS = 2 Cycles, PLL Off) Hitachi 443...
Page 455 Note: 1. The DACKn waveform shown is for the case where active high has been specified. Figure 15.52 Pseudo- SRAM Read Cycle (PLL On, TRP = 1 Cycles, TRCD = 1 Cycle, No Waits) 444 Hitachi...
Page 456 Note: 1. The DACKn waveform shown is for the case where active high has been specified. Figure 15.53 Pseudo-SRAM Write Cycle (PLL On, TRP = 1 Cycle, TRCD = 1 Cycle, No Waits) Hitachi 445...
Page 457 Note: 1. The DACKn waveform shown is for the case where active high has been specified. Figure 15.54 Pseudo-SRAM Bus Cycle (TRP = 2 Cycles, TRCD = 2 Cycles, 1 Wait) 446 Hitachi...
Page 458 Note: 1. The DACKn waveform shown is for the case where active high has been specified. Figure 15.55 Pseudo-SRAM Bus Cycle (TRP = 1 Cycle, TRCD = 1 Cycle, External Wait Input) Hitachi 447...
Page 459 Note: 1. The DACKn waveform shown is for the case where active high has been specified. Figure 15.56 Pseudo-SRAM Read Cycle (Nibble Access, PLL On, TRP = 1 Cycle, No Waits) 448 Hitachi...
Page 460 Note: 1. The DACKn waveform shown is for the case where active high has been specified. Figure 15.57 Pseudo-SRAM Write Cycle (Nibble Access, PLL On, TRP = 1 Cycle, TRCD = 1 Cycle, No Waits) Hitachi 449...
Page 461 Figure 15.58 Pseudo-SRAM Auto-Refresh Cycle (PLL On, TRP = 1 Cycle, TRAS = 2 Cycles) 450 Hitachi...
Page 462 Figure 15.59 Pseudo-SRAM Self-Refresh Cycle (PLL On, TRP = 1 Cycle, TRAS = 2 Cycles) Hitachi 451...
Page 463 Note: 1. The DACKn waveform shown is for the case where active high has been specified. Figure 15.60 Pseudo-SRAM Read Cycle (PLL Off, TRP = 1 Cycle, TRCD = 1 Cycle, No Waits) 452 Hitachi...
Page 464 Note: 1. The DACKn waveform shown is for the case where active high has been specified. Figure 15.61 Pseudo-SRAM Write Cycle (PLL Off, TRP = 1 Cycle, TRCD = 1 Cycle, No Waits) Hitachi 453...
Page 465 Note: 1. The DACKn waveform shown is for the case where active high has been specified. Figure 15.62 Pseudo-SRAM Read Cycle (Nibble Access, PLL Off, TRP = 1 Cycle, TRCD = 1 Cycle, No Waits) 454 Hitachi...
Page 466 Note: 1. The DACKn waveform shown is for the case where active high has been specified. Figure 15.63 Pseudo-SRAM Write Cycle (Nibble Access, PLL Off, TRP = 1 Cycle, TRCD = 1 Cycle, No Waits) Hitachi 455...
Page 467 Figure 15.64 Pseudo-SRAM Auto-Refresh Cycle (PLL Off, TRP = 1 Cycle, TRAS = 2 Cycles) 456 Hitachi...
Page 468 Figure 15.65 Pseudo-SRAM Self-Refresh Cycle (PLL Off, TRP = 1 Cycle, TRAS = 2 Cycles) Hitachi 457...
Page 469 Note: 1. The DACKn waveform shown is for the case where active high has been specified. Figure 15.66 Burst ROM Read Cycle (PLL On, 1 Wait) 458 Hitachi...
Page 470 Note: 1. The DACKn waveform shown is for the case where active high has been specified. Figure 15.67 Burst ROM Read Cycle (PLL Off, 1 Wait) Hitachi 459...
Page 471 Figure 15.68 Interrupt Vector Fetch Cycle (PLL On, No Waits) 460 Hitachi...
Page 472 Figure 15.69 Interrupt Vector Fetch Cycle (PLL Off, No Waits) Hitachi 461...
Page 473 Figure 15.70 Interrupt Vector Fetch Cycle (1 External Wait Cycle) 462 Hitachi...
Page 474 Figure 15.71 Address Monitor Cycle Hitachi 463...
Page 475: Dmac Timing
DRQS DREQ0, DREQ1 hold time (PLL Off, On) — DRQH DREQ0, DREQ1 hold time (PLL On, 1/4 cycle delay) 1/4 tcyc + 15 — DRQH DREQ0, DREQ1 low level width — DRQW Figure 15.72 DREQ0, DREQ1 Input Timing 464 Hitachi...
Page 476: Free-Running Timer Timing
Timer clock input setup time (PLL On, 1/4 cycle delay) t 80 –1/4 — TCKS tcyc Timer clock pulse width (single edge) — TCKWH Timer clock pulse width (both edges) — TCKWL Figure 15.73 FRT Input/Output Timing Figure 15.74 FRT Clock Input Timing Hitachi 465...
Page 477: Watchdog Timer Timing
= 5.0 V ±10%, Ta = -20 to +75°C) Item Symbol Unit Figure WDTOVF delay time (PLL Off, On) — 15.75 WOVD WDTOVF delay time (PLL On, 1/4 cycle — 1/4 tcyc + WOVD delay) Figure 15.75 Watchdog Timer Output Timing 466 Hitachi...
Page 478: Serial Communications Interface Timing
Transmission data delay time (clocked — 15.77 synchronization) Receive data setup time (clocked synchronization) t — Receive data hold time (clocked synchronization) t — Figure 15.76 Input Clock I/O Timing Figure 15.77 SCI I/O Timing (Clocked Synchronization Mode) Hitachi 467...
Page 479: Ac Characteristics Measurement Conditions
30 pF: CKIO, RAS, CAS , CKE, CS0-CS3 , BREQ, BACK, DACK0, DACK1, IVECF. 50 pF: All output pins other than the above. and I values are as shown in section 15.2, DC Characteristics, and table 15.3, Permitted Output Current Values. Figure 15.78 Output Load Circuit 468 Hitachi...
Page 480: Appendix A Pin States
CKPREQN CKPACKN System control RESET WDTOVF BACK, BRLS BREQ, BGR MD5-MD0 Interrupt IRL3–IRL0 IVECF Address bus A26–A0 Data bus D31–D0 Bus control CS3–CS0 RD, WR RAS, CE CAS, OE CASHH, DQMUU CASHL, DQMUL CASLH, DQMLU CASLL, DQMLL WAIT Hitachi 469...
Page 481 3. When the high impedance bit HIZ of the standby control register SBYCR is set to 1, the output pin becomes high impedance. Other: During sleep, if the DMAC is running, the address/data bus and bus control signals change according to the DMAC operation (likewise during refresh). 470 Hitachi...
Page 482: Appendix B List Of Register
– SERV6 SERV5 SERV4 SERV3 SERV2 SERV1 SERV0 VCRA INTC H'FFFFFE63 – SRXV6 SRXV5 SRXV4 SRXV3 SRXV2 SRXV1 SRXV0 H'FFFFFE64 – STXV6 STXV5 STXV4 STXV3 STXV2 STXV1 STXV0 VCRB H'FFFFFE65 – STEV6 STEV5 STEV4 STEV3 STEV2 STEV1 STEV0 Hitachi 471...
Page 483 – – – – – – H'FFFFFE9F Note*: Address at read. When writing, the WTCSR and WTCNT are H'FFFFFE80 and the RSTCSR is H'FFFFFE82. See Section 12.2.4, Register Access, in Section 12, watchdog Timer (WDT), for more information. 472 Hitachi...
Page 484 – – – H'FFFFFF0B – – – – – – OVFIE OVF H'FFFFFF0C – – – – – – – – H'FFFFFF0D – – – – – – – – VCRDIV H'FFFFFF0E H'FFFFFF0F H'FFFFFF10 H'FFFFFF11 DVDNTH H'FFFFFF12 H'FFFFFF13 Hitachi 473...
Page 485 BAB15 BAB14 BAB13 BAB12 BAB11 BAB10 BAB9 BAB8 BARBL H'FFFFFF63 BAB7 BAB6 BAB5 BAB4 BAB3 BAB2 BAB1 BAB0 H'FFFFFF64 BAMB3 BAMB3 BAMB2 BAMB2 BAMB2 BAMB2 BAMB2 BAMB2 (channel B) BAMRBH H'FFFFFF65 BAMB2 BAMB2 BAMB2 BAMB2 BAMB1 BAMB1 BAMB1 BAMB1 474 Hitachi...
Page 486 BDMB BDMB BDMB BDMB BDMB BDMB BDMB H'FFFFFF78 CMFC CMFP EBBE UMD – PCBA – – BRCR H'FFFFFF79 CMFC CMFP – SEQ DBEB PCBB – – H'FFFFFF7A – – – – – – – – – – H'FFFFFF7F Hitachi 475...
Page 487 – (channel 0) H'FFFFFF89 TCR0 H'FFFFFF8A H'FFFFFF8B H'FFFFFF8C H'FFFFFF8D CHCR0 H'FFFFFF8E H'FFFFFF8F H'FFFFFF90 H'FFFFFF91 SAR1 H'FFFFFF92 H'FFFFFF93 H'FFFFFF94 H'FFFFFF95 DMAC DAR1 H'FFFFFF96 (channel 1) H'FFFFFF97 H'FFFFFF98 – – – – – – – – H'FFFFFF99 TCR1 H'FFFFFF9A H'FFFFFF9B 476 Hitachi...
Page 488 – – – – – DMAOR H'FFFFFFB2 – – – – – – – – DMAC H'FFFFFFB3 – – – – NMIF DME (channels H'FFFFFFB4 0 and 1) – – – – – – – – – H'FFFFFFDF Hitachi 477...
Page 489 H'FFFFFFF4 – – – – – – – – H'FFFFFFF5 RTCNT H'FFFFFFF6 H'FFFFFFF7 H'FFFFFFF8 – – – – – – – – H'FFFFFFF9 RTCOR H'FFFFFFFA H'FFFFFFFB H'FFFFFFFC – – – – – – – – – – H'FFFFFFFF 478 Hitachi...
Page 490: Register Chart
B.2 Register Chart Hitachi 479...
Page 491 0 1 φ/16 Clock select 1 and 0 1 0 φ/64 (CKS1, CKS0) 1 1 φ/256 Bit rate register (BRR) H'FFFFFE01 Item Bit Name Initial Value Bit Name Description 7 to 0 (Bit rate setting) Sets serial transmit/receive bit rate 480 Hitachi...
Page 492 Clocked Internal clock, SCK pin used for synchronous mode synchronous clock input 1 1 Asynchronous mode Internal clock, SCK pin used for clock input Clocked Internal clock, SCK pin used for synchronous mode synchronous clock input Hitachi 481...
Page 493 RDRF after it has been set to 1, then writes 0 in RDRF, or the DMAC reads data from RDR. RDR contains valid received data. RDRF is set to 1 when serial data is received normally and transferred from RSR to RDR. 482 Hitachi...
Page 494 Multiprocessor bit value in receive data is 0 (initial value). (MPB) Multiprocessor bit value in receive data is 1. Multiprocessor bit Multiprocessor bit value in transmit data is 0 (initial transfer (MPBT) value). Multiprocessor bit value in transmit data is 1. Hitachi 483...
Page 495 Receive data register (RDR) H'FFFFFE05 Item Bit Name Initial Value Bit Name Description 7 to 0 (Stores serial receive Stores the received serial data data) 484 Hitachi...
Page 496 Set conditions: When FRC value is sent to the ICR by the input capture signal Output compare flag A Clear conditions: When OCFA = 1, OCFA is read and (OCFA) then 0 is written to it (initial value) Set conditions: When FRC value becomes equal to OCRA Hitachi 485...
Page 497 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit nam Description 15 to 0 (compares FRC value) Sets the OCRA when OCRA = FRC Sets the OCRB when OCRB = FFC 486 Hitachi...
Page 498 Selects OCRB register Output level A (OLVLA) Outputs 0 on compare match A (initial value) Outputs 1 on compare match A Output level B (OLVLB) Outputs 0 on compare match B (initial value) Outputs 1 on compare match B Hitachi 487...
Page 499 Input capture register (FICR) H'FFFFFE19 (FICRL) Note: Access FICRH first and then FICRL in eight bits twice. Item Bit name Initial Value Bit nam Description 15 to 0 (Stores FRC value) Stores FRC value when an input capture signal occurs 488 Hitachi...
Page 500 15 to 12 Serial communication interface These bits set the serial communication interface (SCI) interrupt priority level (SCI) interrupt priority level. (SCIIP3-SCIIP0) 11 to 8 Free-running timer (FRT) interrupt These bits set the free-running timer (FRT) interrupt priority level (FRTIP3-FRTIP0) priority level. Hitachi 489...
Page 501 (SCI) transmit-data-empty interrupt communication interface (SCI) transmit-data-empty vector number (STXV6-STXV0) interrupt (TXI). 6 to 0 Serial communication interface These bits set the vector number for the serial (SCI) transmit-end interrupt vector communication interface (SCI) transmit-end interrupt number (STEV6-STEV0) (TEI). 490 Hitachi...
Page 502 – Initial Value R/W R/W R/W R/W R/W R/W R/W Bit nam Description 14 to 8 Free-running timer (FRT) overflow These bit set the vector number for the free-running interrupt vector number (FOVV6- timer(FRT) overflow interrupt (OVI). FOVV0) Hitachi 491...
Page 503 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit nam Description 15 to 0 (Sets vector number) These bits set the vector number for the interrupt when the interrupt is occurred by the overflow or underflow of the division unit. 492 Hitachi...
Page 504 Interrupt request is detected on falling edge of NMI input (initial value) Interrupt request is detected on rising edge of NMI input RL interrupt vector Auto vector mode, set internally (initial valne) mode select (VECMD) External vector mode, external input Hitachi 493...
Page 505 2 to 0 Clock select 2 to 0 CKS2 CKS1 CKS0 Clock Source Overflow Interval (CKS2 to CKS0) (φ = 28.7 MHz) φ/2(initial value) 17.8µs φ/64 570.8µs φ/128 1.1ms φ/256 2.2ms φ/512 4.5ms φ/1024 9.1ms φ/4096 35.5ms φ/8192 73.0ms 494 Hitachi...
Page 506 Cleared when software reads WOVF, then writes 0 in WOVF Set by WTCNT overflow in watchdog timer mode Reset enable (RSTE) Not reset when WTCNT overflows (initial value) Reset when WTCNT overflows Reset select (RSTS) Power-on reset (initial value) Manual reset Hitachi 495...
Page 507 – – R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit nam Description 31 to 0 (Sets the dividend) Sets the 32-bit dividend used for 32 bit/32 bit division operations 496 Hitachi...
Page 508 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit nam Description 31 to 1 (Sets the dividend) Sets the upper 32 bits of the dividend used for 64 bit/32 bit division operations Hitachi 497...
Page 509 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit nam Description 31 to 1 (Sets the dividend) Sets the lower 32 bits of the dividend used for 64 bit/32 bit division operations 498 Hitachi...
Page 510 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit nam Description 15 to 0 Break address BAA15- These bits specify the lower bits (bit 15 to bit 0) of the BAA0 address of the channel A break condition Hitachi 499...
Page 511 Bit Name Value Description 15 to 0 Break address Channel A break address BAAn is included in the break BAMA15-BAMA0 conditions (initial value) Channel A break address BAAn is not included in the break conditions n=15 to 0 500 Hitachi...
Page 512 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit nam Description 15 to 0 Break address BAB31- These bits specify the upper bits (bit 31 to bit 16) of the BAB16 address of the channel B break condition Hitachi 501...
Page 513 Bit Name Value Description 15 to 0 Break address mask Channel B break address BABn is included in the break BAMB31-BAMB16 conditions (initial value) Channel B break address BABn is not included in the break conditions n=31 to 16 502 Hitachi...
Page 514 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit nam Description 15 to 0 Break address BDB31- These bits specify the upper bits (bit 31 to bit 16) of the BDB16 address of the channel B break condition Hitachi 503...
Page 515 15 to 0 Break data mask Channel B break address BDBn is included in the break BDMB31-BDMB16 conditions (initial value) Channel B break address BDBn is masked and therefore not included in the break conditions n=31 to 16 504 Hitachi...
Page 516 Description 15 to 0 Break data mask Channel B break address BDBn is included in the break BDMB15-BDMB0 conditions (initial value) Channel B break address BDBn is masked and therefore not inclnded in the break conditions n=15 to0 Hitachi 505...
Page 517 1 1 Break on both read and write cycles 1, 0 Operand size select B 0 0 Operand size is not a break condition (initial value) (SZB1, SZB0) 0 1 Break on byte access 1 0 Break on word access 1 1 Break on longword access 506 Hitachi...
Page 518 (EBBE) (initial value) Chip-external bus cycle included in break conditions UBC mode (UMD) Compatible mode for SH7000-series UBCs (initial value) SH7095 mode PC break select A Places the channel A instruction fetch cycle break before (PCBA) instruction execution (initial value)
Page 519 – – – – – R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit nam Description 31 to 0 (Specifies the transfer Specifies the DMA transfer destination address destination address) 508 Hitachi...
Page 520 +16 for 16-byte transfer size) 1 0 Destination address is decremented (-1 for byte transfer size, -2 for word transfer size, -4 for longword transfer size, and -16 for 16-byte transfer size) 1 1 Reserved (setting prohibited) Hitachi 509...
Page 521 DMA has not ended or was aborted (initial value) (TE) Cleared by reading 1 from the TE bit and then writing 0 DMA has ended nomally (by TCR = 0) DMA enable bit (DE) DMA transfer disabled (initial value) DMA transfer enabled 510 Hitachi...
Page 522 0 0 DREQ (external request) (initial value) 1, 0 (RS1, RS0) 0 1 RXI (receive-data-full interrupt transfer request of the on- chip serial communication interface (SCI)) 1 0 TXI (transmit-data-full interrupt transfer request of the on- chip SCI) 1 1 Reserved (setting disabled) Hitachi 511...
Page 523 No NMIF interrupt (initial value) To clear the NMIF bit, read 1 from it and then write 0. NMIF has occurred DMA master enable bit Disables DMA transfers on all channels (initial value) (DME) Enables DMA transfers on all channels 512 Hitachi...
Page 524 1 0 0 Area 2 is synchronous DRAM space; area 3 is ordinary space 1 0 1 Areas 2 and 3 are synchronous DRAM spaces 1 1 0 Reserved (do not set) 1 1 1 Reserved (do not set) Hitachi 513...
Page 525 15 to 8 Idles between cycles for IW31 IW30 areas 3 to 0 IW21 IW20 IW11 IW10 IW01 IW00 0 No idle cycle 1 Inserts one idle cycle 0 Inserts two idle cycles (initial value) 1 Reserved (do not set) 514 Hitachi...
Page 526 Individual memory control register (MCR) H'FFFFFFEC 16/32 Item Bit Name TRAS TRAS TRP RCD TRWL 1 BE RASD – AMX2 SZ AMX1AMX0 RFSHRMD – – Initial Value R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Hitachi 515...
Page 527 The next access always starts with bank active commands. Far synchronous DRAM, access ends with bank active status. This is only valid for area 3. When area 2 is synchronous DRAM, the mode is always auto precharge. 516 Hitachi...
Page 528 1 1 0 Reserved (do not set) 1 1 1 2-Mbit DRAM (128k x 16 bits) Memory data size (SZ) Word (initial value) Longword Refresh control (RFSH) No refresh (initial value) Refresh Refresh mode Normal refresh (initial value) (RMODE) Self refresh Hitachi 517...
Page 529 Refresh time constant register (RTCOR) H'FFFFFFF8 16/32 Item Bit Name – – – – – – – – Initial Value R/W R/W R/W R/W R/W R/W R/W R/W Bit Name Description 7 to 0 (Timer constant) Sets the refresh cycle 518 Hitachi...
Page 530 (OD) Data not replaced even when cache missed in data access Instruction replacement Nomal operation (initial value) disable (ID) Data not replaced even when cache missed in instruction fetch Cache enable (CE) Cache disabled (initial value) Cache enabled Hitachi 519...
Page 531 Module stop 2 (MSTP2) DIVU running (initial value) Clock supply to DIVU halted Module stop 1 (MSTP1) FRT running (initial value) Clock supply to FRT halted Module stop 0 (MSTP0) SCI running (initial value) Clock supply to SCI halted 520 Hitachi...
Page 532: Appendix C External Dimensions
Appendix C External Dimensions Figure C.1 shows the external dimensions of the SH7095 (FP-144). Figure C.1 External Dimensions Hitachi 521...

Hitachi SH7095 Hardware User Manual

Section 1 Overview and Pin Functions

Section 2 CPU

Section 3 Operating Mode

Section 4 Exception Processing

Section 5 Interrupt Controller (INTC)

Section 6 User Break Controller

Section 7 Bus State Controller (BSC)

Section 8 Cache

Section 9 Direct Memory Access Controller (DMAC)

Section 10 Division Unit

Section 11 16-Bit Free-Running Timer

Section 12 Watchdog Timer (WDT)

Section 13 Serial Communication Interface

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Summary of Contents for Hitachi SH7095