NEC 78K0/KD1 Series User Manual

8-bit single-chip microcontrollers

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Preliminary User's Manual

78K0/KD1

8-Bit Single-Chip Microcontrollers

µ µ µ µ PD780121

µ µ µ µ PD780122

µ µ µ µ PD780123

µ µ µ µ PD780124

µ µ µ µ PD78F0124

Document No. U16315EJ1V0UD00 (1st edition)

Date Published July 2002 N CP(K)

2002

Printed in Japan

µ µ µ µ PD780121(A)

µ µ µ µ PD780122(A)

µ µ µ µ PD780123(A)

µ µ µ µ PD780124(A)

µ µ µ µ PD78F0124(A)

µ µ µ µ PD780121(A1)

µ µ µ µ PD780122(A1)

µ µ µ µ PD780123(A1)

µ µ µ µ PD780124(A1)

Table of Contents

Summary of Contents for NEC 78K0/KD1 Series

Page 1 Preliminary User’s Manual 78K0/KD1 8-Bit Single-Chip Microcontrollers µ µ µ µ PD780121 µ µ µ µ PD780121(A) µ µ µ µ PD780121(A1) µ µ µ µ PD780122 µ µ µ µ PD780122(A) µ µ µ µ PD780122(A1) µ µ µ µ PD780123 µ...
Page 2 [MEMO] Preliminary User’s Manual U16315EJ1V0UD...
Page 3 Reset operation must be executed immediately after power-on for devices having reset function. EEPROM is a trademark of NEC Corporation. Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries.
Page 4 The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
Page 5 Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: •...
Page 6 INTRODUCTION Readers This manual is intended for user engineers who wish to understand the functions of the 78K0/KD1 Series and design and develop application systems and programs for these devices. The target products are as follows. 78K0/KD1 Series: µ PD780121, 780122, 780123, 780124, 78F0124, 780121(A),...
Page 7 How to Read This Manual It is assumed that the readers of this manual have general knowledge of electrical engineering, logic circuits, and microcontrollers. • When using this manual as the manual for (A) products and (A1) products: → Only the quality grade differs between standard products and (A) and (A1) products.
Page 8 SEMICONDUCTOR SELECTION GUIDE − Product & Packages − X13769E Semiconductor Device Mounting Technology Manual C10535E Quality Grades on NEC Semiconductor Devices C11531E NEC Semiconductor Device Reliability/Quality Control System C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E Caution The related documents listed above are subject to change without notice.
Page 9: Table Of Contents
CONTENTS CHAPTER 1 OUTLINE ..........................25 Features ............................25 Applications..........................26 Ordering Information ........................27 Pin Configuration (Top View).....................29 78K0/Kxx Series Lineup ......................31 Block Diagram ..........................33 Outline of Functions ........................34 CHAPTER 2 PIN FUNCTIONS ........................36 Pin Function List .........................36 Description of Pin Functions .....................39 2.2.1 P00 to P03 (port 0) .........................39 2.2.2...
Page 10 3.3.2 Immediate addressing ........................68 3.3.3 Table indirect addressing....................... 69 3.3.4 Register addressing........................69 Operand Address Addressing ....................70 3.4.1 Implied addressing......................... 70 3.4.2 Register addressing........................71 3.4.3 Direct addressing........................... 72 3.4.4 Short direct addressing........................73 3.4.5 Special function register (SFR) addressing ................... 74 3.4.6 Register indirect addressing ......................
Page 11 5.8.2 Switching from X1 input clock to Ring-OSC clock ................125 5.8.3 Switching from X1 input clock to subsystem clock................126 5.8.4 Switching from subsystem clock to X1 input clock................127 5.8.5 Register settings...........................128 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00................129 Functions of 16-Bit Timer/Event Counter 00................129 Configuration of 16-Bit Timer/Event Counter 00 ..............130 Registers Controlling 16-Bit Timer/Event Counter 00............133 Operation of 16-Bit Timer/Event Counter 00 ................139...
Page 12 10.2 Configuration of Watchdog Timer ..................211 10.3 Registers Controlling Watchdog Timer ................. 212 10.4 Operation of Watchdog Timer....................214 10.4.1 Watchdog timer operation when “Ring-OSC cannot be stopped” is selected by mask option ..214 10.4.2 Watchdog timer operation when “Ring-OSC can be stopped by software” is selected by mask option ......................
Page 13 15.2 Configuration of Serial Interface CSI10 ..................311 15.3 Registers Controlling Serial Interface CSI10 .................313 15.4 Operation of Serial Interface CSI10..................315 15.4.1 Operation stop mode ........................315 15.4.2 3-wire serial I/O mode ........................316 CHAPTER 16 INTERRUPT FUNCTIONS .....................324 16.1 Interrupt Function Types......................324 16.2 Interrupt Sources and Configuration ..................324 16.3 Registers Controlling Interrupt Functions ................327 16.4 Interrupt Servicing Operations ....................334...
Page 14 22.4 Operation of Low-Voltage Detector..................374 22.5 Cautions for Low-Voltage Detector ..................378 CHAPTER 23 REGULATOR ......................... 382 23.1 Outline ............................382 CHAPTER 24 MASK OPTIONS ......................383 CHAPTER 25 µ µ µ µ PD78F0124 ........................384 25.1 Internal Memory Size Switching Register................385 25.2 Flash Memory Programming....................
Page 15 LIST OF FIGURES (1/7) Figure No. Title Page Pin I/O Circuit List ............................44 Memory Map ( µ PD780121) ......................... 47 Memory Map ( µ PD780122) ......................... 48 Memory Map ( µ PD780123) ......................... 49 Memory Map ( µ PD780124) ......................... 50 Memory Map ( µ...
Page 16 LIST OF FIGURES (2/7) Figure No. Title Page Format of Ring-OSC Mode Register (RCM) ....................107 Format of Main Clock Mode Register (MCM) ....................108 Format of Main OSC Control Register (MOC) ...................109 Format of Oscillation Stabilization Time Counter Status Register (OSTC) ..........110 Format of Oscillation Stabilization Time Select Register (OSTS) ..............111 External Circuit of X1 Oscillator.........................112 5-10...
Page 17 LIST OF FIGURES (3/7) Figure No. Title Page 6-25 External Event Counter Operation Timing (with Rising Edge Specified) ........... 151 6-26 Control Register Settings in Square-Wave Output Mode ................152 6-27 Square-Wave Output Operation Timing ....................152 6-28 Control Register Settings for One-Shot Pulse Output with Software Trigger..........154 6-29 Timing of One-Shot Pulse Output Operation with Software Trigger ............
Page 18 LIST OF FIGURES (4/7) Figure No. Title Page 10-1 Block Diagram of Watchdog Timer ......................211 10-2 Format of Watchdog Timer Mode Register (WDTM) .................212 10-3 Format of Watchdog Timer Enable Register (WDTE)................213 10-4 Operation in STOP Mode (CPU Clock and WDT Operation Clock: X1 Input Clock) .........216 10-5 Operation in STOP Mode (CPU Clock: X1 Input Clock, WDT Operation Clock: Ring-OSC Clock) ...216 10-6...
Page 19 LIST OF FIGURES (5/7) Figure No. Title Page 13-7 Normal Transmission Completion Interrupt Request Timing ..............259 13-8 Reception Completion Interrupt Request Timing..................260 13-9 Noise Filter Circuit............................. 261 13-10 Configuration of Baud Rate Generator ...................... 262 13-11 Permissible Baud Rate Range During Reception..................266 14-1 LIN Transmission Operation........................
Page 20 LIST OF FIGURES (6/7) Figure No. Title Page 16-5 Format of External Interrupt Rising Edge Enable Register (EGP) and External Interrupt Falling Edge Enable Register (EGN)..............332 16-6 Format of Program Status Word........................333 16-7 Interrupt Request Acknowledgement Processing Algorithm..............335 16-8 Interrupt Request Acknowledgement Timing (Minimum Time) ..............336 16-9 Interrupt Request Acknowledgement Timing (Maximum Time) ..............336 16-10...
Page 21 LIST OF FIGURES (7/7) Figure No. Title Page 25-1 Format of Internal Memory Size Switching Register (IMS)................ 385 25-2 Communication Mode Selection Format ....................387 25-3 Connection of Flashpro III/Flashpro IV in 3-Wire Serial I/O Mode............. 388 25-4 Connection of Flashpro III/Flashpro IV in 3-Wire Serial I/O Mode (Using Handshake) ......388 25-5 Connection of Flashpro III/Flashpro IV in UART (UART0) Mode ..............
Page 22 LIST OF TABLES (1/3) Table No. Title Page Flash Memory Versions Corresponding to Mask Options of Mask ROM Versions........28 Pin I/O Circuit Types............................43 Set Values of Internal Memory Size Switching Register (IMS) ..............46 Internal Memory Capacity..........................52 Vector Table ..............................52 Internal High-Speed RAM Capacity......................53 Special Function Register List ........................64 Port Functions .............................79 Port Configuration............................80...
Page 23 LIST OF TABLES (2/3) Table No. Title Page 12-3 A/D Converter Sampling Time and A/D Conversion Start Delay Time (ADM Set Value) ......244 13-1 Configuration of Serial Interface UART0 ....................246 13-2 Cause of Reception Error.......................... 261 13-3 Set Data of Baud Rate Generator ......................265 13-4 Maximum/Minimum Permissible Baud Rate Error..................
Page 24 LIST OF TABLES (3/3) Table No. Title Page 29-1 Registers That Generate Wait and Number of CPU Wait Clocks ..............428 29-2 Number of Wait Clocks and Number of Execution Clocks on Occurrence of Wait (A/D Converter) ..429 Preliminary User’s Manual U16315EJ1V0UD...
Page 25: Chapter 1 Outline
CHAPTER 1 OUTLINE 1.1 Features ROM, RAM capacities Item Program Memory Data Memory (ROM) Part Number Internal High-Speed RAM µ PD780121 Mask ROM 8 KB 512 bytes µ PD780122 16 KB µ PD780123 24 KB 1024 bytes µ PD780124 32 KB µ...
Page 26: Applications
CHAPTER 1 OUTLINE 1.2 Applications Automotive equipment • System control for body electricals (power windows, keyless entry reception, etc.) • Sub-microcontrollers for control Home audio, car audio AV equipment PC peripheral equipment (keyboards, etc.) Household electrical appliances • Outdoor air conditioner units •...
Page 27: Ordering Information
P l e a s e r e f e r t o " Q u a l i t y G r a d e s o n N E C S e m i c o n d u c t o r D e v i c e s " ( D o c u m e n t N o . C 1 1 5 3 1 E ) p u b l i s h e d b y NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
Page 28 CHAPTER 1 OUTLINE Mask ROM versions ( µ PD780121, 780122, 780123, and 780124) include mask options. When ordering, it is possible to select “Power-on-clear (POC) circuit can be used/cannot be used”, “Ring-OSC clock can be stopped/cannot be stopped by software” and “Pull-up resistor incorporated/not incorporated in 1-bit units (P60 to P63 pins)”.
Page 29: Pin Configuration (Top View)
CHAPTER 1 OUTLINE 1.4 Pin Configuration (Top View) • 52-pin plastic LQFP (10 × 10) µ PD780121GB-×××-8ET, 780122GB-×××-8ET, 780123GB-×××-8ET, 780124GB-×××-8ET, µ PD780121GB(A)-×××-8ET, 780122GB(A)-×××-8ET, 780123GB(A)-×××-8ET, µ PD780124GB(A)-×××-8ET, 780121GB(A1)-×××-8ET, 780122GB(A1)-×××-8ET, µ PD780123GB(A1)-×××-8ET, 780124GB(A1)-×××-8ET, 78F0124M1GB-8ET, µ PD78F0124M2GB-8ET, 78F0124M3GB-8ET, 78F0124M4GB-8ET, 78F0124M5GB-8ET, µ PD78F0124M6GB-8ET, 78F0124M1GB(A)-8ET, 78F0124M2GB(A)-8ET, 78F0124M3GB(A)-8ET, µ...
Page 30 CHAPTER 1 OUTLINE Pin Identification ANI0 to ANI7: Analog input PCL: Programmable clock output Analog reference voltage REGC: Regulator capacitance Analog ground RESET: Reset Power supply for port RxD0, RxD6: Receive data Ground for port SCK10: Serial clock input/output Internally connected SI10: Serial data input INTP0 to INTP6: External interrupt input...
Page 31: 78K0/Kxx Series Lineup
Mask ROM: 16 KB, RAM: 512 bytes PD780112 µ PD780111 Mask ROM: 8 KB, RAM: 512 bytes 78K0/KD1 Series: 52-pin (10 × 10 mm 0.65 mm pitch) µ PD78F0124 Flash memory: 32 KB, RAM: 1 KB µ Mask ROM: 32 KB, RAM: 1 KB PD780124 µ...
Page 32 CHAPTER 1 OUTLINE The function list in the 78K0/Kxx Series (under development or in planning) is shown below. Part Number 78K0/KB1 78K0/KC1 78K0/KD1 78K0/KE1 78K0/KF1 Item Package 30 pins 44 pins 52 pins 64 pins 80 pins − − − −...
Page 33: Block Diagram
CHAPTER 1 OUTLINE 1.6 Block Diagram TO00/TI010/P01 16-bit timer/ Port 0 P00 to P03 event counter 00 TI000/P00 Port 1 P10 to P17 TOH0/P15 8-bit timer H0 Port 2 P20 to P27 Port 3 P30 to P33 TOH1/P16 8-bit timer H1 Port 6 P60 to P63 8-bit timer/...
Page 34: Outline Of Functions
CHAPTER 1 OUTLINE 1.7 Outline of Functions (1/2) µ PD780121 µ PD780122 µ PD780123 µ PD780124 µ PD78F0124 Item − Internal Mask ROM 16 K 24 K 32 K memory − Note 1 Flash memory 32 K (bytes) Note 1 High-speed RAM −...
Page 35 CHAPTER 1 OUTLINE (2/2) µ PD780121 µ PD780122 µ PD780123 µ PD780124 µ PD78F0124 Item Vectored interrupt Internal sources External Key interrupt Key interrupt (INTKR) occurs by detecting falling edge of key input pins (KR0 to KR7). Reset • Reset using RESET pin •...
Page 36: Chapter 2 Pin Functions
CHAPTER 2 PIN FUNCTIONS 2.1 Pin Function List (1) Port pins Pin Name Function After Reset Alternate Function Port 0. Input TI000 4-bit I/O port. TI010/TO00 Input/output can be specified in 1-bit units. − Use of an on-chip pull-up resistor can be specified by a −...
Page 37 CHAPTER 2 PIN FUNCTIONS (2) Non-port pins (1/2) Pin Name Function After Reset Alternate Function INTP0 Input External interrupt request input for which the valid edge (rising Input P120 edge, falling edge, or both rising and falling edges) can be INTP1 to INTP3 P30 to P32 specified...
Page 38 CHAPTER 2 PIN FUNCTIONS (2) Non-port pins (2/2) Pin Name Function After Reset Alternate Function − − − Positive power supply (except for ports) − − − Positive power supply for ports − − − Ground potential (except for ports) −...
Page 39: Description Of Pin Functions
CHAPTER 2 PIN FUNCTIONS 2.2 Description of Pin Functions 2.2.1 P00 to P03 (port 0) P00 to P03 function as a 4-bit I/O port. These pins also function as timer I/O. The following operation modes can be specified in 1-bit units. (1) Port mode P00 to P03 function as a 4-bit I/O port.
Page 40: P20 To P27 (Port 2)
CHAPTER 2 PIN FUNCTIONS (e) TO50, TOH0, and TOH1 These are timer output pins. (f) INTP5 This is an external interrupt request input pin for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. 2.2.3 P20 to P27 (port 2) P20 to P27 function as an 8-bit input-only port.
Page 41: P120 (Port 12)
CHAPTER 2 PIN FUNCTIONS (1) Port mode P70 to P77 function as an 8-bit I/O port. P70 to P77 can be set to input or output in 1-bit units using port mode register 7 (PM7). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 7 (PU7). (2) Control mode P70 to P77 function as key interrupt input pins.
Page 42: Reset
V in the normal operation mode. 2.2.19 IC (mask ROM versions only) The IC (Internally Connected) pin is provided to set the test mode to check the 78K0/KD1 Series at shipment. Connect it directly to EV or V pin with the shortest possible wire in the normal operation mode.
Page 43: Pin I/O Circuits And Recommended Connection Of Unused Pins
CHAPTER 2 PIN FUNCTIONS 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins Table 2-1 shows the types of pin I/O circuits and the recommended connections of unused pins. Refer to Figure 2-1 for the configuration of the I/O circuit of each type. Table 2-1.
Page 44 CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuit List (1/2) Type 2 Type 8-A Pullup P-ch enable Data P-ch IN/OUT Schmitt-triggered input with hysteresis characteristics Output N-ch disable Type 3-C Type 9-C Comparator P-ch N-ch P-ch – Data (threshold voltage) N-ch Input enable...
Page 45 CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuit List (2/2) Type 13-S Type 13-W IN/OUT   Mask   Data option   N-ch IN/OUT Output disable Data N-ch Output disable Input enable Middle-voltage input buffer Type 13-V Type 16 Feedback ...
Page 46: Chapter 3 Cpu Architecture
CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Space Products in the 78K0/KD1 Series can each access a 64 KB memory space. Figures 3-1 to 3-5 show the memory maps. Caution Regardless of the internal memory capacity, the initial value of the internal memory size switching register (IMS) of all products in the 78K0/KD1 Series is fixed (IMS = CFH).
Page 47 CHAPTER 3 CPU ARCHITECTURE Figure 3-1. Memory Map ( µ µ µ µ PD780121) Special function registers (SFR) 256 × 8 bits General-purpose registers 32 × 8 bits Internal high-speed RAM 512 × 8 bits Program area Data memory space CALLF entry area Reserved Program area...
Page 48 CHAPTER 3 CPU ARCHITECTURE Figure 3-2. Memory Map ( µ µ µ µ PD780122) Special function registers (SFR) 256 × 8 bits General-purpose registers 32 × 8 bits Internal high-speed RAM 512 × 8 bits Program area Data memory space CALLF entry area Reserved Program area...
Page 49 CHAPTER 3 CPU ARCHITECTURE Figure 3-3. Memory Map ( µ µ µ µ PD780123) Special function registers (SFR) 256 × 8 bits General-purpose registers 32 × 8 bits Internal high-speed RAM 1024 × 8 bits Program area Data memory space CALLF entry area Reserved Program area...
Page 50 CHAPTER 3 CPU ARCHITECTURE Figure 3-4. Memory Map ( µ µ µ µ PD780124) Special function registers (SFR) 256 × 8 bits General-purpose registers 32 × 8 bits Internal high-speed RAM 1024 × 8 bits Program area Data memory space CALLF entry area Reserved Program area...
Page 51 CHAPTER 3 CPU ARCHITECTURE Figure 3-5. Memory Map ( µ µ µ µ PD78F0124) Special function registers (SFR) 256 × 8 bits General-purpose registers 32 × 8 bits Internal high-speed RAM 1024 × 8 bits Program area Data memory space CALLF entry area Reserved Program area...
Page 52: Internal Program Memory Space
3.1.1 Internal program memory space The internal program memory space stores the program and table data. Normally, it is addressed with the program counter (PC). 78K0/KD1 Series products incorporate internal ROM (or flash memory), as shown below. Table 3-2. Internal Memory Capacity Part Number...
Page 53: Internal Data Memory Space
CHAPTER 3 CPU ARCHITECTURE 3.1.2 Internal data memory space 78K0/KD1 Series products incorporate the following internal high-speed RAMs. Table 3-4. Internal High-Speed RAM Capacity Part Number Internal High-Speed RAM µ PD780121 512 × 8 bits (FD00H to FEFFH) µ PD780122 µ...
Page 54: Data Memory Addressing
Several addressing modes are provided for addressing the memory relevant to the execution of instructions for the 78K0/KD1 Series, based on operability and other considerations. For areas containing data memory in particular, special addressing methods designed for the functions of special function registers (SFR) and general-purpose registers are available for use.
Page 55 CHAPTER 3 CPU ARCHITECTURE Figure 3-7. Data Memory Addressing ( µ µ µ µ PD780122) Special function registers (SFR) SFR addressing 256 × 8 bits General-purpose registers Register addressing 32 × 8 bits Short direct addressing Internal high-speed RAM 512 × 8 bits Direct addressing Register indirect addressing Based addressing...
Page 56 CHAPTER 3 CPU ARCHITECTURE Figure 3-8. Data Memory Addressing ( µ µ µ µ PD780123) Special function registers (SFR) SFR addressing 256 × 8 bits General-purpose registers Register addressing 32 × 8 bits Short direct addressing Internal high-speed RAM 1024 × 8 bits Direct addressing Register indirect addressing Based addressing...
Page 57 CHAPTER 3 CPU ARCHITECTURE Figure 3-9. Data Memory Addressing ( µ µ µ µ PD780124) Special function registers (SFR) SFR addressing 256 × 8 bits General-purpose registers Register addressing 32 × 8 bits Short direct addressing Internal high-speed RAM 1024 × 8 bits Direct addressing Register indirect addressing Based addressing...
Page 58 CHAPTER 3 CPU ARCHITECTURE Figure 3-10. Data Memory Addressing ( µ µ µ µ PD78F0124) Special function registers (SFR) SFR addressing 256 × 8 bits General-purpose registers Register addressing 32 × 8 bits Short direct addressing Internal high-speed RAM 1024 × 8 bits Direct addressing Register indirect addressing Based addressing...
Page 59: Processor Registers
CHAPTER 3 CPU ARCHITECTURE 3.2 Processor Registers The 78K0/KD1 Series products incorporate the following processor registers. 3.2.1 Control registers The control registers control the program sequence, statuses and stack memory. The control registers consist of a program counter (PC), a program status word (PSW) and a stack pointer (SP).
Page 60 CHAPTER 3 CPU ARCHITECTURE (a) Interrupt enable flag (IE) This flag controls the interrupt request acknowledge operations of the CPU. When 0, the IE flag is set to the interrupt disabled (DI) state, and only non-maskable interrupt requests become acknowledgeable. Other interrupt requests are all disabled. When 1, the IE flag is set to the interrupt enabled (EI) state and interrupt request acknowledgement is controlled with an in-service priority flag (ISP), an interrupt mask flag for various interrupt sources, and a priority specification flag.
Page 61 CHAPTER 3 CPU ARCHITECTURE Figure 3-13. Format of Stack Pointer SP15 SP14 SP13 SP12 SP11 SP10 SP9 The SP is decremented ahead of write (save) to the stack memory and is incremented after read (restored) from the stack memory. Each stack operation saves/restores data as shown in Figures 3-14 and 3-15. Caution Since RESET input makes the SP contents undefined, be sure to initialize the SP before instruction execution.
Page 62: General-Purpose Registers
CHAPTER 3 CPU ARCHITECTURE 3.2.2 General-purpose registers General-purpose registers are mapped at particular addresses (FEE0H to FEFFH) of the data memory. The general-purpose registers consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H). Each register can be used as an 8-bit register, and two 8-bit registers can also be used in a pair as a 16-bit register (AX, BC, DE, and HL).
Page 63: Special Function Registers (Sfrs)
CHAPTER 3 CPU ARCHITECTURE 3.2.3 Special Function Registers (SFRs) Unlike a general-purpose register, each special function register has a special function. SFRs are allocated to the FF00H to FFFFH area. Special function registers can be manipulated like general-purpose registers, using operation, transfer and bit manipulation instructions.
Page 64 CHAPTER 3 CPU ARCHITECTURE Table 3-5. Special Function Register List (1/3) Address Special Function Register (SFR) Name Symbol Manipulatable Bit Unit After Reset 1 Bit 8 Bits 16 Bits √ √ − FF00H Port 0 √ √ − FF01H Port 1 √...
Page 65 CHAPTER 3 CPU ARCHITECTURE Table 3-5. Special Function Register List (2/3) Address Special Function Register (SFR) Name Symbol Manipulatable Bit Unit After Reset 1 Bit 8 Bits 16 Bits √ √ − FF33H Pull-up resistor option register 3 √ √ −...
Page 66 Notes 1. This value varies depending on the reset source. The initial value of IMS is fixed (IMS = CFH) in all products in the 78K0/KD1 Series regardless of the internal memory capacity. Therefore, set the following value to each product.
Page 67: Instruction Address Addressing
CHAPTER 3 CPU ARCHITECTURE 3.3 Instruction Address Addressing An instruction address is determined by program counter (PC) contents and is normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed.
Page 68: Immediate Addressing
CHAPTER 3 CPU ARCHITECTURE 3.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed. CALL !addr16 and BR !addr16 instructions can be branched to the entire memory space.
Page 69: Register Addressing
CHAPTER 3 CPU ARCHITECTURE 3.3.3 Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (PC) and branched. This function is carried out when the CALLT [addr5] instruction is executed.
Page 70: Operand Address Addressing
[Function] The register that functions as an accumulator (A and AX) among the general-purpose registers is automatically (implicitly) addressed. Of the 78K0/KD1 Series instruction words, the following instructions employ implied addressing. Instruction Register to Be Specified by Implied Addressing MULU...
Page 71: Register Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.2 Register addressing [Function] The general-purpose register to be specified is accessed as an operand with the register bank select flags (RBS0 to RBS1) and the register specify codes (Rn and RPn) of an operation code. Register addressing is carried out when an instruction with the following operand format is executed.
Page 72: Direct Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.3 Direct addressing [Function] The memory to be manipulated is directly addressed with immediate data in an instruction word becoming an operand address. [Operand format] Identifier Description addr16 Label or 16-bit immediate data [Description example] MOV A, !0FE00H; when setting !addr16 to FE00H Operation code OP code [Illustration]...
Page 73: Short Direct Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.4 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. This addressing is applied to the 256-byte space FE20H to FF1FH. Internal RAM and special function registers (SFRs) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively.
Page 74: Special Function Register (Sfr) Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.5 Special function register (SFR) addressing [Function] A memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFRs mapped at FF00H to FF1FH can be accessed with short direct addressing.
Page 75: Register Indirect Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.6 Register indirect addressing [Function] Register pair contents specified by a register pair specify code in an instruction word and by a register bank select flag (RBS0 and RBS1) serve as an operand address for addressing the memory. This addressing can be carried out for all the memory spaces.
Page 76: Based Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.7 Based addressing [Function] 8-bit immediate data is added as offset data to the contents of the base register, that is, the HL register pair in the register bank specified by the register bank select flag (RBS0 and RBS1), and the sum is used to address the memory.
Page 77: Based Indexed Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.8 Based indexed addressing [Function] The B or C register contents specified in an instruction word are added to the contents of the base register, that is, the HL register pair in the register bank specified by the register bank select flag (RBS0 and RBS1), and the sum is used to address the memory.
Page 78: Chapter 4 Port Functions
CHAPTER 4 PORT FUNCTIONS 4.1 Port Functions 78K0/KD1 Series products are provided with the ports shown in Figure 4-1, which enable variety of control operations. The functions of each port are shown in Table 4-1. In addition to the function as digital I/O ports, these ports have several alternate functions. For details of the alternate functions, refer to CHAPTER 2 PIN FUNCTIONS.
Page 79 CHAPTER 4 PORT FUNCTIONS Table 4-1. Port Functions Pin Name Function After Reset Alternate Function Port 0. Input TI000 4-bit I/O port. TI010/TO00 Input/output can be specified in 1-bit units. − Use of an on-chip pull-up resistor can be specified by a −...
Page 80: Port Configuration
CHAPTER 4 PORT FUNCTIONS 4.2 Port Configuration Ports consist of the following hardware. Table 4-2. Port Configuration Item Configuration Control registers Port mode register (PM0, PM1, PM3, PM6, PM7, PM12, PM14) Pull-up resistor option register (PU0, PU1, PU3, PU7, PU12, PU14) Input switch control register (ISC) Port Total: 39 (CMOS I/O: 26, CMOS input: 8, CMOS output: 1, N-ch open drain I/O: 4)
Page 81: Port 0
CHAPTER 4 PORT FUNCTIONS 4.2.1 Port 0 Port 0 is a 4-bit I/O port with an output latch. Port 0 can be set to the input mode or output mode in 1-bit units using port mode register 0 (PM0). When the P00 to P03 pins are used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 0 (PU0).
Page 82 CHAPTER 4 PORT FUNCTIONS Figure 4-3. Block Diagram of P01 PU01 P-ch Alternate function PORT Output latch P01/TI010/TO00 (P01) PM01 Alternate function PU0: Pull-up resistor option register 0 Port mode register Port 0 read signal Port 0 write signal Preliminary User’s Manual U16315EJ1V0UD...
Page 83 CHAPTER 4 PORT FUNCTIONS Figure 4-4. Block Diagram of P02 PU02 P-ch PORT Output latch (P02) PM02 Alternate function PU0: Pull-up resistor option register 0 Port mode register Port 0 read signal Port 0 write signal Preliminary User’s Manual U16315EJ1V0UD...
Page 84: Port 1
CHAPTER 4 PORT FUNCTIONS 4.2.2 Port 1 Port 1 is an 8-bit I/O port with an output latch. Port 1 can be set to the input mode or output mode in 1-bit units using port mode register 1 (PM1). When the P10 to P17 pins are used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 1 (PU1).
Page 85 CHAPTER 4 PORT FUNCTIONS Figure 4-6. Block Diagram of P11 and P14 PU11, PU14 P-ch Alternate function PORT Output latch P11/SI10/RxD0, (P11, P14) P14/RxD6 PM11, PM14 PU1: Pull-up resistor option register 1 Port mode register Port 1 read signal Port 1 write signal Preliminary User’s Manual U16315EJ1V0UD...
Page 86 CHAPTER 4 PORT FUNCTIONS Figure 4-7. Block Diagram of P12 PU12 P-ch PORT Output latch (P12) P12/SO10 PM12 Alternate function PU1: Pull-up resistor option register 1 Port mode register Port 1 read signal Port 1 write signal Preliminary User’s Manual U16315EJ1V0UD...
Page 87 CHAPTER 4 PORT FUNCTIONS Figure 4-8. Block Diagram of P13 PU13 P-ch PORT Output latch (P13) P13/TxD6 PM13 Alternate function PU1: Pull-up resistor option register 1 Port mode register Port 1 read signal Port 1 write signal Preliminary User’s Manual U16315EJ1V0UD...
Page 88 CHAPTER 4 PORT FUNCTIONS Figure 4-9. Block Diagram of P15 PU15 P-ch PORT Output latch (P15) P15/TOH0 PM15 Alternate function PU1: Pull-up resistor option register 1 Port mode register Port 1 read signal Port 1 write signal Preliminary User’s Manual U16315EJ1V0UD...
Page 89 CHAPTER 4 PORT FUNCTIONS Figure 4-10. Block Diagram of P16 and P17 PU16, PU17 P-ch Alternate function PORT Output latch P16/TOH1/INTP5, (P16, P17) P17/TI50/TO50 PM16, PM17 Alternate function PU1: Pull-up resistor option register 1 Port mode register Port 1 read signal Port 1 write signal Preliminary User’s Manual U16315EJ1V0UD...
Page 90: Port 2
CHAPTER 4 PORT FUNCTIONS 4.2.3 Port 2 Port 2 is an 8-bit input-only port. This port can also be used for A/D converter analog input. Figure 4-11 shows a block diagram of port 2. Figure 4-11. Block Diagram of P20 to P27 P20/ANI0 to P27/ANI7 A/D converter –...
Page 91: Port 3
CHAPTER 4 PORT FUNCTIONS 4.2.4 Port 3 Port 3 is a 4-bit I/O port with an output latch. Port 3 can be set to the input mode or output mode in 1-bit units using port mode register 3 (PM3). When used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 3 (PU3).
Page 92 CHAPTER 4 PORT FUNCTIONS Figure 4-13. Block Diagram of P33 PU33 P-ch Alternate function PORT Output latch P33/INTP4/TI51/TO51 (P33) PM33 Alternate function PU0: Pull-up resistor option register 3 Port mode register Port 3 read signal Port 3 write signal Preliminary User’s Manual U16315EJ1V0UD...
Page 93: Port 6
CHAPTER 4 PORT FUNCTIONS 4.2.5 Port 6 Port 6 is a 4-bit I/O port with an output latch. Port 6 can be set to the input mode or output mode in 1-bit units using port mode register 6 (PM6). This port has the following functions for pull-up resistors. These functions differ depending on whether the product is a mask ROM version or a flash memory version.
Page 94: Port 7
CHAPTER 4 PORT FUNCTIONS 4.2.6 Port 7 Port 7 is an 8-bit I/O port with an output latch. Port 7 can be set to the input mode or output mode in 1-bit units using port mode register 7 (PM7). When the P70 to P77 pins are used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 7 (PU7).
Page 95: Port 12
CHAPTER 4 PORT FUNCTIONS 4.2.7 Port 12 Port 12 is a 1-bit I/O port with an output latch. Port 12 can be set to the input mode or output mode in 1-bit units using port mode register 12 (PM12). When used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 12 (PU12).
Page 96: Port 13
CHAPTER 4 PORT FUNCTIONS 4.2.8 Port 13 Port 13 is a 1-bit output-only port. Figure 4-17 shows a block diagram of port 13. Figure 4-17. Block Diagram of P130 PORT Output latch P130 (P130) Port 13 read signal Port 13 write signal Preliminary User’s Manual U16315EJ1V0UD...
Page 97: Port 14
CHAPTER 4 PORT FUNCTIONS 4.2.9 Port 14 Port 14 is a 1-bit I/O port with an output latch. Port 14 can be set to the input mode or output mode in 1-bit units using port mode register 14 (PM14). When the P140 pin is used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 14 (PU14).
Page 98: Registers Controlling Port Function
CHAPTER 4 PORT FUNCTIONS 4.3 Registers Controlling Port Function Port functions are controlled by the following three types of registers. • Port mode registers (PM0, PM1, PM3, PM6, PM7, PM12, PM14) • Pull-up resistor option registers (PU0, PU1, PU3, PU7, PU12, PU14) •...
Page 99 CHAPTER 4 PORT FUNCTIONS Table 4-4. Settings of Port Mode Register and Output Latch When Using Alternate Function Pin Name Alternate Function PM×× P×× Function Name × TI000 Input × TI010 Input TO00 Output × SCK10 Input Output TxD0 Output ×...
Page 100 CHAPTER 4 PORT FUNCTIONS (2) Pull-up resistor option registers (PU0, PU1, PU3, PU7, PU12, and PU14) These registers specify whether the on-chip pull-up resistors of P00 to P03, P10 to P17, P30 to P33, P70 to P77, P120, or P140 are to be used or not. On-chip pull-up resistors can be used in 1-bit units only for the bits set to input mode of the pins to which the use of an on-chip pull-up resistor has been specified in PU0, PU1, PU3, PU7, PU12, and PU14.
Page 101 CHAPTER 4 PORT FUNCTIONS (3) Input switch control register (ISC) This register is used to receive a status signal transmitted from the master during LIN (Local Interconnect Network) reception. The input signal is switched by setting ISC. For the port configuration during LIN reception, refer to Figure 14-3 Port Configuration for LIN Reception Operation in CHAPTER 14 SERIAL INTERFACE UART6.
Page 102: Port Function Operations
CHAPTER 4 PORT FUNCTIONS 4.4 Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. 4.4.1 Writing to I/O port (1) Output mode A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin.
Page 103: Chapter 5 Clock Generator
CHAPTER 5 CLOCK GENERATOR 5.1 Functions of Clock Generator The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following three system clock oscillators are available. • X1 oscillator The X1 oscillator oscillates a clock of 2.0 to 10.0 MHz. Oscillation can be stopped by executing the STOP instruction or setting the main OSC control register (MOC) and processor clock control register (PCC).
Page 104: Configuration Of Clock Generator
CHAPTER 5 CLOCK GENERATOR 5.2 Configuration of Clock Generator The clock generator consists of the following hardware. Table 5-1. Configuration of Clock Generator Item Configuration Control registers Processor clock control register (PCC) Ring-OSC mode register (RCM) Main clock mode register (MCM) Main OSC control register (MOC) Oscillation stabilization time counter status register (OSTC) Oscillation stabilization time select register (OSTS)
Page 105: Registers Controlling Clock Generator
CHAPTER 5 CLOCK GENERATOR 5.3 Registers Controlling Clock Generator The following six registers are used to control the clock generator. • Processor clock control register (PCC) • Ring-OSC mode register (RCM) • Main clock mode register (MCM) • Main OSC control register (MOC) •...
Page 106 CHAPTER 5 CLOCK GENERATOR Figure 5-3. Format of Processor Clock Control Register (PCC) Note 1 Address: FFFBH After reset: 00H Symbol PCC2 PCC1 PCC0 Note 2 Control of X1 oscillator operation Oscillation possible Oscillation stopped Note 3 Subsystem clock feedback resistor selection On-chip feedback resistor used On-chip feedback resistor not used CPU clock status...
Page 107 CHAPTER 5 CLOCK GENERATOR The fastest instruction can be executed in 2 clocks of the CPU clock in the 78K0/KD1 Series. Therefore, the relationship between the CPU clock (f ) and minimum instruction execution time is as shown in the Table 5-2.
Page 108 CHAPTER 5 CLOCK GENERATOR (3) Main clock mode register (MCM) This register sets the CPU clock (X1 input clock/Ring-OSC clock). MCM can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 5-5. Format of Main Clock Mode Register (MCM) Note Address: FFA1H After reset: 00H...
Page 109 CHAPTER 5 CLOCK GENERATOR (4) Main OSC control register (MOC) This register selects the operation mode of the X1 input clock. This register is used to stop the X1 oscillator operation when the CPU is operating with the Ring-OSC clock. Therefore, this register is valid only when the CPU is operating with the Ring-OSC clock.
Page 110 CHAPTER 5 CLOCK GENERATOR (5) Oscillation stabilization time counter status register (OSTC) This is the status register of the X1 input clock oscillation stabilization time counter. If the Ring-OSC clock is used as the CPU clock, the X1 input clock oscillation stabilization time can be checked. OSTC can be read by a 1-bit or 8-bit memory manipulation instruction.
Page 111 CHAPTER 5 CLOCK GENERATOR (6) Oscillation stabilization time select register (OSTS) This register is used to select the X1 oscillation stabilization wait time when STOP mode is released. The wait time set by OSTS is valid only after STOP mode is released with the X1 input clock selected as CPU clock.
Page 112: System Clock Oscillator
CHAPTER 5 CLOCK GENERATOR 5.4 System Clock Oscillator 5.4.1 X1 oscillator The X1 oscillator oscillates with a crystal resonator or ceramic resonator (Standard: 8.38 MHz, 10 MHz when REGC pin is directly connected to V ) connected to the X1 and X2 pins. An external clock can be input to the X1 oscillator when the REGC pin is directly connected to V .
Page 113 CHAPTER 5 CLOCK GENERATOR Cautions 1. When using the X1 oscillator and subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the Figure 5-11 to avoid an adverse effect from wiring capacitance. • Keep the wiring length as short as possible. •...
Page 114 CHAPTER 5 CLOCK GENERATOR Figure 5-11. Examples of Incorrect Resonator Connection (2/2) (c) Wiring near high alternating current (d) Current flowing through ground line of oscillator (potential at points A, B, and C fluctuates) High current (e) Signals are fetched Remark When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively.
Page 115: When Subsystem Clock Is Not Used
• Clock to peripheral hardware The CPU starts operation when the on-chip Ring-OSC oscillator starts outputting after reset release in the 78K0/KD1 Series, thus enabling the following. (1) Enhancement of security function When the X1 input clock is set as the CPU clock by the default setting, the device cannot operate if the X1 input clock is damaged or badly connected and therefore does not operate after reset is released.
Page 116 CHAPTER 5 CLOCK GENERATOR (2) Improvement of performance Because the CPU can be started without waiting for the X1 input clock oscillation stabilization time, the total performance can be improved. A timing diagram of the CPU default start using Ring-OSC is shown in Figure 5-12. Figure 5-12.
Page 117 CHAPTER 5 CLOCK GENERATOR (e) Select the X1 input clock oscillation stabilization time (2 ) using the oscillation stabilization time select register (OSTS) when releasing STOP mode while X1 input clock is being used as the CPU clock. In addition, when releasing STOP mode while RESET is released and Ring-OSC clock is being used as the CPU clock, check the X1 input clock oscillation stabilization time using the oscillation stabilization time counter status register (OSTC).
Page 118 CHAPTER 5 CLOCK GENERATOR Figure 5-13. Status Transition Diagram (2/4) (2) When “Ring-OSC can be stopped by software” is selected by mask option (when subsystem clock is used) Status 6 CPU clock: f : Oscillation stopped : Oscillating/ oscillation stopped Interrupt MCC = 0 MCC = 1...
Page 119 CHAPTER 5 CLOCK GENERATOR Figure 5-13. Status Transition Diagram (3/4) (3) When “Ring-OSC cannot be stopped” is selected by mask option (when subsystem clock is not used) HALT HALT HALT instruction Interrupt Interrupt instruction Interrupt HALT instruction Status 3 Status 1 Status 2 Note 2 MCM0 = 0...
Page 120 CHAPTER 5 CLOCK GENERATOR Figure 5-13. Status Transition Diagram (4/4) (4) When “Ring-OSC cannot be stopped” is selected by mask option (when subsystem clock is used) Status 5 CPU clock: f : Oscillation stopped : Oscillating/ oscillation stopped Interrupt MCC = 0 MCC = 1 HALT instruction Status 4...
Page 121 CHAPTER 5 CLOCK GENERATOR Table 5-3. Relationship Between Operation Clocks in Each Operation Status Status Ring-OSC Oscillator Subsystem CPU Clock Prescaler Clock Supplied Oscillator Clock After to Peripherals Oscillator Release Note 1 Note 2 MCM0 = 0 MCM0 = 1 Operation Mode RSTOP = 0...
Page 122: Time Required To Switch Between Ring-Osc Clock And X1 Input Clock
CHAPTER 5 CLOCK GENERATOR 5.6 Time Required to Switch Between Ring-OSC Clock and X1 Input Clock Bit 0 (MCM0) of the main clock mode register (MCM) is used to switch between the Ring-OSC clock and X1 input clock. In the actual switching operation, switching does not occur immediately after MCM0 rewrite; several instructions are executed using the pre-switch clock after switching MCM0 (see Table 5-5).
Page 123: Changing System Clock And Cpu Clock Settings
CHAPTER 5 CLOCK GENERATOR 5.7 Changing System Clock and CPU Clock Settings 5.7.1 Time required for switching between system clock and CPU clock The system clock and CPU clock can be switched using bits 0 to 2 (PCC0 to PCC2) and bit 4 (CSS) of the processor clock control register (PCC).
Page 124: Clock Switching Flowchart And Register Setting
CHAPTER 5 CLOCK GENERATOR 5.8 Clock Switching Flowchart and Register Setting 5.8.1 Switching from Ring-OSC clock to X1 input clock Figure 5-14. Switching from Ring-OSC Clock to X1 Input Clock (Flowchart) After reset release PCC = 00H RCM = 00H ;...
Page 125: Switching From X1 Input Clock To Ring-Osc Clock
CHAPTER 5 CLOCK GENERATOR 5.8.2 Switching from X1 input clock to Ring-OSC clock Figure 5-15. Switching from X1 Input Clock to Ring-OSC Clock (Flowchart) Register setting PCC.7 (MCC) = 0 ; X1 oscillation in X1 input PCC.4 (CSS) = 0 ;...
Page 126: Switching From X1 Input Clock To Subsystem Clock
CHAPTER 5 CLOCK GENERATOR 5.8.3 Switching from X1 input clock to subsystem clock Figure 5-16. Switching from X1 Input Clock to Subsystem Clock (Flowchart) Register setting PCC.7 (MCC) = 0 ; X1 oscillation in X1 input PCC.4 (CSS) = 0 ;...
Page 127: Switching From Subsystem Clock To X1 Input Clock
CHAPTER 5 CLOCK GENERATOR 5.8.4 Switching from subsystem clock to X1 input clock Figure 5-17. Switching from Subsystem Clock to X1 Input Clock (Flowchart) PCC.4 (CSS) = 1 ; Subsystem clock operation MCM = 03H No: X1 oscillating MCC = 1? ;...
Page 128: Register Settings
CHAPTER 5 CLOCK GENERATOR 5.8.5 Register settings Table 5-7. Clock and Register Setting Mode Setting Flag Status Flag PCC Register Register Register Register Register Register Note 1 MCM0 MSTOP RSTOP Note 2 X1 input clock Ring-OSC oscillating Ring-OSC stopped Ring-OSC clock X1 oscillating Note 3 X1 stopped...
Page 129: Chapter 6 16-Bit Timer/Event Counter 00
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.1 Functions of 16-Bit Timer/Event Counter 00 16-bit timer/event counter 00 has the following functions. • Interval timer • PPG output • Pulse width measurement • External event counter • Square-wave output • One-shot pulse output (1) Interval timer 16-bit timer/event counter 00 generates an interrupt request at the preset time interval.
Page 130: Configuration Of 16-Bit Timer/Event Counter 00
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.2 Configuration of 16-Bit Timer/Event Counter 00 16-bit timer/event counter 00 consists of the following hardware. Table 6-1. Configuration of 16-Bit Timer/Event Counter 00 Item Configuration 16 bits × 1 (TM00) Timer counter 16-bit timer capture/compare register: 16 bits × 2 (CR000, CR010) Register Timer output 1 (TO00)
Page 131 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (1) 16-bit timer counter 00 (TM00) TM00 is a 16-bit read-only register that counts count pulses. The counter is incremented in synchronization with the rising edge of the input clock. The count value is reset to 0000H in the following cases.
Page 132 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 CR000 can be set by a 16-bit memory manipulation instruction. RESET input clears CR000 to 0000H. Cautions 1. Set a value other than 0000H in CR000 in the mode in which clear & start occurs on a match of TM00 and CR000.
Page 133: Registers Controlling 16-Bit Timer/Event Counter 00
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.3 Registers Controlling 16-Bit Timer/Event Counter 00 The following five registers are used to control 16-bit timer/event counter 00. • 16-bit timer mode control register 00 (TMC00) • Capture/compare control register 00 (CRC00) • 16-bit timer output control register 00 (TOC00) •...
Page 134 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-2. Format of 16-Bit Timer Mode Control Register 00 (TMC00) Address FFBAH After reset: 00H Symbol TMC00 TMC003 TMC002 TMC001 OVF00 TMC003 TMC002 TMC001 Operating mode and clear TO00 output timing selection Interrupt request generation mode selection Operation stop No change...
Page 135 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (2) Capture/compare control register 00 (CRC00) This register controls the operation of the 16-bit timer capture/compare registers (CR000, CR010). CRC00 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears CRC00 to 00H. Figure 6-3.
Page 136 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-4. Format of 16-Bit Timer Output Control Register 00 (TOC00) Address: FFBDH After reset: 00H Symbol TOC00 OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00 OSPT00 One-shot pulse output trigger control via software No one-shot pulse trigger One-shot pulse trigger OSPE00 One-shot pulse output operation control...
Page 137 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (4) Prescaler mode register 00 (PRM00) This register is used to set the 16-bit timer counter 00 (TM00) count clock and TI000 and TI010 input valid edges. PRM00 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears PRM00 to 00H.
Page 138 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (5) Port mode register 0 (PM0) This register sets port 0 input/output in 1-bit units. When using the P01/TO00/TI010 pin for timer output, set PM01 and the output latch of P01 to 0. PM0 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM0 to FFH.
Page 139: Operation Of 16-Bit Timer/Event Counter 00
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4 Operation of 16-Bit Timer/Event Counter 00 6.4.1 Interval timer operation Setting 16-bit timer mode control register 00 (TMC00) and capture/compare control register 00 (CRC00) as shown in Figure 6-7 allows operation as an interval timer. Interrupt requests are generated repeatedly using the count value preset in 16-bit timer capture/compare register 000 (CR000) as the interval.
Page 140 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-8. Interval Timer Configuration Diagram 16-bit timer capture/compare register 000 (CR000) INTTM000 16-bit timer counter 00 OVF00 (TM00) Noise TI000/P00 eliminator Clear circuit Figure 6-9. Timing of Interval Timer Operation Count clock TM00 count value 0000H 0001H 0000H 0001H...
Page 141: Ppg Output Operations
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.2 PPG output operations Setting 16-bit timer mode control register 00 (TMC00) and capture/compare control register 00 (CRC00) as shown in Figure 6-10 allows operation as PPG (Programmable Pulse Generator) output. In the PPG output operation, rectangular waves are output from the TO00 pin with the pulse width and the cycle that correspond to the count values preset in 16-bit timer capture/compare register 010 (CR010) and in 16-bit timer capture/compare register 000 (CR000), respectively.
Page 142 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-11. Configuration of PPG Output 16-bit timer capture/compare register 000 (CR000) Clear 16-bit timer counter 00 circuit (TM00) Noise TI000/P00 eliminator TO00/TI010/P01 16-bit timer capture/compare register 010 (CR010) Figure 6-12. PPG Output Operation Timing Count clock TM00 count value 0000H...
Page 143: Pulse Width Measurement Operations
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.3 Pulse width measurement operations It is possible to measure the pulse width of the signals input to the TI000 pin and TI010 pin using 16-bit timer counter 00 (TM00). There are two measurement methods: measuring with TM00 used in free-running mode, and measuring by restarting the timer in synchronization with the edge of the signal input to the TI000 pin.
Page 144 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-14. Configuration Diagram for Pulse Width Measurement with Free-Running Counter 16-bit timer counter 00 OVF00 (TM00) 16-bit timer capture/compare TI000 register 010 (CR010) INTTM010 Internal bus Figure 6-15. Timing of Pulse Width Measurement Operation with Free-Running Counter and One Capture Register (with Both Edges Specified) Count clock 0000H...
Page 145 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (2) Measurement of two pulse widths with free-running counter When 16-bit timer counter 00 (TM00) is operated in free-running mode (see Figure 6-16), it is possible to simultaneously measure the pulse widths of the two signals input to the TI000 pin and the TI010 pin. When the edge specified by bits 4 and 5 (ES000 and ES001) of prescaler mode register 00 (PRM00) is input to the TI000 pin, the value of TM00 is taken into 16-bit timer capture/compare register 010 (CR010) and an interrupt request signal (INTTM010) is set.
Page 146 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 • • • • Capture operation (free-running mode) The capture register operation when capture trigger is input is shown below. Figure 6-17. CR010 Capture Operation with Rising Edge Specified Count clock TM00 N – 3 N –...
Page 147 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (3) Pulse width measurement with free-running counter and two capture registers When 16-bit timer counter 00 (TM00) is operated in free-running mode (see Figure 6-19), it is possible to measure the pulse width of the signal input to the TI000 pin. When the edge specified by bits 4 and 5 (ES000 and ES001) of prescaler mode register 00 (PRM00) is input to the TI000 pin, the value of TM00 is taken into 16-bit timer capture/compare register 010 (CR010) and an interrupt request signal (INTTM010) is set.
Page 148 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-20. Timing of Pulse Width Measurement Operation with Free-Running Counter and Two Capture Registers (with Rising Edge Specified) Count clock TM00 count value 0000H 0001H D0 + 1 D1 + 1 FFFFH 0000H D2 + 1 TI000 pin input CR010 capture value...
Page 149 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (4) Pulse width measurement by means of restart When input of a valid edge to the TI000 pin is detected, the count value of 16-bit timer counter 00 (TM00) is taken into 16-bit timer capture/compare register 010 (CR010), and then the pulse width of the signal input to the TI000 pin is measured by clearing TM00 and restarting the count operation (see Figure 6-21).
Page 150: External Event Counter Operation
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.4 External event counter operation The external event counter counts the number of external clock pulses input to the TI000 pin using 16-bit timer counter 00 (TM00). TM00 is incremented each time the valid edge specified by prescaler mode register 00 (PRM00) is input. When the TM00 count value matches the 16-bit timer capture/compare register 000 (CR000) value, TM00 is cleared to 0 and the interrupt request signal (INTTM000) is generated.
Page 151 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-24. Configuration Diagram of External Event Counter 16-bit timer capture/compare register 000 (CR000) Match INTTM000 Clear 16-bit timer counter 00 (TM00) OVF00 Noise eliminator 16-bit timer capture/compare Valid edge of TI000 Noise eliminator register 010 (CR010) Internal bus Figure 6-25.
Page 152: Square-Wave Output Operation
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.5 Square-wave output operation A square wave with any selected frequency can be output at intervals of the count value preset to 16-bit timer capture/compare register 000 (CR000). The TO00 pin output status is reversed at intervals of the count value preset to CR000 by setting bit 0 (TOE00) and bit 1 (TOC001) of 16-bit timer output control register 00 (TOC00) to 1.
Page 153: One-Shot Pulse Output Operation
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.6 One-shot pulse output operation 16-bit timer/event counter 00 can output a one-shot pulse in synchronization with a software trigger or an external trigger (TI000 pin input). (1) One-shot pulse output with software trigger A one-shot pulse can be output from the TO00 pin by setting 16-bit timer mode control register 00 (TMC00), capture/compare control register 00 (CRC00), and 16-bit timer output control register 00 (TOC00) as shown in Figure 6-27, and by setting bit 6 (OSPT00) of the TOC00 register to 1 by software.
Page 154 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-28. Control Register Settings for One-Shot Pulse Output with Software Trigger (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 OVF00 TMC00 Free-running mode (b) Capture/compare control register 00 (CRC00) CRC002 CRC001 CRC000 CRC00 CR000 as compare register CR010 as compare register...
Page 155 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-29. Timing of One-Shot Pulse Output Operation with Software Trigger Set TMC00 to 0CH (TM00 count starts) Count clock TM00 count 0000H 0001H N + 1 0000H N – 1 M – 1 M + 1 M + 2 CR010 set value CR000 set value...
Page 156 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-30. Control Register Settings for One-Shot Pulse Output with External Trigger (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 OVF00 TMC00 Clears and starts at valid edge of TI000 pin (b) Capture/compare control register 00 (CRC00) CRC002 CRC001 CRC000 CRC00...
Page 157 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-31. Timing of One-Shot Pulse Output Operation with External Trigger (with Rising Edge Specified) Set TMC00 to 08H (TM00 count starts) Count clock M − 2 M − 1 TM00 count value 0000H 0001H 0000H N + 1 N + 2...
Page 158: Cautions For 16-Bit Timer/Event Counter 00
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.5 Cautions for 16-Bit Timer/Event Counter 00 (1) Timer start errors An error of up to one clock may occur in the time required for a match signal to be generated after timer start. This is because 16-bit timer counter 00 (TM00) is started asynchronously to the count clock.
Page 159 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (4) Capture register data retention timing If the valid edge of the TI000 pin is input during 16-bit timer capture/compare register 010 (CR010) read, CR010 performs a capture operation. However, the value read at this time is not guaranteed. The interrupt request flag (TMIF010) is set upon detection of the valid edge.
Page 160 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (7) Operation of OVF00 flag <1> The OVF00 flag is set to 1 in the following case. When of the following modes: the mode in which clear & start occurs on a match between TM00 and CR000, the mode in which clear &...
Page 161 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (10) Capture operation <1> If TI000 valid edge is specified as the count clock, a capture operation by the capture register specified as the trigger for TI000 is not possible. <2> To ensure the reliability of the capture operation, the capture trigger requires a pulse two times longer than the count clock selected by prescaler mode register 00 (PRM00).
Page 162: Chapter 7 8-Bit Timer/Event Counters 50 And 51
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 7.1 Functions of 8-Bit Timer/Event Counters 50 and 51 8-bit timer/event counters 50 and 51 have the following functions. • Interval timer • External event counter • Square-wave output • PWM output Figures 7-1 and 7-2 show the block diagrams of 8-bit timer/event counters 50 and 51.
Page 163 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 7-2. Block Diagram of 8-Bit Timer/Event Counter 51 Internal bus 8-bit timer compare Selector INTTM51 register 51 (CR51) TI51/TO51/P33/INTP4 Match 8-bit timer TO51/TI51/P33/INTP4 counter 51 (TM51) Clear Invert level Selector TCE51 TMC516 LVS51 LVR51 TMC511 TOE51 TCL512 TCL511 TCL510 8-bit timer mode control Timer clock selection...
Page 164: Configuration Of 8-Bit Timer/Event Counters 50 And 51
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 7.2 Configuration of 8-Bit Timer/Event Counters 50 and 51 8-bit timer/event counters 50 and 51 consist of the following hardware. Table 7-1. Configuration of 8-Bit Timer/Event Counters 50 and 51 Item Configuration Timer register 8-bit timer counter 5n (TM5n) Register...
Page 165: Registers Controlling 8-Bit Timer/Event Counters 50 And 51
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 7.3 Registers Controlling 8-Bit Timer/Event Counters 50 and 51 The following three registers are used to control 8-bit timer/event counters 50 and 51. • Timer clock selection register 5n (TCL5n) • 8-bit timer mode control register 5n (TMC5n) •...
Page 166 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 7-4. Format of Timer Clock Selection Register 51 (TCL51) Address: FF8CH After reset: 00H Symbol TCL51 TCL512 TCL511 TCL510 TCL512 TCL511 TCL510 Count clock selection TI51 falling edge TI51 rising edge (10 MHz) /2 (5 MHz) (625 kHz)
Page 167 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (2) 8-bit timer mode control register 5n (TMC5n) TMC5n is a register that performs the following five types of settings. <1> 8-bit timer counter 5n (TM5n) count operation control <2> 8-bit timer counter 5n (TM5n) operating mode selection <3>...
Page 168 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 7-6. Format of 8-Bit Timer Mode Control Register 51 (TMC51) Note Address: FF43H After reset: 00H Symbol TMC51 TCE51 TMC516 LVS51 LVR51 TMC511 TOE51 TCE51 TM51 count operation control After clearing to 0, count operation disabled (counter stopped) Count operation start TMC516 TM51 operating mode selection...
Page 169 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Cautions 1. To clear TCE5n to 0, set the interrupt mask flag (TMMK5n) to 1 beforehand. Otherwise, an interrupt may occur when TCE5n is cleared. TCE5n is cleared to 0 as follows. TMMK5n = 1;...
Page 170 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (3) Port mode register 1 (PM1) and port mode register 3 (PM3) These registers set ports 1 and 3 input/output in 1-bit units. When using the P17/TO50/TI50 and P33/TO51/TI51/INTP4 pins for timer output, set PM17 and PM33 and the output latches of P17 and P33 to 0.
Page 171: Operations Of 8-Bit Timer/Event Counters 50 And 51
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 7.4 Operations of 8-Bit Timer/Event Counters 50 and 51 7.4.1 Operation as interval timer 8-bit timer/event counter 5n operates as an interval timer that generates interrupt requests repeatedly at intervals of the count value preset to 8-bit timer compare register 5n (CR5n). When the count value of 8-bit timer counter 5n (TM5n) matches the value set to CR5n, counting continues with the TM5n value cleared to 0 and an interrupt request signal (INTTM5n) is generated.
Page 172 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 7-9. Interval Timer Operation Timing (2/2) (b) When CR5n = 00H Count clock TM5n CR5n TCE5n INTTM5n TO5n Interval time (c) When CR5n = FFH Count clock TM5n CR5n TCE5n INTTM5n Interrupt acknowledged Interrupt acknowledged...
Page 173: Operation As External Event Counter
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 7.4.2 Operation as external event counter The external event counter counts the number of external clock pulses to be input to TI5n by 8-bit timer counter 5n (TM5n). TM5n is incremented each time the valid edge specified by timer clock selection register 5n (TCL5n) is input. Either the rising or falling edge can be selected.
Page 174: Square-Wave Output Operation
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 7.4.3 Square-wave output operation A square wave with any selected frequency is output at intervals of the value preset to 8-bit timer compare register 5n (CR5n). The TO5n pin output status is inverted at intervals of the count value preset to CR5n by setting bit 0 (TOE5n) of 8- bit timer mode control register 5n (TMC5n) to 1.
Page 175 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 7-11. Square-Wave Output Operation Timing Count clock TMn count value N – 1 N – 1 Count start CR5n Note TO5n Note The initial value of TO5n output can be set by bits 2 and 3 (LVR5n, LVS5n) of 8-bit timer mode control register 5n (TMC5n).
Page 176: Pwm Output Operation
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 7.4.4 PWM output operation 8-bit timer/event counter 5n operates as a PWM output when bit 6 (TMC5n6) of 8-bit timer mode control register 5n (TMC5n) is set to 1. The duty ratio pulse determined by the value set to 8-bit timer compare register 5n (CR5n) is output from TO5n. Set the active level width of the PWM pulse to CR5n;...
Page 177 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 7-12. PWM Output Operation Timing (a) Basic operation (active level = H) Count clock TM5n 00H 01H FFH 00H 01H 02H N N + 1 FFH 00H 01H 02H CR5n TCE5n INTTM5n TO5n Active level...
Page 178: Cautions For 8-Bit Timer/Event Counters 50 And 51
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (2) Operation with CR5n changed Figure 7-13. Timing of Operation with CR5n Changed (a) CR5n value is changed from N to M before clock rising edge of FFH → → → → Value is reloaded to CR5n at overflow immediately after change. Count clock TM5n N N + 1 N + 2...
Page 179: Chapter 8 8-Bit Timers H0 And H1
CHAPTER 8 8-BIT TIMERS H0 AND H1 8.1 Functions of 8-Bit Timers H0 and H1 8-bit timers H0 and H1 have the following functions. • 8-bit-accuracy interval timer • 8-bit-accuracy PWM pulse generator mode • 8-bit-accuracy carrier generator mode (8-bit timer H1 only) 8.2 Configuration of 8-Bit Timers H0 and H1 8-bit timers H0 and H1 consist of the following hardware.
Page 180 CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-1. Block Diagram of 8-Bit Timer H0 Internal bus 8-bit timer H mode control register 0 (TMHMD0) 8-bit timer H 8-bit timer H TMHE0 CKS02 CKS01 CKS00 TMMD01TMMD00 TOLEV0 TOEN0 compare register compare register 10 (CMP10) 00 (CMP00)
Page 181 CHAPTER 8 8-BIT TIMERS H0 AND H1 (1) 8-bit timer H compare register 0n (CMP0n) This register can be read/written by an 8-bit memory manipulation instruction. RESET input clears this register to 00H. After reset: 00H Address: FF18H, FF1AH CMP0n Caution This register cannot be rewritten during timer count operation.
Page 182: Registers Controlling 8-Bit Timers H0 And H1
CHAPTER 8 8-BIT TIMERS H0 AND H1 8.3 Registers Controlling 8-Bit Timers H0 and H1 8-bit timers H0 and H1 are controlled by 8-bit timer H mode registers 0 and 1 (TMHMD0, TMHMD1) and 8-bit timer Note H carrier control register 1 (TMCYC1) Note 8-bit timer H1 only (1) 8-bit timer H mode registers 0 and 1 (TMHMD0, TMHMD1) These registers control the mode of timer H.
Page 183 CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-3. Format of 8-Bit Timer H Mode Register 0 (TMHMD0) Address: FF69H After reset: 00H TMHMD0 TMHE0 CKS02 CKS01 CKS00 TMMD01 TMMD00 TOLEV0 TOEN0 TMHE0 Timer operation enable Stops timer count operation Enables timer count operation (count operation started by inputting clock) CKS02 CKS01...
Page 184 CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-4. Format of 8-Bit Timer H Mode Register 1 (TMHMD1) Address: FF6CH After reset: 00H TMHMD1 TMHE1 CKS12 CKS11 CKS10 TMMD11 TMMD10 TOLEV1 TOEN1 TMHE1 Timer operation enable Stops timer count operation Enables timer count operation (count operation started by inputting clock) CKS12 CKS11...
Page 185 CHAPTER 8 8-BIT TIMERS H0 AND H1 (2) 8-bit timer H carrier control register 1 (TMCYC1) This register controls the remote control output and carrier pulse output status of 8-bit timer H1. This register can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H.
Page 186: Operation Of 8-Bit Timers H0 And H1
CHAPTER 8 8-BIT TIMERS H0 AND H1 8.4 Operation of 8-Bit Timers H0 and H1 8.4.1 Operation as interval timer When 8-bit timer counter Hn and compare register 0n (CMP0n) match, an interrupt request signal (INTTMHn) is generated and 8-bit timer counter Hn is cleared to 00H. Compare register 1n (CMP1n) is not used in interval timer mode.
Page 187 CHAPTER 8 8-BIT TIMERS H0 AND H1 (2) Timing chart The timing in interval timer mode is shown below. Figure 8-7. Timing of Interval Timer Operation (1/2) (a) Basic operation Count clock Count start 01H 00H 8-bit timer counter Hn Clear Clear CMP0n...
Page 188 CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-7. Timing of Interval Timer Operation (2/2) (b) Operation when CMP0n = FFH Count clock Count start 8-bit timer counter Hn Clear Clear CMP0n TMHEn INTTMHn TOHn Interval time (c) Operation when CMP0n = 00H Count clock Count start 8-bit timer counter Hn...
Page 189: Operation As Pwm Pulse Generator
CHAPTER 8 8-BIT TIMERS H0 AND H1 8.4.2 Operation as PWM pulse generator In PWM mode, a pulse with an arbitrary duty and arbitrary cycle can be output. 8-bit timer compare register 0n (CMP0n) controls the cycle of timer output (TOHn). Rewriting the CMP0n register during timer operation is prohibited.
Page 190 CHAPTER 8 8-BIT TIMERS H0 AND H1 <4> When 8-bit timer counter Hn and the CMP1n register match, TOHn output becomes inactive and the compare register to be compared with 8-bit timer counter Hn is changed from the CMP1n register to the CMP0n register.
Page 191 CHAPTER 8 8-BIT TIMERS H0 AND H1 (2) Timing chart The operation timing in PWM mode is shown below. Caution Make sure that the CMP1n register setting value (M) and CMP0n register setting value (N) are within the following range. 00H ≤...
Page 192 CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-9. Operation Timing in PWM Pulse Generator Mode (2/4) (b) Operation when CMP0n = FFH, CMP1n = 00H Count clock 8-bit timer counter Hn 00H 01H FFH 00H 01H 02H FFH 00H 01H 02H FFH 00H CMP0n...
Page 193 CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-9. Operation Timing in PWM Pulse Generator Mode (3/4) (d) Operation when CMP0n = 01H, CMP1n = 00H Count clock 01H 00H 01H 00H 00H 01H 00H 01H 8-bit timer counter Hn CMP0n CMP1n TMHEn...
Page 194 CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-9. Operation Timing in PWM Pulse Generator Mode (4/4) (e) Operation by changing CMP1n (CMP1n = 01H → → → → 03H, CMP0n = A5H) Count clock 8-bit timer counter Hn 00H 01H 02H A5H 00H 01H 02H 03H A5H 00H 01H 02H 03H A5H 00H...
Page 195: Carrier Generator Mode Operation (8-Bit Timer H1 Only)
CHAPTER 8 8-BIT TIMERS H0 AND H1 8.4.3 Carrier generator mode operation (8-bit timer H1 only) The carrier clock generated by 8-bit timer H1 is output in the cycle set by 8-bit timer/event counter 51. In carrier generator mode, the output of the 8-bit timer H1 carrier pulse is controlled by 8-bit timer/event counter 51, and the carrier pulse is output from the TOH1 output.
Page 196 CHAPTER 8 8-BIT TIMERS H0 AND H1 To control the carrier pulse output during a count operation, the NRZ1 and NRZB1 bits of the TMCYC1 register have a master and slave bit configuration. The NRZ1 bit is read-only but the NRZB1 bit can be read and written. The INTTM51 signal is synchronized with the 8-bit timer H1 count clock and output as the INTTM5H1 signal.
Page 197 CHAPTER 8 8-BIT TIMERS H0 AND H1 (3) Usage Outputs an arbitrary carrier clock from the TOH1 pin. <1> Set each register. Figure 8-12. Register Setting in Carrier Generator Mode Setting 8-bit timer H mode register 1 (TMHMD1) TMHE1 CKS12 CKS11 CKS10 TMMD11...
Page 198 CHAPTER 8 8-BIT TIMERS H0 AND H1 If the setting value of the CMP01 register is 1, the setting value of the CMP11 register is M, and the count clock frequency is f , the carrier clock output cycle and duty ratio are as follows. Carrier clock output cycle = (1 + M + 2)/f Duty ratio = High-level width : Low-level width = ( M + 1) : (1 + 1) Cautions 1.
Page 199 CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-13. Carrier Generator Mode Operation Timing (1/3) (a) Operation when CMP01 = 1, CMP11 = 1 8-bit timer H1 count clock 8-bit timer counter N 00H N 00H N 00H N 00H N 00H H1 count value CMP01...
Page 200 CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-13. Carrier Generator Mode Operation Timing (2/3) (b) Operation when CMP01 = 1, CMP11 = M (operation when carrier clock phase is asynchronous to NRZ1 phase) 8-bit timer H1 count clock 8-bit timer counter N 00H 01H M 00H N 00H 01H...
Page 201 CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-13. Carrier Generator Mode Operation Timing (3/3) (c) Operation when CMP11 is changed 8-bit timer H1 count clock 8-bit timer counter 00H 01H 00H 01H H1 count value CMP01 <3> <3>’ CMP11 M (L) TMHE1 INTTMH1...
Page 202: Chapter 9 Watch Timer
CHAPTER 9 WATCH TIMER 9.1 Functions of Watch Timer The watch timer has the following functions. • Watch timer • Interval timer The watch timer and the interval timer can be used simultaneously. Figure 9-1 shows the watch timer block diagram. Figure 9-1.
Page 203 CHAPTER 9 WATCH TIMER (1) Watch timer When the X1 input clock or subsystem clock is used, interrupt requests (INTWT) are generated at preset intervals. Table 9-1. Watch Timer Interrupt Time Interrupt Time When Operated at f = 32.768 kHz When Operated at f = 10 MHz 488 µ...
Page 204: Configuration Of Watch Timer
CHAPTER 9 WATCH TIMER 9.2 Configuration of Watch Timer The watch timer consists of the following hardware. Table 9-3. Watch Timer Configuration Item Configuration 5 bits × 1 Counter 11 bits × 1 Prescaler Control register Watch timer operation mode register (WTM) 9.3 Register Controlling Watch Timer The watch timer is controlled by the watch timer operation mode register (WTM).
Page 205 CHAPTER 9 WATCH TIMER Figure 9-2. Format of Watch Timer Operation Mode Register (WTM) Address: FF6FH After reset: 00H Symbol WTM7 WTM6 WTM5 WTM4 WTM3 WTM2 WTM1 WTM0 WTM7 Watch timer count clock selection (78.125 kHz) (32.768 kHz) WTM6 WTM5 WTM4 Prescaler interval time selection WTM3...
Page 206: Watch Timer Operations
CHAPTER 9 WATCH TIMER 9.4 Watch Timer Operations 9.4.1 Watch timer operation The watch timer generates an interrupt request (INTWT) at a specific time interval by using the X1 input clock or subsystem clock. When bit 0 (WTM0) and bit 1 (WTM1) of the watch timer operation mode register (WTM) are set to 1, the count operation starts.
Page 207: Interval Timer Operation
CHAPTER 9 WATCH TIMER 9.4.2 Interval timer operation The watch timer operates as interval timer which generates interrupt requests (INTWTI) repeatedly at an interval of the preset count value. The interval time can be selected with bits 4 to 6 (WTM4 to WTM6) of the watch timer operation mode register (WTM).
Page 208 CHAPTER 9 WATCH TIMER Figure 9-3. Operation Timing of Watch Timer/Interval Timer 5-bit counter Overflow Overflow Start Count clock Watch timer interrupt INTWT Interrupt time of watch timer (0.5 s) Interrupt time of watch timer (0.5 s) Interval timer interrupt INTWTI Interval time n ×...
Page 209: Chapter 10 Watchdog Timer
CHAPTER 10 WATCHDOG TIMER 10.1 Functions of Watchdog Timer The watchdog timer detects an inadvertent program loop. If a program loop is detected, an internal reset signal (WDTRES) is generated. When a reset occurs due to the watchdog timer, bit 4 (WDTRF) of the reset control flag register (RESF) is set to 1. For details of RESF, refer to CHAPTER 19 RESET FUNCTION.
Page 210 CHAPTER 10 WATCHDOG TIMER Table 10-2. Mask Option Setting and Watchdog Timer Operation Mode Mask Option Ring-OSC Cannot Be Stopped Ring-OSC Can Be Stopped by Software • Selectable by software (f Note 1 Watchdog timer clock Fixed to f source stopped) •...
Page 211: Configuration Of Watchdog Timer
CHAPTER 10 WATCHDOG TIMER 10.2 Configuration of Watchdog Timer The watchdog timer consists of following hardware. Table 10-3. Configuration of Watchdog Timer Item Configuration Control registers Watchdog timer mode register (WDTM) Watchdog timer enable register (WDTE) Figure 10-1. Block Diagram of Watchdog Timer Clock Output WDTRES...
Page 212: Registers Controlling Watchdog Timer
CHAPTER 10 WATCHDOG TIMER 10.3 Registers Controlling Watchdog Timer The watchdog timer is controlled by the following two registers. • Watchdog timer mode register (WDTM) • Watchdog timer enable register (WDTE) (1) Watchdog timer mode register (WDTM) This register sets the overflow time and operation clock of the watchdog timer. This register can be set by an 8-bit memory manipulation instruction and can be read many times, but can be written only once after reset is released.
Page 213 CHAPTER 10 WATCHDOG TIMER Cautions 3. After reset is released, WDTM can be written only once by an 8-bit memory manipulation instruction. If writing attempted a second time, an internal reset signal is generated. 4. WDTM cannot be set by a 1-bit memory manipulation instruction. Remarks 1.
Page 214: Operation Of Watchdog Timer
CHAPTER 10 WATCHDOG TIMER 10.4 Operation of Watchdog Timer 10.4.1 Watchdog timer operation when “Ring-OSC cannot be stopped” is selected by mask option The operation clock of watchdog timer is fixed to the Ring-OSC. After reset is released, operation is started at the maximum cycle (bits 2, 1, and 0 (WDCS2, WDCS1, WDCS0) of the watchdog timer mode register (WDTM) = 1, 1, 1).
Page 215: Watchdog Timer Operation When "Ring-Osc Can Be Stopped By Software" Is Selected By Mask Option
CHAPTER 10 WATCHDOG TIMER 10.4.2 Watchdog timer operation when “Ring-OSC can be stopped by software” is selected by mask option The operation clock of the watchdog timer can be selected as either the Ring-OSC clock or the X1 input clock. After reset is released, operation is started at the maximum cycle (bits 2, 1, and 0 (WDCS2, WDCS1, WDCS0) of the watchdog timer mode register (WDTM) = 1, 1, 1) of the Ring-OSC clock.
Page 216: Watchdog Timer Operation In Stop Mode (When "Ring-Osc Can Be Stopped By Software" Is Selected By Mask Option)
CHAPTER 10 WATCHDOG TIMER 10.4.3 Watchdog timer operation in STOP mode (when “Ring-OSC can be stopped by software” is selected by mask option) The watchdog timer stops counting during STOP instruction execution regardless of whether the X1 input clock or Ring-OSC clock is being used.
Page 217 CHAPTER 10 WATCHDOG TIMER (3) When the CPU clock is the Ring-OSC clock (f ) and the watchdog timer operation clock is the X1 input clock (f ) when the STOP instruction is executed When the STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is released, counting is stopped until the timing of <1>...
Page 218: Watchdog Timer Operation In Halt Mode (When "Ring-Osc Can Be Stopped By Software" Is Selected By Mask Option)
CHAPTER 10 WATCHDOG TIMER (4) When CPU clock and watchdog timer operation clock are the Ring-OSC clocks (f ) during STOP instruction execution When the STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is released, counting is started again using the operation clock before the operation was stopped.
Page 219: Chapter 11 Clock Output Controller
CHAPTER 11 CLOCK OUTPUT CONTROLLER 11.1 Functions of Clock Output Controller The clock output controller is intended for carrier output during remote controlled transmission and clock output for supply to peripheral LSIs. The clock selected with the clock output selection register (CKS) is output. Figure 11-1 shows the block diagram of clock output controller.
Page 220: Configuration Of Clock Output Controller
CHAPTER 11 CLOCK OUTPUT CONTROLLER 11.2 Configuration of Clock Output Controller The clock output controller consists of the following hardware. Table 11-1. Clock Output Controller Configuration Item Configuration Control registers Clock output selection register (CKS) Note Port mode register 14 (PM14) Note See Figure 4-18 Block Diagram of P140.
Page 221 CHAPTER 11 CLOCK OUTPUT CONTROLLER Figure 11-2. Format of Clock Output Selection Register (CKS) Address: FF40H After reset: 00H Symbol CLOE CCS3 CCS2 CCS1 CCS0 CLOE PCL output enable/disable specification Clock division circuit operation stopped. PCL fixed to low level. Clock division circuit operation enabled.
Page 222 CHAPTER 11 CLOCK OUTPUT CONTROLLER (2) Port mode register 14 (PM14) This register sets port 14 input/output in 1-bit units. When using the P140/INTP6/PCL pin for clock output, set PM140 and the output latch of P140 to 0. PM14 is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM14 to FFH.
Page 223: Clock Output Controller Operations
CHAPTER 11 CLOCK OUTPUT CONTROLLER 11.4 Clock Output Controller Operations The clock pulse is output as the following procedure. <1> Select the clock pulse output frequency with bits 0 to 3 (CCS0 to CCS3) of the clock output selection register (CKS) (clock pulse output in disabled status).
Page 224: Chapter 12 A/D Converter
CHAPTER 12 A/D CONVERTER 12.1 Functions of A/D Converter The A/D converter converts an analog input signal into a digital value, and consists of up to eight channels (ANI0 to ANI7) with a resolution of 10 bits. The A/D converter has the following two functions. (1) 10-bit resolution A/D conversion 10-bit resolution A/D conversion is carried out repeatedly for one channel selected from analog inputs ANI0 to ANI7.
Page 225 CHAPTER 12 A/D CONVERTER Figure 12-2. Block Diagram of Power-Fail Detection Function PFCM PFEN ANI0/P20 ANI1/P21 ANI2/P22 INTAD ANI3/P23 A/D converter Comparator ANI4/P24 ANI5/P25 ANI6/P26 ANI7/P27 Power-fail comparison ADS2 ADS1 ADS0 PFEN PFCM threshold register (PFT) Analog input channel Power-fail comparison specification register mode register (PFM) (ADS)
Page 226: Configuration Of A/D Converter
CHAPTER 12 A/D CONVERTER 12.2 Configuration of A/D Converter The A/D converter consists of the following hardware. Table 12-1. Configuration of A/D Converter Item Configuration Analog input 8 channels (ANI0 to ANI7) Registers Successive approximation register (SAR) A/D conversion result register (ADCR) Control registers A/D converter mode register (ADM) Analog input channel specification register (ADS)
Page 227 CHAPTER 12 A/D CONVERTER (3) Sample & hold circuit The sample & hold circuit samples each analog input signal sequentially applied from the input circuit, and sends it to the voltage comparator. This circuit holds the sampled analog input voltage value during A/D conversion. (4) Voltage comparator The voltage comparator compares the analog input with the series resistor string output voltage.
Page 228: Registers Controlling A/D Converter
CHAPTER 12 A/D CONVERTER 12.3 Registers Controlling A/D Converter The following four registers are used to control the A/D converter. • A/D converter mode register (ADM) • Analog input channel specification register (ADS) • Power-fail comparison mode register (PFM) • Power-fail comparison threshold register (PFT) (1) A/D converter mode register (ADM) This register sets the conversion time for analog input to be A/D converted, and starts/stops conversion.
Page 229 CHAPTER 12 A/D CONVERTER Table 12-2. Settings of ADCS and ADCE ADCS ADCE A/D Conversion Operation Stop status (DC power consumption path does not exist) Conversion waiting mode (only reference voltage generator consumes power) Note Conversion mode (reference voltage generator operation stopped Conversion mode (reference voltage generator operates) Note Data of first conversion cannot be used.
Page 230 CHAPTER 12 A/D CONVERTER (2) Analog input channel specification register (ADS) This register specifies the input port of the analog voltage to be A/D converted. ADS can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 12-6.
Page 231 CHAPTER 12 A/D CONVERTER (3) Power-fail comparison mode register (PFM) The power-fail comparison mode register (PFM) is a register that controls the comparison operation. PFM can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 12-7.
Page 232: A/D Converter Operations
CHAPTER 12 A/D CONVERTER 12.4 A/D Converter Operations 12.4.1 Basic operations of A/D converter <1> Select one channel for A/D conversion with analog input channel specification register (ADS). <2> The voltage input to the selected analog input channel is sampled by the sample & hold circuit. <3>...
Page 233 CHAPTER 12 A/D CONVERTER Figure 12-9. Basic Operation of A/D Converter Conversion time Sampling time A/D converter Sampling A/D conversion operation Conversion Undefined result Conversion ADCR result INTAD A/D conversion operations are performed continuously until bit 7 (ADCS) of the A/D converter mode register (ADM) is reset (0) by software.
Page 234: Input Voltage And Conversion Results
CHAPTER 12 A/D CONVERTER 12.4.2 Input voltage and conversion results The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI7) and the A/D conversion result (stored in the A/D conversion result register (ADCR)) is shown by the following expression. ×...
Page 235: A/D Converter Operation Mode
CHAPTER 12 A/D CONVERTER 12.4.3 A/D converter operation mode The operation mode of the A/D converter is the select mode. One channel of analog input is selected from ANI0 to ANI7 by the analog input channel specification register (ADS) and A/D conversion is executed. In addition, the following two functions can be selected by setting of bit 7 (PFEN) of the power-fail comparison mode register (PFM).
Page 236 CHAPTER 12 A/D CONVERTER (2) Power-fail detection function (when PFEN = 1) By setting bit 7 (ADCS) of the A/D converter mode register (ADM) to 1 and bit 7 (PFEN) of the power-fail comparison mode register (PFM) to 1, the A/D conversion operation of the voltage applied to the analog input pin specified by the analog input channel specification register (ADS) is started.
Page 237 CHAPTER 12 A/D CONVERTER The setting methods are described below. • When used as A/D conversion operation <1> Set bit 0 (ADCE) of the A/D converter mode register (ADM) to 1. <2> Select the channel and conversion time using bits 2 to 0 (ADS2 to ADS0) of the analog input channel specification register (ADS) and bits 5 to 3 (FR2 to FR0) of ADM.
Page 238: How To Read A/D Converter Characteristics Table
CHAPTER 12 A/D CONVERTER 12.5 How to Read A/D Converter Characteristics Table Here, special terms unique to the A/D converter are explained. (1) Resolution This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage per bit of digital output is called 1LSB (Least Significant Bit).
Page 239 CHAPTER 12 A/D CONVERTER (4) Zero-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (1/2LSB) when the digital output changes from 0..000 to 0..001. If the actual measurement value is greater than the theoretical value, it shows the difference between the actual measurement value of the analog input voltage and the theoretical value (3/2LSB) when the digital output changes from 0……001 to 0……010.
Page 240: Cautions For A/D Converter
CHAPTER 12 A/D CONVERTER (8) Conversion time This expresses the time since sampling has been started until digital output is obtained. The sampling time is included in the conversion time in the characteristics table. (9) Sampling time This is the time the analog switch is turned on for the analog voltage to be sampled by the sample & hold circuit. Sampling time Conversion time...
Page 241 CHAPTER 12 A/D CONVERTER (3) Conflicting operations <1> Conflict between A/D conversion result register (ADCR) write and ADCR read by instruction upon the end of conversion ADCR read has priority. After the read operation, the new conversion result is written to ADCR. Old data can be read from ADCR at the timing of (1) and new data can be read from ADCR at the timing of (2) as shown in Figure 12-20.
Page 242 CHAPTER 12 A/D CONVERTER (4) Noise countermeasures To maintain the 10-bit resolution, attention must be paid to noise input to the AV pin and pins ANI0 to ANI7. Because the effect increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected externally, as shown in Figure 12-21, to reduce noise.
Page 243 CHAPTER 12 A/D CONVERTER (8) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the analog input channel specification register (ADS) is changed. Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion result and ADIF for the pre-change analog input may be set just before the ADS rewrite.
Page 244 CHAPTER 12 A/D CONVERTER (11) A/D converter sampling time and A/D conversion start delay time The A/D converter sampling time differs depending on the set value of the A/D converter mode register (ADM). The delay time exists until actual sampling is started after A/D converter operation is enabled. When using a set in which the A/D conversion time must be strictly observed, care is required for the contents shown in Figure 12-23 and Table 12-3.
Page 245: Chapter 13 Serial Interface Uart0
CHAPTER 13 SERIAL INTERFACE UART0 13.1 Functions of Serial Interface UART0 Serial interface UART0 has the following two modes. (1) Operation stop mode This mode is used when serial transfer is not executed and can enable a reduction in the power consumption. For details, refer to 13.4.1 Operation stop mode.
Page 246: Configuration Of Serial Interface Uart0
CHAPTER 13 SERIAL INTERFACE UART0 13.2 Configuration of Serial Interface UART0 Serial interface UART0 consists of the following hardware. Table 13-1. Configuration of Serial Interface UART0 Item Configuration Registers Receive buffer register 0 (RXB0) Receive shift register 0 (RXS0) Transmit shift register 0 (TXS0) Control registers Asynchronous serial interface operation mode register 0 (ASIM0) Asynchronous serial interface reception error status register 0 (ASIS0)
Page 247 Figure 13-1. Block Diagram of Serial Interface UART0 Filter D0/SI10/P11 Receive shift register 0 (RXS0) Asynchronous serial Asynchronous serial Reception control INTSR0 Receive buffer register 0 Baud rate interface operation mode interface reception error (RXB0) generator register 0 (ASIM0) status register 0 (ASIS0) Reception unit Internal bus TO50/TI50/P17...
Page 248 CHAPTER 13 SERIAL INTERFACE UART0 (1) Receive buffer register 0 (RXB0) This 8-bit register stores parallel data converted by receive shift register 0 (RXS0). Each time 1 byte of data has been received, new receive data is transferred to this register from receive shift register 0 (RXS0).
Page 249: Registers Controlling Serial Interface Uart0
CHAPTER 13 SERIAL INTERFACE UART0 13.3 Registers Controlling Serial Interface UART0 Serial interface UART0 is controlled by the following three registers. • Asynchronous serial interface operation mode register 0 (ASIM0) • Asynchronous serial interface reception error status register 0 (ASIS0) •...
Page 250 CHAPTER 13 SERIAL INTERFACE UART0 Figure 13-2. Format of Asynchronous Serial Interface Operation Mode Register 0 (ASIM0) (2/2) PS01 PS00 Transmission operation Reception operation Does not output parity bit. Reception without parity Note Outputs 0 parity. Reception as 0 parity Outputs odd parity.
Page 251 CHAPTER 13 SERIAL INTERFACE UART0 (2) Asynchronous serial interface reception error status register 0 (ASIS0) This register indicates an error status on completion of reception by serial interface UART0. It includes three error flag bits (PE0, FE0, OVE0). This register can be set by an 8-bit memory manipulation instruction and is read-only. RESET input clears this register to 00H if bit 7 (POWER0) and bit 5 (RXE0) of ASIM0 = 0.
Page 252 CHAPTER 13 SERIAL INTERFACE UART0 (3) Baud rate generator control register 0 (BRGC0) This register selects the base clock of serial interface UART0 and controls the baud rate. BRGC0 can be set by an 8-bit memory manipulation instruction. RESET input sets this register to 1FH. Figure 13-4.
Page 253: Operation Of Serial Interface Uart0
CHAPTER 13 SERIAL INTERFACE UART0 13.4 Operation of Serial Interface UART0 This section explains the two modes of serial interface UART0. 13.4.1 Operation stop mode In this mode, serial transfer cannot be executed, thus reducing the power consumption. In addition, the pins can be used as ordinary port pins in this mode.
Page 254: Asynchronous Serial Interface (Uart) Mode
CHAPTER 13 SERIAL INTERFACE UART0 13.4.2 Asynchronous serial interface (UART) mode In this mode, 1-byte data is transmitted/received following a start bit, and a full-duplex operation can be performed. A dedicated UART baud rate generator is incorporated, so that communication can be executed at a wide range of baud rates.
Page 255 CHAPTER 13 SERIAL INTERFACE UART0 PS01 PS00 Transmission operation Reception operation Does not output parity bit. Reception without parity Note Outputs 0 parity. Reception as 0 parity Outputs odd parity. Judges as odd parity. Outputs even parity. Judges as even parity. Specifies character length of transmit/receive data Character length of data = 7 bits Character length of data = 8 bits...
Page 256 CHAPTER 13 SERIAL INTERFACE UART0 (b) Asynchronous serial interface reception error status register 0 (ASIS0) This register indicates an error status on completion of reception by serial interface UART0. It includes three error flag bits (PE0, FE0, OVE0). This register can be set by an 8-bit memory manipulation instruction and is read-only. RESET input clears this register to 00H if bit 7 (POWER0) and bit 5 (RXE0) of ASIM0 = 0.
Page 257 CHAPTER 13 SERIAL INTERFACE UART0 (2) Communication operation (a) Normal transmit/receive data format Figure 13-5 shows the format of the transmit/receive data. Figure 13-5. Format of Normal UART Transmit/Receive Data 1 data frame Start Parity Stop bit Character bits One data frame consists of the following bits. •...
Page 258 CHAPTER 13 SERIAL INTERFACE UART0 (b) Parity types and operation The parity bit is used to detect a bit error in communication data. Usually, the same type of parity bit is used on both the transmission and reception sides. With even parity and odd parity, a 1-bit (odd number) error can be detected.
Page 259 CHAPTER 13 SERIAL INTERFACE UART0 (c) Transmission The T D0 pin outputs a high level when bit 7 (POWER0) of asynchronous serial interface mode register 0 (ASIM0) is set to 1. If bit 6 (TXE0) of ASIM0 is then set to 1, transmission is enabled. Transmission can be started by writing transmit data to transmit shift register 0 (TXS0).
Page 260 CHAPTER 13 SERIAL INTERFACE UART0 (d) Reception Reception is enabled and the R D0 pin input is sampled when bit 7 (POWER0) of asynchronous serial interface operation mode register 0 (ASIM0) is set to 1 and then bit 5 (RXE0) of ASIM0 is set to 1. The 5-bit counter of the baud rate generator starts counting when the falling edge of the R D0 pin input is detected.
Page 261 CHAPTER 13 SERIAL INTERFACE UART0 (e) Reception error Three types of errors may occur during reception: a parity error, framing error, or overrun error. If the error flag of asynchronous serial interface reception error status register 0 (ASIS0) is set as a result of data reception, a reception error interrupt request (INTSR0) is generated.
Page 262: Dedicated Baud Rate Generator
CHAPTER 13 SERIAL INTERFACE UART0 13.4.3 Dedicated baud rate generator The dedicated baud rate generator consists of a source clock selector and a 5-bit programmable counter, and generates a serial clock for transmission/reception of UART0. Separate 5-bit counters are provided for transmission and reception. (1) Configuration of baud rate generator •...
Page 263 CHAPTER 13 SERIAL INTERFACE UART0 (2) Generation of serial clock A serial clock can be generated by using baud rate generator control register 0 (BRGC0). Select the clock to be input to the 5-bit counter by using bits 7 and 6 (TPS01 and TPS00) of BRGC0. Bits 4 to 0 (MDL04 to MDL00) of BRGC0 can be used to select the division value of the 5-bit counter.
Page 264 CHAPTER 13 SERIAL INTERFACE UART0 (b) Baud rate The baud rate can be calculated by the following expression. XCLK • Baud rate = [bps] 2 × k : Frequency of base clock (Clock) selected by the TPS01 and TPS00 bits of the BRGC0 register XCLK Value set by the MDL04 to MDL00 bits of the BRGC0 register (k = 8, 9, 10, ..., 31) (c) Error of baud rate...
Page 265 CHAPTER 13 SERIAL INTERFACE UART0 (3) Example of setting baud rate Table 13-3. Set Data of Baud Rate Generator Baud Rate = 10.0 MHz = 8.38 MHz = 4.19 MHz [bps] TPS01, Calculated ERR[%] TPS01, Calculated ERR[%] TPS01, Calculated ERR[%] TPS00 Value TPS00...
Page 266 CHAPTER 13 SERIAL INTERFACE UART0 (4) Permissible baud rate range during reception The permissible error from the baud rate at the transmission destination during reception is shown below. Caution Make sure that the baud rate error during reception is within the permissible error range, by using the calculation expression shown below.
Page 267 CHAPTER 13 SERIAL INTERFACE UART0 k − 2 21k + 2 Minimum permissible transfer rate: FLmin = 11 × FL − × FL = Therefore, the maximum receivable baud rate at the transmission destination is as follows. − BRmax = (FLmin/11) Brate 21k + 2 Similarly, the maximum permissible transfer rate can be calculated as follows.
Page 268: Chapter 14 Serial Interface Uart6
CHAPTER 14 SERIAL INTERFACE UART6 14.1 Functions of Serial Interface UART6 Serial interface UART6 has the following two modes. (1) Operation stop mode This mode is used when serial transfer is not executed and can enable a reduction in the power consumption. For details, refer to 14.4.1 Operation stop mode.
Page 269 CHAPTER 14 SERIAL INTERFACE UART6 Remark LIN stands for Local Interconnect Network and is a low-speed (1 to 20 kbps) serial communication protocol intended to aid the cost reduction of an automotive network. LIN communication is single-master communication, and up to 15 slaves can be connected to one master.
Page 270 CHAPTER 14 SERIAL INTERFACE UART6 Figure 14-2. LIN Reception Operation Checksum Wakeup Tuning Data field field signal frame break field Tuning field Match field Data field Sleep Data Data Data ID reception Note 5 Note 2 reception reception reception reception 13 bits reception Disable...
Page 271 CHAPTER 14 SERIAL INTERFACE UART6 Figure 14-3. Port Configuration for LIN Reception Operation P14/R RXD6 input Port mode (PM14) Port latch (P14) P120/INTP0 INTP0 input Port mode Port input (PM120) switch control (ISC0) Port latch <ISC0> (P120) 0: A output 1: B output P00/TI000 TI000 input...
Page 272: Configuration Of Serial Interface Uart6
CHAPTER 14 SERIAL INTERFACE UART6 14.2 Configuration of Serial Interface UART6 Serial interface UART6 consists of the following hardware. Table 14-1. Configuration of Serial Interface UART6 Item Configuration Registers Receive buffer register 6 (RXB6) Receive shift register 6 (RXS6) Transmit buffer register 6 (TXB6) Transmit shift register 6 (TXS6) Control registers Asynchronous serial interface operation mode register 6 (ASIM6)
Page 273 Figure 14-4. Block Diagram of Serial Interface UART6 Filter D6/P14 INTSR6 Reception control INTSRE6 Receive shift register 6 (RXS6) Asynchronous serial Asynchronous serial Asynchronous serial interface Baud rate Receive buffer register 6 interface reception error interface operation mode control register 6 (ASICL6) generator (RXB6) status register 6 (ASIS6)
Page 274 CHAPTER 14 SERIAL INTERFACE UART6 (1) Receive buffer register 6 (RXB6) This 8-bit register stores parallel data converted by the receive shift register. Each time 1 byte of data has been received, new receive data is transferred to this register from receive shift register 6 (RXS6).
Page 275: Registers Controlling Serial Interface Uart6
CHAPTER 14 SERIAL INTERFACE UART6 14.3 Registers Controlling Serial Interface UART6 Serial interface UART6 is controlled by the following six registers. • Asynchronous serial interface operation mode register 6 (ASIM6) • Asynchronous serial interface reception error status register 6 (ASIS6) •...
Page 276 CHAPTER 14 SERIAL INTERFACE UART6 Figure 14-5. Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) (2/2) RXE6 Enables/disables reception Disables reception (synchronously resets the reception circuit). Enables reception PS61 PS60 Transmission operation Reception operation Does not output parity bit. Reception without parity Note Outputs 0 parity.
Page 277 CHAPTER 14 SERIAL INTERFACE UART6 (2) Asynchronous serial interface reception error status register 6 (ASIS6) This register indicates an error status on completion of reception by serial interface UART6. It includes three error flag bits (PE6, FE6, OVE6). This register can be set by an 8-bit memory manipulation instruction and is read-only. RESET input clears this register to 00H if bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 0.
Page 278 CHAPTER 14 SERIAL INTERFACE UART6 (3) Asynchronous serial interface transmission status register 6 (ASIF6) This register indicates the status of transmission by serial interface UART6. It includes two status flag bits (TXBF6 and TXSF6). Transmission can be continued without disruption even during an interrupt period, by writing the next data to the TXB6 register after data has been transferred from the TXB6 register to the TXS6 register.
Page 279 CHAPTER 14 SERIAL INTERFACE UART6 (4) Clock selection register 6 (CKSR6) This register selects the base clock of serial interface UART6. CKSR6 can be set by an 8-bit memory manipulation instruction. RESET input clears this register to 00H. Remark CKSR6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1).
Page 280 CHAPTER 14 SERIAL INTERFACE UART6 (5) Baud rate generator control register 6 (BRGC6) This register selects the base clock of serial interface UART6. BRGC6 can be set by an 8-bit memory manipulation instruction. RESET input sets this register to FFH. Remark BRGC6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1).
Page 281 CHAPTER 14 SERIAL INTERFACE UART6 (6) Asynchronous serial interface control register 6 (ASICL6) This register controls the serial transfer operations of serial interface UART6. ASICL6 can be set by a 1-bit transfer instruction or an 8-bit memory manipulation instruction. RESET input sets this register to 16H. Remark ASICL6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1).
Page 282 CHAPTER 14 SERIAL INTERFACE UART6 Figure 14-10. Format of Asynchronous Serial Interface Control Register 6 (ASICL6) (2/2) SBL62 SBL61 SBL60 SBF transmission output width control SBF is output with 13-bit length. SBF is output with 14-bit length. SBF is output with 15-bit length. SBF is output with 16-bit length.
Page 283: Operation Of Serial Interface Uart6
CHAPTER 14 SERIAL INTERFACE UART6 14.4 Operation of Serial Interface UART6 This section explains the two modes of serial interface UART6. 14.4.1 Operation stop mode In this mode, serial transfer cannot be executed; therefore, the power consumption can be reduced. In addition, the pins can be used as ordinary port pins in this mode.
Page 284: Asynchronous Serial Interface (Uart) Mode
CHAPTER 14 SERIAL INTERFACE UART6 14.4.2 Asynchronous serial interface (UART) mode In this mode, data of 1 byte is transmitted/received following a start bit, and a full-duplex operation can be performed. A dedicated UART baud rate generator is incorporated, so that communication can be executed at a wide range of baud rates.
Page 285 CHAPTER 14 SERIAL INTERFACE UART6 RXE6 Enables/disables reception Disables reception (synchronously resets the reception circuit). Enables reception PS61 PS60 Transmission operation Reception operation Does not output parity bit. Reception without parity Note Outputs 0 parity. Reception as 0 parity Outputs odd parity. Judges as odd parity.
Page 286 CHAPTER 14 SERIAL INTERFACE UART6 (b) Asynchronous serial interface reception error status register 6 (ASIS6) This register indicates an error status on completion of reception by serial interface UART6. It includes three error flag bits (PE6, FE6, OVE6). This register can be set by an 8-bit memory manipulation instruction and is read-only. RESET input clears this register to 00H if bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 0.
Page 287 CHAPTER 14 SERIAL INTERFACE UART6 (c) Asynchronous serial interface transmission status register 6 (ASIF6) This register indicates the status of transmission by serial interface UART6. It includes two status flag bits (TXBF6 and TXSF6). Transmission can be continued without disruption even during an interrupt period, by writing the next data to the TXB6 register after data has been transferred from the TXB6 register to the TXS6 register.
Page 288 CHAPTER 14 SERIAL INTERFACE UART6 (d) Asynchronous serial interface control register 6 (ASICL6) This register controls the serial transfer operations of serial interface UART6. ASICL6 can be set by a 1-bit transfer instruction or an 8-bit memory manipulation instruction. RESET input sets this register to 16H. Remark ASICL6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1).
Page 289 CHAPTER 14 SERIAL INTERFACE UART6 SBL62 SBL61 SBL60 SBF transmission output width control SBF is output with 13-bit length. SBF is output with 14-bit length. SBF is output with 15-bit length. SBF is output with 16-bit length. SBF is output with 17-bit length. SBF is output with 18-bit length.
Page 290 CHAPTER 14 SERIAL INTERFACE UART6 (2) Communication operation (a) Normal transmit/receive data format Figure 14-11 shows the format of the transmit/receive data. Figure 14-11. Format of Normal UART Transmit/Receive Data 1. LSB-first transmission/reception 1 data frame Start Parity Stop bit Character bits 2.
Page 291 CHAPTER 14 SERIAL INTERFACE UART6 Figure 14-12. Example of Normal UART Transmit/Receive Data Format 1. Data length: 8 bits, LSB first, Parity: Even parity, Stop bit: 1 bit, Transfer data: 55H 1 data frame Start Parity Stop 2. Data length: 8 bits, MSB first, Parity: Even parity, Stop bit: 1 bit, Transfer data: 55H 1 data frame Start Parity...
Page 292 CHAPTER 14 SERIAL INTERFACE UART6 (b) Parity types and operation The parity bit is used to detect a bit error in communication data. Usually, the same type of parity bit is used on both the transmission and reception sides. With even parity and odd parity, a 1-bit (odd number) error can be detected.
Page 293 CHAPTER 14 SERIAL INTERFACE UART6 (c) Normal transmission The T D6 pin outputs a high level when bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is set to 1. If bit 6 (TXE6) of ASIM6 is then set to 1, transmission is enabled. Transmission can be started by writing transmit data to transmit buffer register 6 (TXB6).
Page 294 CHAPTER 14 SERIAL INTERFACE UART6 (d) Continuous transmission When transmit shift register 6 (TXS6) has started the shift operation, the next transmit data can be written to transmit buffer register 6 (TXB6). As a result, data can be transmitted without intermission even while an interrupt that has occurred after transmission of one data frame is being serviced, thus realizing an efficient communication rate.
Page 295 CHAPTER 14 SERIAL INTERFACE UART6 Figure 14-14 shows the processing flow of continuous transmission. Figure 14-14. Processing Flow of Continuous Transmission Set registers. Write transmit data to TXB6 register. Read ASIF6 register. TXBF6 = 0? Interrupt occurs. Transfer executed necessary number of times? Read ASIF6 Read ASIF6...
Page 296 CHAPTER 14 SERIAL INTERFACE UART6 Figure 14-15 shows the timing of starting continuous transmission, and Figure 14-16 shows the timing of ending continuous transmission. Figure 14-15. Timing of Starting Continuous Transmission Start Data (1) Parity Stop Start Data (2) Parity Stop Start INTST6...
Page 297 CHAPTER 14 SERIAL INTERFACE UART6 Figure 14-16. Timing of Ending Continuous Transmission Start Start Data (n) Parity Parity Stop Stop Data (n–1) Stop INTST6 TXB6 Data (n–1) Data (n) TXS6 Data (n–1) Data (n) TXBF6 TXSF6 POWER6 or TXE6 Remark T D6 pin (output) INTST6: Interrupt request signal...
Page 298 CHAPTER 14 SERIAL INTERFACE UART6 (e) Normal reception Reception is enabled and the R D6 pin input is sampled when bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is set to 1 and then bit 5 (RXE6) of ASIM6 is set to 1. The 8-bit counter of the baud rate generator starts counting when the falling edge of the R D6 pin input is detected.
Page 299 CHAPTER 14 SERIAL INTERFACE UART6 (f) Reception error Three types of errors may occur during reception: a parity error, framing error, or overrun error. If the error flag of asynchronous serial interface reception error status register 6 (ASIS6) is set as a result of data reception, a reception error interrupt request (INTSR6/INTSRE6) is generated.
Page 300 CHAPTER 14 SERIAL INTERFACE UART6 (g) Noise filter of receive data The RXD6 signal is sampled with the base clock output by the prescaler block. If two sampled values are the same, the output of the match detector changes, and the data is sampled as input data.
Page 301 CHAPTER 14 SERIAL INTERFACE UART6 SBF reception When the device is incorporated in LIN, the SBF (Synchronous Break Field) reception control function is used for reception. For the reception operation of LIN, refer to Figure 14-2 LIN Reception Operation. Reception is enabled when bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is set to 1 and then bit 5 (RXE6) of ASIM6 is set to 1.
Page 302: Dedicated Baud Rate Generator
CHAPTER 14 SERIAL INTERFACE UART6 14.4.3 Dedicated baud rate generator The dedicated baud rate generator consists of a source clock selector and an 8-bit programmable counter, and generates a serial clock for transmission/reception of UART6. Separate 8-bit counters are provided for transmission and reception. (1) Configuration of baud rate generator •...
Page 303 CHAPTER 14 SERIAL INTERFACE UART6 Figure 14-22. Configuration of Baud Rate Generator POWER6 POWER6, TXE6 (or RXE6) Clock Selector 8-bit counter XCLK Match detector Baud rate TO50/TI50/P17 (TM50 output) CKSR6: TPS63 to TPS60 BRGC6: MDL67 to MDL60 Remark POWER6: Bit 7 of asynchronous serial interface operation mode register 6 (ASIM6) TXE6: Bit 6 of ASIM6 RXE6:...
Page 304 CHAPTER 14 SERIAL INTERFACE UART6 (2) Generation of serial clock A serial clock can be generated by using clock selection register 6 (CKSR6) and baud rate generator control register 6 (BRGC6). Select the clock to be input to the 8-bit counter by using bits 3 to 0 (TPS63 to TPS60) of CKSR6. Bits 7 to 0 (MDL67 to MDL60) of BRGC6 can be used to select the division value of the 8-bit counter.
Page 305 CHAPTER 14 SERIAL INTERFACE UART6 (b) Baud rate generator control register 6 (BRGC6) This register selects the base clock of serial interface UART6. BRGC6 can be set by an 8-bit memory manipulation instruction. RESET input sets this register to FFH. Remark BRGC6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1).
Page 306 CHAPTER 14 SERIAL INTERFACE UART6 (c) Baud rate The baud rate can be calculated by the following expression. XCLK • Baud rate = [bps] 2 × k : Frequency of base clock (Clock) selected by TPS63 to TPS60 bits of CKSR6 register XCLK Value set by MDL67 to MDL60 bits of BRGC6 register (k = 8, 9, 10, ..., 255) (d) Error of baud rate...
Page 307 CHAPTER 14 SERIAL INTERFACE UART6 (3) Example of setting baud rate Table 14-4. Set Data of Baud Rate Generator Baud Rate = 10.0 MHz = 8.38 MHz = 4.19 MHz [bps] TPS63 to Calculated ERR[%] TPS63 to Calculated ERR[%] TPS63 to Calculated ERR[%] TPS60...
Page 308 CHAPTER 14 SERIAL INTERFACE UART6 (4) Permissible baud rate range during reception The permissible error from the baud rate at the transmission destination during reception is shown below. Caution Make sure that the baud rate error during reception is within the permissible error range, by using the calculation expression shown below.
Page 309 CHAPTER 14 SERIAL INTERFACE UART6 Therefore, the maximum receivable baud rate at the transmission destination is as follows. − BRmax = (FLmin/11) Brate 21k + 2 Similarly, the maximum permissible transfer rate can be calculated as follows. 21k − 2 k + 2 ×...
Page 310 CHAPTER 14 SERIAL INTERFACE UART6 (5) Transfer rate during continuous transmission When data is continuously transmitted, the transfer rate from a stop bit to the next start bit is extended by two clocks from the normal value. However, the result of transfer is not affected because the timing is initialized on the reception side when the start bit is detected.
Page 311: Chapter 15 Serial Interface Csi10
CHAPTER 15 SERIAL INTERFACE CSI10 15.1 Functions of Serial Interface CSI10 Serial interface CSI10 has the following two modes. • Operation stop mode • 3-wire serial I/O mode (1) Operation stop mode This mode is used when serial transfer is not performed and can enable a reduction in the power consumption. (2) 3-wire serial I/O mode (MSB/LSB-first selectable) This mode is used to transfer 8-bit data using three lines: a serial clock line (SCK10) and two serial data lines (SI10 and SO10).
Page 312 CHAPTER 15 SERIAL INTERFACE CSI10 Figure 15-1. Block Diagram of Serial Interface CSI10 Internal bus Serial I/O shift Transmit buffer Output SI10/P11/R SO10/P12 register 10 (SIO10) register 10 (SOTB10) selector Transmit data Output latch controller Transmit controller /2 to f Clock start/stop controller &...
Page 313: Registers Controlling Serial Interface Csi10
CHAPTER 15 SERIAL INTERFACE CSI10 15.3 Registers Controlling Serial Interface CSI10 Serial interface CSI10 is controlled by the following two registers. • Serial operation mode register 10 (CSIM10) • Serial clock selection register 10 (CSIC10) (1) Serial operation mode register 10 (CSIM10) CSIM10 is used to select the operation mode and enable or disable operation.
Page 314 CHAPTER 15 SERIAL INTERFACE CSI10 (2) Serial clock selection register 10 (CSIC10) CSIC10 is used to select the phase of the data clock and set the count clock. CSIC10 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H.
Page 315: Operation Of Serial Interface Csi10
CHAPTER 15 SERIAL INTERFACE CSI10 15.4 Operation of Serial Interface CSI10 Serial interface CSI10 can be used in the following two modes. • Operation stop mode • 3-wire serial I/O mode 15.4.1 Operation stop mode Serial transfer is not executed in this mode. Therefore, the power consumption can be reduced. In addition, the P10/SCK10/T D0, P11/SI10/R D0, and P12/SO10 pins can be used as ordinary I/O port pins in this mode.
Page 316: 3-Wire Serial I/O Mode
CHAPTER 15 SERIAL INTERFACE CSI10 15.4.2 3-wire serial I/O mode The 3-wire serial I/O mode is useful for connecting peripheral ICs and display controllers that have a clocked serial interface. In this mode, communication is executed by using three lines: the serial clock (SCK10), serial output (SO10), and serial input (SI10) lines.
Page 317 CHAPTER 15 SERIAL INTERFACE CSI10 (b) Serial clock selection register 10 (CSIC10) CSIC10 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Address: FF81H After reset: 00H R/W Symbol CSIC10 CKP10 DAP10 CKS102 CKS101...
Page 318 CHAPTER 15 SERIAL INTERFACE CSI10 (2) Setting of ports <1> Transmit/receive mode (a) To use externally input clock as system clock (SCK10) Bit 1 (PM11) of port mode register 1: Set to 1 Bit 2 (PM12) of port mode register 1: Cleared to 0 Bit 0 (PM10) of port mode register 1: Set to 1 Bit 2 (P12) of port 1: Cleared to 0 (b) To use internal clock as system clock (SCK10)
Page 319 CHAPTER 15 SERIAL INTERFACE CSI10 (3) Communication operation In the 3-wire serial I/O mode, data is transmitted or received in 8-bit units. Each bit of the data is transmitted or received in synchronization with the serial clock. Data can be transmitted or received if bit 6 (TRMD10) of serial operation mode register 10 (CSIM10) is 1. Transmission/reception is started when a value is written to transmit buffer register 10 (SOTB10).
Page 320 CHAPTER 15 SERIAL INTERFACE CSI10 Figure 15-4. Timing in 3-Wire Serial I/O Mode (2/2) (2) Transmission/reception timing (Type 2; TRMD10 = 1, DIR10 = 0, CKP10 = 0, DAP10 = 1) SCK10 Read/write trigger SOTB10 55H (communication data) SIO10 CSOT10 INTCSI10 CSIIF10 SI10 (input AAH)
Page 321 CHAPTER 15 SERIAL INTERFACE CSI10 Figure 15-5. Timing of Clock/Data Phase (a) Type 1; CKP10 = 0, DAP10 = 0 SCK10 SI10 capture SO10 Writing to SOTB10 or reading from SIO10 CSIIF10 CSOT10 (b) Type 2; CKP10 = 0, DAP10 = 1 SCK10 SI10 capture SO10...
Page 322 CHAPTER 15 SERIAL INTERFACE CSI10 (4) Timing of output to SO10 pin (first bit) When communication is started, the value of transmit buffer register 10 (SOTB10) is output from the SO10 pin. The output operation of the first bit at this time is described below. Figure 15-6.
Page 323 CHAPTER 15 SERIAL INTERFACE CSI10 (5) Output value of SO10 pin (last bit) After communication has been completed, the SO10 pin holds the output value of the last bit. Figure 15-7. Output Value of SO10 Pin (Last Bit) (1) Type 1; when CKP10 = 0 and DAP10 = 0 (or CKP10 = 1, DAP10 = 0) SCK10 ( ←...
Page 324: Chapter 16 Interrupt Functions
CHAPTER 16 INTERRUPT FUNCTIONS 16.1 Interrupt Function Types The following two types of interrupt functions are used. (1) Maskable interrupts These interrupts undergo mask control. Maskable interrupts can be divided into a high interrupt priority group and a low interrupt priority group by setting the priority specification flag registers (PR0L, PR0H, PR1L). Multiple interrupt servicing can be applied to low-priority interrupts when high-priority interrupts are generated.
Page 325 CHAPTER 16 INTERRUPT FUNCTIONS Table 16-1. Interrupt Source List Interrupt Default Interrupt Source Internal/ Vector Basic Note 1 Type Priority External Table Configuration Name Trigger Note 2 Address Type Maskable INTLVI Low-voltage detection Internal 0004H INTP0 Pin input edge detection External 0006H INTP1...
Page 326 CHAPTER 16 INTERRUPT FUNCTIONS Figure 16-1. Basic Configuration of Interrupt Function (1/2) (A) Internal maskable interrupt Internal bus Vector table Priority controller Interrupt address generator request Standby release signal (B) External maskable interrupt (INTP0 to INTP6) Internal bus External interrupt edge enable register (EGP, EGN) Vector table...
Page 327: Registers Controlling Interrupt Functions
CHAPTER 16 INTERRUPT FUNCTIONS Figure 16-1. Basic Configuration of Interrupt Function (2/2) (C) External maskable interrupt (INTKR) Internal bus Interrupt Vector table Priority controller request interrupt address generator detector 1 when KRMn = 1 (n = 0 to 7) Standby release signal (D) Software interrupt Internal bus Interrupt...
Page 328 CHAPTER 16 INTERRUPT FUNCTIONS Table 16-2. Flags Corresponding to Interrupt Request Sources Interrupt Source Interrupt Request Flag Interrupt Mask Flag Priority Specification Flag Register Register Register INTLVI LVIIF IF0L LVIMK MK0L LVIPR PR0L INTP0 PIF0 PMK0 PPR0 INTP1 PIF1 PMK1 PPR1 INTP2 PIF2...
Page 329 CHAPTER 16 INTERRUPT FUNCTIONS (1) Interrupt request flag registers (IF0L, IF0H, IF1L) The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon RESET input.
Page 330 CHAPTER 16 INTERRUPT FUNCTIONS (2) Interrupt mask flag registers (MK0L, MK0H, MK1L) The interrupt mask flags are used to enable/disable the corresponding maskable interrupt servicing. MK0L, MK0H, and MK1L are set by a 1-bit or 8-bit memory manipulation instruction. When MK0L and MK0H are combined to form 16-bit register MK0, they are set by a 16-bit memory manipulation instruction.
Page 331 CHAPTER 16 INTERRUPT FUNCTIONS (3) Priority specification flag registers (PR0L, PR0H, PR1L) The priority specification flag registers are used to set the corresponding maskable interrupt priority order. PR0L, PR0H, and PR1L are set by a 1-bit or 8-bit memory manipulation instruction. If PR0L and PR0H are combined to form 16-bit register PR0, they are set by a 16-bit memory manipulation instruction.
Page 332 CHAPTER 16 INTERRUPT FUNCTIONS (4) External interrupt rising edge enable register (EGP), external interrupt falling edge enable register (EGN) These registers specify the valid edge for INTP0 to INTP6. EGP and EGN are set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears these registers to 00H.
Page 333 CHAPTER 16 INTERRUPT FUNCTIONS (5) Program status word (PSW) The program status word is a register used to hold the instruction execution result and the current status for an interrupt request. The IE flag that sets maskable interrupt enable/disable and the ISP flag that controls multiple interrupt servicing are mapped to the PSW.
Page 334: Interrupt Servicing Operations
CHAPTER 16 INTERRUPT FUNCTIONS 16.4 Interrupt Servicing Operations 16.4.1 Maskable interrupt request acknowledgement A maskable interrupt request becomes acknowledgeable when the interrupt request flag is set to 1 and the mask (MK) flag corresponding to that interrupt request is cleared to 0. A vectored interrupt request is acknowledged if interrupts are in the interrupt enabled state (when the IE flag is set to 1).
Page 335 CHAPTER 16 INTERRUPT FUNCTIONS Figure 16-7. Interrupt Request Acknowledgement Processing Algorithm Start ××IF = 1? Yes (interrupt request generation) ××MK = 0? Interrupt request held pending Yes (High priority) ××PR = 0? No (Low priority) Any high-priority Any high-priority interrupt request among those interrupt request among simultaneously generated with ××PR = 0?
Page 336: Software Interrupt Request Acknowledgement
CHAPTER 16 INTERRUPT FUNCTIONS Figure 16-8. Interrupt Request Acknowledgement Timing (Minimum Time) 6 clocks PSW and PC saved, Interrupt servicing CPU processing Instruction Instruction jump to interrupt program servicing ××IF (××PR = 1) 8 clocks ××IF (××PR = 0) 7 clocks Remark 1 clock: 1/f : CPU clock) Figure 16-9.
Page 337: Multiple Interrupt Servicing
CHAPTER 16 INTERRUPT FUNCTIONS 16.4.3 Multiple interrupt servicing Multiple interrupt servicing occurs when another interrupt request is acknowledged during execution of an interrupt. Multiple interrupt servicing does not occur unless the interrupt request acknowledgement enabled state is selected (IE = 1). Also, when an interrupt request is acknowledged, interrupt request acknowledgement becomes disabled (IE = 0).
Page 338 CHAPTER 16 INTERRUPT FUNCTIONS Figure 16-10. Examples of Multiple Interrupt Servicing (1/2) Example 1. Multiple interrupt servicing occurs twice Main processing INTxx servicing INTyy servicing INTzz servicing IE = 0 IE = 0 IE = 0 INTxx INTyy INTzz (PR = 1) (PR = 0) (PR = 0) RETI...
Page 339 CHAPTER 16 INTERRUPT FUNCTIONS Figure 16-10. Examples of Multiple Interrupt Servicing (2/2) Example 3. Multiple interrupt servicing does not occur because interrupts are not enabled Main processing INTxx servicing INTyy servicing IE = 0 INTyy (PR = 0) INTxx (PR = 0) RETI IE = 1 IE = 0...
Page 340: Interrupt Request Hold
CHAPTER 16 INTERRUPT FUNCTIONS 16.4.4 Interrupt request hold There are instructions where, even if an interrupt request is issued for them while another instruction is being executed, request acknowledgement is held pending until the end of execution of the next instruction. These instructions (interrupt request hold instructions) are listed below.
Page 341: Chapter 17 Key Interrupt Function
CHAPTER 17 KEY INTERRUPT FUNCTION 17.1 Functions of Key Interrupt A key interrupt (INTKR) can be generated by setting the key return mode register (KRM) and inputting a falling edge to the key interrupt input pins (KR0 to KR7). Table 17-1. Assignment of Key Interrupt Detection Pins Flag Description KRM0...
Page 342: Register Controlling Key Interrupt
CHAPTER 17 KEY INTERRUPT FUNCTION 17.3 Register Controlling Key Interrupt (1) Key return mode register (KRM) This register controls the KRM0 to KRM7 bits using the KR0 to KR7 signals, respectively. This register is set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H.
Page 343: Chapter 18 Standby Function
CHAPTER 18 STANDBY FUNCTION 18.1 Standby Function and Configuration 18.1.1 Standby function Table 18-1. Relationship Between HALT Mode, STOP Mode, and Clock X1 Input Clock Ring-OSC Clock Subsystem Clock CPU Clock HALT mode Oscillation continues Oscillation continues Oscillation continues Operation stopped STOP mode Oscillation stopped Oscillation continues...
Page 344 CHAPTER 18 STANDBY FUNCTION Figure 18-1. Operation Timing When STOP Mode Is Released STOP mode release STOP mode X1 input clock Ring-OSC clock X1 input clock is selected as CPU clock HALT status X1 input clock when STOP instruction (oscillation stabilization time set by OSTS) is executed Ring-OSC clock is Ring-OSC clock...
Page 345: Registers Controlling Standby Function
CHAPTER 18 STANDBY FUNCTION 18.1.2 Registers controlling standby function The standby function is controlled by the following two registers. • Oscillation stabilization time counter status register (OSTC) • Oscillation stabilization time select register (OSTS) (1) Oscillation stabilization time counter status register (OSTC) This is the status register of the X1 input clock oscillation stabilization time counter.
Page 346 CHAPTER 18 STANDBY FUNCTION (2) Oscillation stabilization time select register (OSTS) This register is used to select the X1 oscillation stabilization wait time when STOP mode is released. The wait time set by OSTS is valid only after STOP mode is released when the X1 input clock is selected as the CPU clock.
Page 347: Standby Function Operation
CHAPTER 18 STANDBY FUNCTION 18.2 Standby Function Operation 18.2.1 HALT mode (1) HALT mode The HALT mode is set by executing the HALT instruction. HALT mode can be set regardless of whether the CPU clock before the setting was the X1 input clock, Ring-OSC clock, or subsystem clock. The operating statuses in the HALT mode are shown below.
Page 348 CHAPTER 18 STANDBY FUNCTION Table 18-2. Operating Statuses in HALT Mode (2/2) HALT Mode Setting When HALT Instruction Is Executed While CPU Is Operating on Subsystem Clock When X1 Input Clock Oscillation Continues When X1 Input Clock Oscillation Stopped When Ring-OSC When Ring-OSC When Ring-OSC When Ring-OSC...
Page 349 CHAPTER 18 STANDBY FUNCTION (2) HALT mode release The HALT mode can be released by the following two sources. (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the HALT mode is released. If interrupt acknowledgement is enabled, vectored interrupt servicing is carried out. If interrupt acknowledgement is disabled, the next address instruction is executed.
Page 350 CHAPTER 18 STANDBY FUNCTION (b) Release by RESET input When the RESET signal is input, HALT mode is released, and then, as in the case with a normal reset operation, the program is executed after branching to the reset vector address. Figure 18-5.
Page 351: Stop Mode
CHAPTER 18 STANDBY FUNCTION 18.2.2 STOP mode (1) STOP mode setting and operating statuses The STOP mode is set by executing the STOP instruction, and it can be set only when the CPU clock before the setting was the X1 input clock or Ring-OSC clock. Caution Because the interrupt request signal is used to clear the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is immediately cleared if set.
Page 352 CHAPTER 18 STANDBY FUNCTION (2) STOP mode release The STOP mode can be released by the following two sources. (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the STOP mode is released. After the oscillation stabilization time has elapsed, if interrupt acknowledgement is enabled, vectored interrupt servicing is carried out.
Page 353 CHAPTER 18 STANDBY FUNCTION (b) Release by RESET input When the RESET signal is input, STOP mode is released and a reset operation is performed after the oscillation stabilization time has elapsed. Figure 18-7. STOP Mode Release by RESET Input (1) When X1 input clock is used as CPU clock STOP instruction...
Page 354: Chapter 19 Reset Function
CHAPTER 19 RESET FUNCTION The following five operations are available to generate a reset signal. (1) External reset input via RESET pin (2) Internal reset by watchdog timer program loop detection (3) Internal reset by clock monitor X1 clock oscillation stop detection (4) Internal reset by comparison of supply voltage and detection voltage of power-on-clear (POC) circuit (5) Internal reset by comparison of supply voltage and detection voltage of low-power-supply detector (LVI) External and internal resets have no functional differences.
Page 355 CHAPTER 19 RESET FUNCTION Figure 19-1. Block Diagram of Reset Function Internal bus Reset control flag register (RESF) WDTRF CLMRF LVIRF WDTRES (Watchdog timer reset signal) Clear Clear Clear CLMRESB (Clock monitor reset signal) Reset signal RESET Reset signal to LVIM/LVIS register POCRESB (Power-on-clear circuit reset signal) Reset signal...
Page 356 CHAPTER 19 RESET FUNCTION Figure 19-2. Timing of Reset by RESET Input Operation Normal operation Reset period stop CPU clock Normal operation (Reset processing, Ring-OSC clock) (Oscillation stop) (17/f RESET Internal reset signal Delay Delay Note Hi-Z Port pin Figure 19-3. Timing of Reset Due to Watchdog Timer Overflow Operation Reset period Normal operation...
Page 357 CHAPTER 19 RESET FUNCTION Table 19-1. Hardware Statuses After Reset (1/2) Hardware Status After Reset Note 1 Program counter (PC) The contents of the reset vector table (0000H, 0001H) are set. Stack pointer (SP) Undefined Program status word (PSW) Note 2 Data memory Undefined Note 2...
Page 358 CHAPTER 19 RESET FUNCTION Table 19-1. Hardware Statuses After Reset (2/2) Hardware Status After Reset Watchdog timer Mode register (WDTM) Enable register (WDTE) A/D converter Conversion result register (ADCR) Undefined Mode register (ADM) Analog input channel specification register (ADS) Power-fail comparison mode register (PFM) Power-fail comparison threshold register (PFT) Serial interface UART0 Receive buffer register 0 (RXB0)
Page 359: Register For Confirming Reset Source
CHAPTER 19 RESET FUNCTION 19.1 Register for Confirming Reset Source Many internal reset generation sources exist in the 78K0/KD1 Series. The reset control flag register (RESF) is used to store which source has generated the reset request. RESF can be read by an 8-bit memory manipulation instruction.
Page 360: Chapter 20 Clock Monitor
CHAPTER 20 CLOCK MONITOR 20.1 Functions of Clock Monitor The clock monitor samples the X1 input clock using the on-chip Ring-OSC, and generates an internal reset signal when the X1 input clock is stopped. When a reset signal is generated by the clock monitor, bit 1 (CLMRF) of the reset control flag register (RESF) is set to 1.
Page 361: Register Controlling Clock Monitor
CHAPTER 20 CLOCK MONITOR 20.3 Register Controlling Clock Monitor Clock monitor is controlled by the clock monitor mode register (CLM). (1) Clock monitor mode register (CLM) This register sets the operation mode of the clock monitor. This register can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H.
Page 362: Operation Of Clock Monitor
CHAPTER 20 CLOCK MONITOR 20.4 Operation of Clock Monitor This section explains the functions of the clock monitor. The start and stop conditions are as follows. <Start condition> When bit 0 (CLME) of the clock monitor mode register (CLM) is set to operation enabled (1). <Stop condition>...
Page 363 CHAPTER 20 CLOCK MONITOR Figure 20-3. Timing of Clock Monitor (1/3) (1) When internal reset is executed by oscillation stop of X1 input clock 4 clocks of Ring-OSC clock X1 input clock Ring-OSC clock Internal reset signal CLME Note CLMRF Note CLMRF is read by software and then automatically cleared to 0.
Page 364 CHAPTER 20 CLOCK MONITOR Figure 20-3. Timing of Clock Monitor (2/3) (3) Clock monitor status after STOP mode is released (CLME = 1 is set when CPU clock operates on Ring-OSC clock and before entering STOP mode) Clock supply Normal stopped Normal operation (Ring-OSC clock) operation...
Page 365 CHAPTER 20 CLOCK MONITOR Figure 20-3. Timing of Clock Monitor (3/3) (5) Clock monitor status after RESET input (CLME = 1 is set after RESET input and at the end of X1 input clock oscillation stabilization time) Normal Clock supply operation CPU operation Reset...
Page 366: Chapter 21 Power-On-Clear Circuit
CHAPTER 21 POWER-ON-CLEAR CIRCUIT 21.1 Functions of Power-on-Clear Circuit The power-on-clear circuit (POC) has the following functions. • Generates internal reset signal at power on. • Compares supply voltage (V ) and detection voltage (V ), and generates internal reset signal when V <...
Page 367: Configuration Of Power-On-Clear Circuit
CHAPTER 21 POWER-ON-CLEAR CIRCUIT 21.2 Configuration of Power-on-Clear Circuit The block diagram of the power-on-clear circuit is shown in Figure 21-1. Figure 21-1. Block Diagram of Power-on-Clear Circuit Internal reset signal – Detection voltage source 21.3 Operation of Power-on-Clear Circuit In the power-on-clear circuit, the supply voltage (V ) and detection voltage (V ) are compared, and when V...
Page 368: Cautions For Power-On-Clear Circuit
CHAPTER 21 POWER-ON-CLEAR CIRCUIT 21.4 Cautions for Power-on-Clear Circuit In a system where the supply voltage (V ) fluctuates for a certain period in the vicinity of the POC detection voltage (V ), the system may be repeatedly reset and released from the reset status. In this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action.
Page 369 CHAPTER 21 POWER-ON-CLEAR CIRCUIT Figure 21-3. Example of Software Processing After Release of Reset (2/2) • Checking reset cause Check reset cause WDTRF of RESF register = 1? Reset processing by watchdog timer CLMRF of RESF register = 1? Reset processing by clock monitor LVIRF of RESF register = 1?
Page 370: Chapter 22 Low-Voltage Detector
CHAPTER 22 LOW-VOLTAGE DETECTOR 22.1 Functions of Low-Voltage Detector The low-voltage detector (LVI) has following functions. • Compares supply voltage (V ) and detection voltage (V ), and generates an internal interrupt signal or internal reset signal when V < V •...
Page 371: Registers Controlling Low-Voltage Detector
CHAPTER 22 LOW-VOLTAGE DETECTOR 22.3 Registers Controlling Low-Voltage Detector The low-voltage detector is controlled by the following registers. • Low-voltage detection register (LVIM) • Low-voltage detection level selection register (LVIS) Preliminary User’s Manual U16315EJ1V0UD...
Page 372 CHAPTER 22 LOW-VOLTAGE DETECTOR (1) Low-voltage detection register (LVIM) This register sets low-voltage detection and the operation mode. This register can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears LVIM to 00H. Figure 22-2. Format of Low-Voltage Detection Register (LVIM) Note 1 Address: FFBEH After reset: 00H...
Page 373 CHAPTER 22 LOW-VOLTAGE DETECTOR (2) Low-voltage detection level selection register (LVIS) This register selects the low-voltage detection level. This register can be set by an 8-bit memory manipulation instruction. RESET input clears LVIS to 00H. Figure 22-3. Format of Low-Voltage Detection Level Selection Register (LVIS) Address: FFBFH After reset: 00H Symbol...
Page 374: Operation Of Low-Voltage Detector
CHAPTER 22 LOW-VOLTAGE DETECTOR 22.4 Operation of Low-Voltage Detector The low-voltage detector can be used in the following two modes. • Used as reset Compares the supply voltage (V ) and detection voltage (V ), and generates an internal reset signal when <...
Page 375 CHAPTER 22 LOW-VOLTAGE DETECTOR Figure 22-4. Timing of Low-Voltage Detector Internal Reset Signal Generation Supply voltage (V LVI detection voltage POC detection voltage 2.7 V Time <2> LVIMK flag (set by software) <1> LVIE flag Not cleared Not cleared (set by software) <3>...
Page 376 CHAPTER 22 LOW-VOLTAGE DETECTOR (2) When used as interrupt • When starting operation <1> Mask the LVI interrupt (LVIMK = 1). <2> Set the detection voltage using bits 2 to 0 (LVIS2 to LVIS0) of the low-voltage detection level selection register (LVIS).
Page 377 CHAPTER 22 LOW-VOLTAGE DETECTOR Figure 22-5. Timing of Low-Voltage Detector Interrupt Signal Generation Supply voltage (V LVI detection voltage POC detection voltage 2.7 V Time <2> LVIMK flag (set by software) <1> <9> Cleared by software LVIE flag (set by software) <3>...
Page 378: Cautions For Low-Voltage Detector
CHAPTER 22 LOW-VOLTAGE DETECTOR 22.5 Cautions for Low-Voltage Detector In a system where the supply voltage (V ) fluctuates for a certain period in the vicinity of the LVI detection voltage ), the operation is as follows depending on how the low-voltage detector is used. (1) When used as reset The system may be repeatedly reset and released from the reset status.
Page 379 CHAPTER 22 LOW-VOLTAGE DETECTOR Figure 22-6. Example of Software Processing After Release of Reset (1/2) • If supply voltage fluctuation is 50 ms or less in vicinity of LVI detection voltage ; The Ring-OSC clock is set as the CPU clock when the reset signal is generated Reset Checking cause The cause of reset (power-on-clear, WDT, LVI, or clock monitor)
Page 380 CHAPTER 22 LOW-VOLTAGE DETECTOR Figure 22-6. Example of Software Processing After Release of Reset (2/2) • Checking reset cause Check reset cause WDTRF of RESF register = 1? Reset processing by watchdog timer CLMRF of RESF register = 1? Reset processing by clock monitor LVIRF of RESF register = 1?
Page 381 CHAPTER 22 LOW-VOLTAGE DETECTOR (2) When used as interrupt Disable interrupts (DI) in the servicing routine of the LVI interrupt, and check to see if “supply voltage (V ) > detection voltage (V )”, by using bit 0 (LVIF) of the low-voltage detection register (LVIM). Then enable interrupts (EI).
Page 382: Chapter 23 Regulator
CHAPTER 23 REGULATOR 23.1 Outline The 78K0/KD1 Series includes a circuit to realize low-voltage operation inside the device. To stabilize the via a 0.1 µ F capacitor. regulator output voltage, connect the REGC pin to V The regulator of the 78K0/KD1 Series stops operating in the following cases.
Page 383: Chapter 24 Mask Options
CHAPTER 24 MASK OPTIONS Mask ROM versions are provided with the following mask options. Power-on-clear (POC) circuit • POC cannot be used • POC used (detection voltage: V = 2.85 V ±0.15 V) • POC used (detection voltage: V = 3.5 V ±0.2 V) Ring-OSC •...
Page 384: Chapter 25 Μ Μ Μ Μ Pd78F0124
CHAPTER 25 µ µ µ µ PD78F0124 The µ PD78F0124 is provided as the flash memory version of the 78K0/KD1 Series. The µ PD78F0124 replaces the internal mask ROM of the µ PD780124 with flash memory to which a program can be written, erased, and overwritten while mounted on the board.
Page 385: Internal Memory Size Switching Register
CHAPTER 25 µ µ µ µ PD78F0124 25.1 Internal Memory Size Switching Register The µ PD78F0124 allows users to select the internal memory capacity using the internal memory size switching register (IMS) so that the same memory map as that of the mask ROM versions with a different internal memory capacity can be achieved.
Page 386: Flash Memory Programming
CHAPTER 25 µ µ µ µ PD78F0124 25.2 Flash Memory Programming On-board writing of flash memory (with device mounted on target system) is supported. On-board writing is performed after connecting a dedicated flash programmer (Flashpro III (FL-PR3, PG- FP3)/Flashpro IV (FL-PR4, PG-FP4)) to the host machine and target system. Moreover, writing to flash memory can also be performed using a flash memory writing adapter connected to Flashpro III/Flashpro IV.
Page 387: Flash Memory Programming Function
CHAPTER 25 µ µ µ µ PD78F0124 Figure 25-2. Communication Mode Selection Format pulses 10 V RESET Flash memory write mode 25.2.2 Flash memory programming function Flash memory writing is performed via command and data transmit/receive operations using the selected communication mode.
Page 388: Connecting Flashpro Iii/Flashpro Iv
CHAPTER 25 µ µ µ µ PD78F0124 25.2.3 Connecting Flashpro III/Flashpro IV The connection between Flashpro III/Flashpro IV and the µ PD78F0124 differs depending on the communication mode (3-wire serial I/O or UART). Figures 25-3 to 25-7 show the connection diagrams of each case. Figure 25-3.
Page 389 CHAPTER 25 µ µ µ µ PD78F0124 Figure 25-5. Connection of Flashpro III/Flashpro IV in UART (UART0) Mode µ Flashpro III/Flashpro IV PD78F0124 RESET RESET RxD0 TxD0 Figure 25-6. Connection of Flashpro III/Flashpro IV in UART (UART0) Mode (Using Handshake) µ...
Page 390: Connection On Adapter For Flash Memory Writing
CHAPTER 25 µ µ µ µ PD78F0124 25.2.4 Connection on adapter for flash memory writing Examples of the recommended connection when using the adapter for flash memory writing are shown below. Figure 25-8. Example of Wiring Adapter for Flash Memory Writing in 3-Wire Serial I/O Mode (2.7 to 5.5 V) LVDD (VDD2) 52 51 50 49 48 47 46 45 44 43 42...
Page 391 CHAPTER 25 µ µ µ µ PD78F0124 Figure 25-9. Example of Wiring Adapter for Flash Memory Writing in 3-Wire Serial I/O Mode (Using Handshake) (2.7 to 5.5 V) LVDD (VDD2) 52 51 50 49 48 47 46 45 44 43 42 41 40 Note µ...
Page 392 CHAPTER 25 µ µ µ µ PD78F0124 Figure 25-10. Example of Wiring Adapter for Flash Memory Writing in UART (UART0) Mode (2.7 to 5.5 V) LVDD (VDD2) 52 51 50 49 48 47 46 45 44 43 42 41 40 Note µ...
Page 393 CHAPTER 25 µ µ µ µ PD78F0124 Figure 25-11. Example of Wiring Adapter for Flash Memory Writing in UART (UART0) Mode (Using Handshake) (2.7 to 5.5 V) LVDD (VDD2) 52 51 50 49 48 47 46 45 44 43 42 41 40 Note µ...
Page 394 CHAPTER 25 µ µ µ µ PD78F0124 Figure 25-12. Example of Wiring Adapter for Flash Memory Writing in UART (UART6) Mode (2.7 to 5.5 V) LVDD (VDD2) 52 51 50 49 48 47 46 45 44 43 42 41 40 Note µ...
Page 395: Chapter 26 Instruction Set
CHAPTER 26 INSTRUCTION SET This chapter lists each instruction set of the 78K0/KD1 Series in table form. For details of each operation and operation code, refer to the separate document 78K/0 Series Instructions User’s Manual (U12326E). 26.1 Conventions Used in Operation List 26.1.1 Operand identifiers and specification methods...
Page 396: Description Of Operation Column
CHAPTER 26 INSTRUCTION SET 26.1.2 Description of operation column A register; 8-bit accumulator X register B register C register D register E register H register L register AX register pair; 16-bit accumulator BC register pair DE register pair HL register pair Program counter Stack pointer PSW:...
Page 397: Operation List
CHAPTER 26 INSTRUCTION SET 26.2 Operation List Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 − r ← byte 8-bit data r, #byte transfer (saddr) ← byte saddr, #byte − sfr ← byte sfr, #byte −...
Page 398 CHAPTER 26 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 − rp ← word 16-bit data MOVW rp, #word transfer (saddrp) ← word saddrp, #word − sfrp ← word sfrp, #word AX ←...
Page 399 CHAPTER 26 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 − A, CY ← A − byte × × × 8-bit A, #byte operation (saddr), CY ← (saddr) − byte × ×...
Page 400 CHAPTER 26 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 − A ← A ∨ byte × 8-bit A, #byte operation (saddr) ← (saddr) ∨ byte × saddr, #byte − A ← A ∨ r ×...
Page 401 CHAPTER 26 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 − AX, CY ← AX + word × × × 16-bit ADDW AX, #word operation − AX, CY ← AX − word ×...
Page 402 CHAPTER 26 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 CY ← CY ∧ (saddr.bit) × AND1 CY, saddr.bit manipulate − CY ← CY ∧ sfr.bit × CY, sfr.bit − CY ← CY ∧ A.bit ×...
Page 403 CHAPTER 26 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 − (SP − 1) ← (PC + 3) , (SP − 2) ← (PC + 3) Call/return CALL !addr16 PC ← addr16, SP ← SP − 2 −...
Page 404 CHAPTER 26 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 PC ← PC + 3 + jdisp8 if (saddr.bit) = 1 Conditional saddr.bit, $addr16 branch − PC ← PC + 4 + jdisp8 if sfr.bit = 1 sfr.bit, $addr16 −...
Page 405: Instructions Listed By Addressing Type
CHAPTER 26 INSTRUCTION SET 26.3 Instructions Listed by Addressing Type (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ Note Second Operand #byte saddr !addr16 [DE]...
Page 406 CHAPTER 26 INSTRUCTION SET (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW Note Second Operand #word sfrp saddrp !addr16 None First Operand ADDW MOVW MOVW MOVW MOVW MOVW SUBW XCHW CMPW Note MOVW MOVW INCW DECW PUSH sfrp MOVW...
Page 407 CHAPTER 26 INSTRUCTION SET (4) Call instructions/branch instructions CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ Second Operand !addr16 !addr11 [addr5] $addr16 First Operand Basic instruction CALL CALLF CALLT Compound instruction BTCLR DBNZ (5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP Preliminary User’s Manual U16315EJ1V0UD...
Page 408: Chapter 27 Electrical Specifications (Target Values)
CHAPTER 27 ELECTRICAL SPECIFICATIONS (TARGET VALUES) These specifications are only target values, and may not be satisfied by mass-produced products. The electrical specifications (target values) of (A1) products are under evaluation. = 25° ° ° ° C) (1/2) Absolute Maximum Ratings (T Parameter Symbol Conditions...
Page 409 CHAPTER 27 ELECTRICAL SPECIFICATIONS (TARGET VALUES) = 25° ° ° ° C) (2/2) Absolute Maximum Ratings (T Parameter Symbol Conditions Ratings Unit Output current, low Per pin P00 to P03, P10 to P17, P30 to P33, P70 to P77, P120, P130, P140 P60 to P63 Total of...
Page 410 CHAPTER 27 ELECTRICAL SPECIFICATIONS (TARGET VALUES) X1 Oscillator Characteristics = − − − − 40 to +85° ° ° ° C, 2.7 V ≤ ≤ ≤ ≤ V ≤ ≤ ≤ ≤ 5.5 V, 2.7 V ≤ ≤ ≤ ≤ AV ≤...
Page 411 CHAPTER 27 ELECTRICAL SPECIFICATIONS (TARGET VALUES) Ring-OSC Oscillator Characteristics = − − − − 40 to +85° ° ° ° C, 2.7 V ≤ ≤ ≤ ≤ V ≤ ≤ ≤ ≤ 5.5 V, 2.7 V ≤ ≤ ≤ ≤ AV ≤...
Page 412 CHAPTER 27 ELECTRICAL SPECIFICATIONS (TARGET VALUES) DC Characteristics (1/4) = − − − − 40 to +85° ° ° ° C, 2.7 V ≤ ≤ ≤ ≤ V ≤ ≤ ≤ ≤ 5.5 V, 2.7 V ≤ ≤ ≤ ≤ AV ≤...
Page 413 CHAPTER 27 ELECTRICAL SPECIFICATIONS (TARGET VALUES) DC Characteristics (2/4) = − − − − 40 to +85° ° ° ° C, 2.7 V ≤ ≤ ≤ ≤ V ≤ ≤ ≤ ≤ 5.5 V, 2.7 V ≤ ≤ ≤ ≤ AV ≤...
Page 414 CHAPTER 27 ELECTRICAL SPECIFICATIONS (TARGET VALUES) DC Characteristics (3/4): µ µ µ µ PD78F0124 = − − − − 40 to +85° ° ° ° C, 2.7 V ≤ ≤ ≤ ≤ V ≤ ≤ ≤ ≤ 5.5 V, 2.7 V ≤ ≤ ≤ ≤ AV ≤...
Page 415 CHAPTER 27 ELECTRICAL SPECIFICATIONS (TARGET VALUES) DC Characteristics (4/4): Mask ROM version = − − − − 40 to +85° ° ° ° C, 2.7 V ≤ ≤ ≤ ≤ V ≤ ≤ ≤ ≤ 5.5 V, 2.7 V ≤ ≤ ≤ ≤ AV ≤...
Page 416 CHAPTER 27 ELECTRICAL SPECIFICATIONS (TARGET VALUES) AC Characteristics (1) Basic operation = − − − − 40 to +85° ° ° ° C, 2.7 V ≤ ≤ ≤ ≤ V ≤ ≤ ≤ ≤ 5.5 V, 2.7 V ≤ ≤ ≤ ≤ AV ≤...
Page 417 CHAPTER 27 ELECTRICAL SPECIFICATIONS (TARGET VALUES) vs. V (X1 Input Clock Operation) via 0.1 µ µ µ µ F capacitor (a) When REGC pin is connected to V 20.0 16.0 10.0 Guaranteed operation range 0.238 2.7 3.3 Supply voltage V (b) When REGC pin is directly connected to V 20.0 16.0...
Page 418 CHAPTER 27 ELECTRICAL SPECIFICATIONS (TARGET VALUES) (2) Serial interface = − − − − 40 to +85° ° ° ° C, 2.7 V ≤ ≤ ≤ ≤ V ≤ ≤ ≤ ≤ 5.5 V, 2.7 V ≤ ≤ ≤ ≤ AV ≤...
Page 419 CHAPTER 27 ELECTRICAL SPECIFICATIONS (TARGET VALUES) AC Timing Test Points (Excluding X1 Input) 0.8V 0.8V Test points 0.2V 0.2V Clock Timing (MIN.) X1 input (MAX.) (MIN.) XT1 input (MAX.) TI Timing TIL0 TIH0 TI00, TI010 TIL5 TIH5 TI50, TI51 Interrupt Request Input Timing INTL INTH INTP0 to INTP6...
Page 420 CHAPTER 27 ELECTRICAL SPECIFICATIONS (TARGET VALUES) RESET Input Timing RESET Serial Transfer Timing 3-wire serial I/O mode: KCYm SCK10 SIKm KSIm SI10 Input data KSOm SO10 Output data Remark m = 1, 2 Preliminary User’s Manual U16315EJ1V0UD...
Page 421 CHAPTER 27 ELECTRICAL SPECIFICATIONS (TARGET VALUES) A/D Converter Characteristics = − − − − 40 to +85° ° ° ° C, 2.7 V ≤ ≤ ≤ ≤ V ≤ ≤ ≤ ≤ 5.5 V, 2.7 V ≤ ≤ ≤ ≤ AV ≤...
Page 422 CHAPTER 27 ELECTRICAL SPECIFICATIONS (TARGET VALUES) = − − − − 40 to +85° ° ° ° C) POC Circuit Characteristics (T Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection voltage Mask option = 3.5 V POC0 Mask option = 2.85 V 2.85 POC1 : 0 V →...
Page 423 CHAPTER 27 ELECTRICAL SPECIFICATIONS (TARGET VALUES) = − − − − 40 to +85° ° ° ° C) LVI Circuit Characteristics (T Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection voltage LVI0 LVI1 LVI2 LVI3 LVI4 3.15 3.45 LVI5 2.95 3.25 LVI6 Note 1...
Page 424 CHAPTER 27 ELECTRICAL SPECIFICATIONS (TARGET VALUES) Flash Memory Programming Characteristics: µ µ µ µ PD78F0124 = +10 to +60° ° ° ° C, 2.7 V ≤ ≤ ≤ ≤ V ≤ ≤ ≤ ≤ 5.5 V, 2.7 V ≤ ≤ ≤ ≤ AV ≤...
Page 425 CHAPTER 27 ELECTRICAL SPECIFICATIONS (TARGET VALUES) (2) Serial write operation characteristics Parameter Symbol Conditions MIN. TYP. MAX. Unit µ s ↑ to V ↑ Set time from V µ s ↑ to RESET↑ t Release time from V pulse input start time from RESET↑...
Page 426: Chapter 28 Package Drawing
CHAPTER 28 PACKAGE DRAWING 52-PIN PLASTIC LQFP (10x10) detail of lead end ITEM MILLIMETERS 12.0±0.2 10.0±0.2 10.0±0.2 12.0±0.2 0.32±0.06 0.13 0.65 (T.P.) 1.0±0.2 0.17 +0.03 −0.05 0.10 0.1±0.05 3° +4° −3° 1.5±0.1 0.25 0.6±0.15 S52GB-65-8ET-2 Preliminary User’s Manual U16315EJ1V0UD...
Page 427: Chapter 29 Cautions For Wait
CHAPTER 29 CAUTIONS FOR WAIT 29.1 Cautions for Wait This product has two internal system buses. One is a CPU bus and the other is a peripheral bus that interfaces with the low-speed peripheral hardware. Because the clock of the CPU bus and the clock of the peripheral bus are asynchronous, unexpected illegal data may be passed if an access to the CPU conflicts with an access to the peripheral hardware.
Page 428: Peripheral Hardware That Generates Wait
CHAPTER 29 CAUTIONS FOR WAIT 29.2 Peripheral Hardware That Generates Wait Table 29-1 lists the registers that issue a wait request when accessed by the CPU, and the number of CPU wait clocks. Table 29-1. Registers That Generate Wait and Number of CPU Wait Clocks Peripheral Hardware Register Access...
Page 429: Example Of Wait Occurrence
CHAPTER 29 CAUTIONS FOR WAIT 29.3 Example of Wait Occurrence <1> Watchdog timer <On execution of MOV WDTM, A> Number of execution clocks: 8 (5 clocks when data is written to a register that does not issue a wait (MOV sfr, A).) <On execution of MOV WDTM, #byte>...
Page 430: Appendix A Development Tools
APPENDIX A DEVELOPMENT TOOLS The following development tools are available for the development of systems that employ the 78K0/KD1 Series. Figure A-1 shows the development tool configuration. • • • • Support for PC98-NX series Unless otherwise specified, products supported by IBM PC/AT compatibles are compatible with PC98-NX series computers.
Page 431 APPENDIX A DEVELOPMENT TOOLS Figure A-1. Development Tool Configuration Language Processing Software • Assembler package • C compiler package • C library source file • Device file Debugging Tool • System simulator • Integrated debugger • Device file Embedded Software •...
Page 432: Software Package
APPENDIX A DEVELOPMENT TOOLS A.1 Software Package SP78K0 Development tools (software) common to the 78K/0 Series are combined in this package. 78K/0 Series software package Part number: µ S××××SP78K0 Remark ×××× in the part number differs depending on the host machine and OS used. µ...
Page 433: Language Processing Software
APPENDIX A DEVELOPMENT TOOLS A.2 Language Processing Software RA78K0 This assembler converts programs written in mnemonics into object codes executable Assembler package with a microcontroller. This assembler is also provided with functions capable of automatically creating symbol tables and branch instruction optimization. This assembler should be used in combination with a device file (DF780124) (sold separately).
Page 434: Flash Memory Writing Tools
APPENDIX A DEVELOPMENT TOOLS Remark ×××× in the part number differs depending on the host machine and OS used. µ S××××RA78K0 µ S××××CC78K0 ×××× Host Machine Supply Medium AB13 PC-9800 series, Windows (Japanese version) 3.5-inch 2HD FD IBM PC/AT compatibles BB13 Windows (English version) AB17...
Page 435: Debugging Tools
APPENDIX A DEVELOPMENT TOOLS A.4 Debugging Tools A.4.1 Hardware IE-78K0-NS The in-circuit emulator serves to debug hardware and software when developing In-circuit emulator application systems using a 78K/0 Series product. It corresponds to the integrated debugger (ID78K0-NS). This emulator should be used in combination with a power supply unit, emulation probe, and the interface adapter required to connect this emulator to the host machine.
Page 436: Software
APPENDIX A DEVELOPMENT TOOLS A.4.2 Software SM78K0 This system simulator is used to perform debugging at C source level or assembler level System simulator while simulating the operation of the target system on a host machine. This simulator runs on Windows. Use of the SM78K0 allows the execution of application logical testing and performance testing on an independent basis from hardware development without having to use an in- circuit emulator, thereby providing higher development efficiency and software quality.
Page 437: Appendix B Embedded Software
APPENDIX B EMBEDDED SOFTWARE The following embedded products are available for efficient development and maintenance of the 78K0/KD1 Series. Real-Time OS The RX78K0 is a real-time OS conforming to the µ ITRON specifications. RX78K0 Real-time OS A tool (configurator) for generating the nucleus of the RX78K0 and multiple information tables is supplied.
Page 438: Appendix C Register Index
APPENDIX C REGISTER INDEX C.1 Register Index (In Alphabetical Order with Respect to Register Names) A/D conversion result register (ADCR)........................226 A/D converter mode register (ADM) ........................... 228 Analog input channel specification register (ADS) ..................... 230 Asynchronous serial interface control register 6 (ASICL6)..................281, 288 Asynchronous serial interface operation mode register 0 (ASIM0) .............249, 253, 254 Asynchronous serial interface operation mode register 6 (ASIM6) .............275, 283, 284 Asynchronous serial interface reception error status register 0 (ASIS0) .............251, 256...
Page 439 APPENDIX C REGISTER INDEX Interrupt mask flag register 1L (MK1L)........................330 Interrupt request flag register 0H (IF0H) ........................329 Interrupt request flag register 0L (IF0L) ........................329 Interrupt request flag register 1L (IF1L) ........................329 Key return mode register (KRM) ..........................342 Low-voltage detection level selection register (LVIS)....................373 Low-voltage detection register (LVIM) ........................372 Main clock mode register (MCM) ..........................108 Main OSC control register (MOC) ..........................109...
Page 440 APPENDIX C REGISTER INDEX Pull-up resistor option register 3 (PU3) ........................100 Pull-up resistor option register 7 (PU7) ........................100 Receive buffer register 0 (RXB0) ..........................248 Receive buffer register 6 (RXB6) ..........................274 Reset control flag register (RESF) ..........................359 Ring-OSC mode register (RCM) ..........................
Page 441: Register Index (In Alphabetical Order With Respect To Register Symbol)
APPENDIX C REGISTER INDEX C.2 Register Index (In Alphabetical Order with Respect to Register Symbol) ADCR: A/D conversion result register .........................226 ADM: A/D converter mode register ........................228 ADS: Analog input channel specification register .....................230 ASICL6: Asynchronous serial interface control register 6................281, 288 ASIF6: Asynchronous serial interface transmission status register 6............278, 287 ASIM0:...
Page 442 APPENDIX C REGISTER INDEX LVIS: Low-voltage detection level selection register ..................373 MCM: Main clock mode register........................108 MK0H: Interrupt mask flag register 0H ....................... 330 MK0L: Interrupt mask flag register 0L........................ 330 MK1L: Interrupt mask flag register 1L........................ 330 MOC: Main OSC control register ........................
Page 443 APPENDIX C REGISTER INDEX RXB6: Receive buffer register 6 .........................274 SIO10: Serial I/O shift register 10........................312 SOTB10: Transmit buffer register 10 ........................312 TCL50: Timer clock selection register 50......................165 TCL51: Timer clock selection register 51......................165 TM00: 16-bit timer counter 00 ..........................131 TM50: 8-bit timer counter 50 ..........................164 TM51:...
Page 444 [MEMO] Preliminary User’s Manual U16315EJ1V0UD...
Page 445 Facsimile Message Although NEC has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that From: errors may occur. Despite all the care and precautions we've taken, you may Name encounter problems in the documentation.

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NEC 78K0/KD1 Series User Manual

Chapter 1 Outline

Chapter 2 Pin Functions

Chapter 3 Cpu Architecture

Chapter 4 Port Functions

Chapter 5 Clock Generator

Chapter 6 16-Bit Timer/Event Counter 00

Chapter 7 8-Bit Timer/Event Counters 50 and 51

Chapter 8 8-Bit Timers H0 and H1

Chapter 9 Watch Timer

Chapter 10 Watchdog Timer

Chapter 11 Clock Output Controller

Chapter 12 A/D Converter

Chapter 13 Serial Interface Uart0

Chapter 14 Serial Interface Uart6

Chapter 15 Serial Interface Csi10

Chapter 16 Interrupt Functions

Chapter 17 Key Interrupt Function

Chapter 18 Standby Function

Chapter 19 Reset Function

Chapter 20 Clock Monitor

Chapter 21 Power-On-Clear Circuit

Chapter 22 Low-Voltage Detector

Chapter 23 Regulator

Chapter 24 Mask Options

CHAPTER 25 Μ Μ Μ Μ PD78F0124

Chapter 26 Instruction Set

Chapter 27 Electrical Specifications (Target Values)

Chapter 28 Package Drawing

Chapter 29 Cautions for Wait

Appendix A Development Tools

Appendix B Embedded Software

Appendix C Register Index

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Summary of Contents for NEC 78K0/KD1 Series