Table of Contents
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YPbPr
001
IC500
(7/11)
EP2C50F484C8N
BANK7
R560 2.2k
V12
W12
I_74M
GND
AA20
PR[0]
I_PR[0]
AA19
PR[2]
I_PR[2]
AB20
AA18
PR[1]
PR[4]
I_PR[1]
I_PR[4]
AB19
AA17
PR[3]
PR[6]
I_PR[3]
I_PR[6]
AB18
AB14
PR[5]
Y[2]
I_PR[5]
I_Y[2]
AB17
AA14
PR[7]
Y[1]
I_PR[7]
I_Y[1]
R501
68
AB16
Y14
PR[9]
I_PR[9]
O_Adclk
ADclk
AA16
Y13
PR[8]
I_PR[8]
O_A_clp
A_clp
AB15
W14
R502
Y[0]
PB[7]
I_Y[0]
I_PB[7]
68
AA15
V14
PB[5]
PB[8]
I_PB[5]
I_PB[8]
PB[4]
W15
I_PB[4]
W16
PB[1]
I_PB[1]
Y16
PB[2]
I_PB[2]
Y17
U13
CL505 0.8
PB[0]
I_PB[0]
U14
PB[9]
I_PB[9]
U15
PB[6]
I_PB[6]
V15
PB[3]
I_PB[3]
AB13
Y[4]
I_Y[4]
AA13
Y[3]
I_Y[3]
AA12
Y[5]
I_Y[5]
AB12
Y[6]
I_Y[6]
+3.1V-3
R566
10k
C573
RB544
RB545
0.1uF
47k
47k
DIP-SW2 ASSIGN
GND
CN501
RB546
S_ASSIGN
220
R567 2.2k
SW_ASSIGN
S2_0
1
2
SW_S2[0]
S2_1
3
4
SW_S2[1]
S2_2
5
6
SW_S2[2]
S2_3
7
8
SW_S2[3]
S2_4
1
2
SW_S2[4]
S2_5
3
4
SW_S2[5]
S2_6
5
6
SW_S2[6]
7
8
S2_7
SW_S2[7]
RB547
GND
220
SL1
12
13
GND
IC500
(6/11)
EP2C50F484C8N
BANK6
R559 2.2k
M21
M22
R548
47
I_74M_2
001
74M_2
GND
N22
IO_RAM1_DQ[6]
IO_RAM1_DQ[6]
N21
IO_RAM1_DQ[3]
IO_RAM1_DQ[3]
IO_RAM1_DQ[28]
R22
O_TALLY_UD_C V20
IO_RAM1_DQ[28]
R21
O_INIT_DONE V19
IO_RAM1_DQ[24]
IO_RAM1_DQ[24]
R20
IO_RAM1_DQ[11] W22
IO_RAM1_DQ[27]
IO_RAM1_DQ[27]
R19
IO_RAM1_DQ[14] W21
O_TALLY_D_L1
001
O_TALLY_D_L1
T22
IO_RAM1_DQ[13] Y22
IO_RAM1_DQ[25]
IO_RAM1_DQ[25]
T21
IO_RAM1_DQ[15] Y21
IO_RAM1_DQ[29]
IO_RAM1_DQ[29]
U20
O_TALLY_D_R1 Y20
001
O_TALLY_D_L2
O_TALLY_D_L2
U19
O_TALLY_U_R1 Y19
001
O_TALLY_U_R2
O_TALLY_U_R2
R18
I_INIT_DONE_DELAY Y18
001
O_TALLY_U_L1
O_TALLY_U_L1
R17
S2_2
P18
O_TALLY_D_R2
001
O_TALLY_D_R2
P17
IO_RAM1_DQ[9] U21
O_TALLY_U_L2
001
O_TALLY_U_L2
IO_RAM1_DQ[10] V22
P19
IO_RAM1_DQ[12] V21
IO_RAM1_DQ[21]
IO_RAM1_DQ[21]
P20
IO_RAM1_DQ[23]
IO_RAM1_DQ[23]
P21
IO_RAM1_DQ[5]
IO_RAM1_DQ[5]
P22
IO_RAM1_DQ[8] U22
IO_RAM1_DQ[26]
IO_RAM1_DQ[26]
W18
001
PACIFIC_H_ACT
IO_RAM1_DQ[20] M19
IO_RAM1_DQ[22] M18
HDVF-C30WR
I
J
+3.1V-3
L500
C503
4.7uH
6.3V
10uF
GND
O_ADclk
001
GND
O_A_clp
001
IC500
(9/11)
EP2C50F484C8N
JTAG/ISP Chain
CN3
PF_TDI
PF_TDI
EPR CN
PF_TDO
1
2
3
4
5
6
7
8
001
PLL
9
10
11
R561 2.2k
R562 2.2k
74M
LCD2_CONT
001
+3.1V-3
GND
PLL_REF
R521
B[4]
R564
R563
10k
10k
L2_CS
7
8
L2_SCL
T18
S2_1
5
6
L2_SDI
U18
S2_0
3
4
L2_RESET
1
2
RB542
47
B[5]
PLL_FB
R523
O_TALLY_UD_C
001
68
R520
B[2]
INIT_DONE
002
B[9]
IO_RAM1_DQ[11]
Y[9]
IO_RAM1_DQ[14]
Y[8]
IO_RAM1_DQ[13]
IO_RAM1_DQ[15]
O_TALLY_D_R1
001
Y[7]
O_TALLY_U_R1
001
B[6]
INIT_DONE_DELAY
002
W20
IO_RAM1_DQ[9]
IO_RAM1_DQ[10]
IO_RAM1_DQ[12]
IO_RAM1_DQ[8]
IO_RAM1_DQ[20]
IO_RAM1_DQ[22]
K
PR-312 (2/2)
PR-312 (2/2)
SUFFIX: -12
SUFFIX: -12
IC500
(10/11)
EP2C50F484C8N
C504
10uF
+3.1V-3
GND
L502
10uH
C509
6.3V
10uF
+1.2V
GND
FB500
FB501
FB502
500
GND
PF_TDO(PF->FPGA)
CPLD
FPGA
IC1
EPR2
CN
001
EPCS64
001
0
001
Pacific bord
FPGA bord
001
O_CLK_IF
IC500
(8/11)
EP2C50F484C8N
BANK8
U11
AB11
B[7]
U12
O_D_B[7]
AB10
B[3]
O_D_B[3]
AB9
R509
47
O_H_X
Y10
O_H_x
68
O_PLL_REF
AB8
O_OSD_CLK
Y9
O_OSD_CLK
O_D_B[4]
AB7
O_OSD_D[2]
Y7
O_OSD_D[2]
O_D_B[1]
AB6
O_OSD_D[3]
Y6
O_OSD_D[3]
O_L2_SDI
AB5
O_CPU_BE_L_x
O_CPU_BE_L_x
AB4
O_CPU_BE_U_x
O_CPU_BE_U_x
AB3
O_P_RST_PLL1_X
Y5
O_L2_CS
O_OSD_CLK
W7
O_L2_RESET
O_OSD_D[3]
V8
O_D_B[0]
O_OSD_D[0]
W8
O_D_B[5]
O_OSD_D[2]
V9
68
O_PLL_FB
O_OSD_D[1]
W9
O_D_B[2]
AA11
B[8]
O_OSD_BLK
AA10
O_D_B[8]
O_D_B[9]
V11
I_Y[9]
AA9
O_FLD
W11
I_Y[8]
AA8
R506
47
O_V_X
O_V_x
AA7
O_OSD_D[1]
O_OSD_D[1]
AA6
O_D_T
O_OSD_D[0]
O_OSD_D[0]
U10
I_Y[7]
AA5
O_OSD_BLK
U9
O_OSD_BLK
O_D_B[6]
AA4
O_CPU_OE_x
U8
O_CPU_OE_x
O_L2_SCL
AA3
O_P_RST_PLL2_X
1
B[5]
3
B[6]
B[2]
5
B[4]
7
B[8]
1
B[7]
3
B[9]
5
B[3]
7
4-7
4-7
L
M
IC500
(11/11)
EP2C50F484C8N
+1.2V
L503
C507
10uH
6.3V
10uF
FB503
FB504
GND
GND
GND-PLL
GND-ANA
+3.1V-3
FB505
FB506
R526
10k
R529
R531
GND
GND-PLL
GND
GND-ANA
10k
10k
NM
NM
+3.1V-3
R525
R527
10k
10k
R528
R530
R513
R515
10k
10k
10k
10k
GND
TDI
TDO
TMS
TCK
R512
10k
EPR2
+3.1V-3
GND
CN500
1
VCC
2
DATAOUT
3
ASDI
4
CONF_DONE
5
nCONFIG
nCONFIG
6
DCLK
7
MODE(H)
8
GND
9
nCE
10
nCS
R532
12 11
10k
JST-angle-10p
GND
GND
47
R517
OSD_CLK
2
1
OSD_D[3]
RB543
4
3
+3.1V-3
OSD_D[0]
6
5
OSD_D[2]
8
7
47
OSD_D[1]
IC501
R500
OSD_BLK
R3112N221A-TR-FA
2
47
R545
10k
68
VDD
1
R519
OUT
001
OSD
4
5
NC
CD
GND
001
C500
3
0.0022uF
GND
9-10mS Delay
2.2V RESET
RB538
47
2
O_D_B[5]
4
O_D_B[6]
R516
6
O_D_B[2]
47k
1k
8
O_D_B[4]
R544
002
INIT_DONE
RB527
C501
+3.1V-3
47
1000pF
2
O_D_B[8]
GND
4
O_D_B[7]
6
O_D_B[9]
VCC
C567
0.1uF
8
O_D_B[3]
GND
IC503
(2/2)
TC7SH14FU(T5RSOYJF)
O_D_B
001
GND
N
O
1
GND
GND
2
+3.1V-3
IC502
EPCS
EPCS64SI16N
C502
0.1uF
GND
15
8
ASDI
DATA
16
DCLK
7
CS
3
11
NC1
NC5
4
12
NC2
NC6
3
5
13
NC3
NC7
6
14
NC4
NC8
GND
002
4
nCONFIG
002
+3.1V-3
IC504
TC7SH32FU(T5RSOYJF)
5
2
R565
68
4
1
XRESET
001
C572
3
0.1uF
GND
(1/2)
IC503
TC7SH14FU(T5RSOYJF)
2
4
INIT_DONE_DELAY
002
I_INIT_DONE_DELAY
5
PR-312 (2/2)
BOARD NO. 1-879-250-12
P
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