Sharp FACSIMILE XU-107 Service Manual page 56

UX-177H
SFE-LC (IC8) terminal descriptions
Pin Name Pin No.
MIRQn 135
SYSCLK 133
TSTCLK 130
A[19:0] [5:6][8:13]
[15:20][22:27]
D[7:0] [136:139]
[141:144]
RDn 128
WRn 127
ROMCSn 120
CS1n 122
CS0n 57
MCSn 121
SYNC 126
REGDMA 124
WAITn 125
DEBUGn 129
RESETn 131
TEST 58
XIN 59
XOUT 60
PWRDWNn 62
BATRSTn 61
START 101
CLK1 100
CLK1n 99
CLK2 98
VIDCTL[1:0] [97:96]
PCLK 29
PDAT 30
PLAT 31
STRB[3:0] [33:36]
STRBPOL 37
Input Output
I/O
Type Type
CPU Control Interface
−
I HU Modem interrupt. (Hysteresis In, Internal Pullup.)
−
I H System clock. (Hysteresis In.)
−
O 3XC Test clock.
Bus Control Interface
O T 3XT Address bus (20-bit).
I/O T 3XT Data bus (8-bit).
−
O 3XTT Read strobe.
−
O 3XTT Write strobe.
−
O 2XT ROM chip select.
−
O 2XT I/O chip select.
−
O 2XTT SRAM chip select. (Battery powered.)
−
O 2XC Modem chip select.
−
O 2XC Indicates CPU op code fetch cycle (active high).
−
O 3XC Indicates REGSEL cycle and DMA cycle.
−
O 3XC Indicates current TSTCLK cycle is a wait state or a halt state.
Prime Power Reset Logic and Test
−
I HU External non-maskable input (NMI).
I/O HU 2XO XFC-B Reset.
−
I C Sets Test mode (battery powered).
Battery Power Control and Reset Logic
−
I OSC Crystal oscillator input pin.
−
O OSC Crystal oscillator output pin.
−
I H Indicates loss of prime power (results in NMI).
−
I H Battery power reset input.
Scanner Interface
−
O 2XS Scanner shift gate control.
−
O 2XS Scanner clock.
−
O 2XS Scanner clock-inverted.
−
O 2XS Scanner reset gate control (or clock for CIS scanner).
−
O 2XC Control for video preprocessing circuits.
−
O 3XC Thermal Print Head (TPH) clock.
−
O 2XP Serial printing data (to TPH).
−
O 3XP TPH data latch.
−
O 1XP Strobe signals for the TPH.
−
I C Sets strobe polarity, active high/low.
(Active low signals have an "n" pin name ending.)
Printer Interface
5 – 3
Pin Description