LG 32LW5700 Manual page 35

VDDC10 +1.5V_FRC_DDR +1.5V_FRC_DDR
+1.26V_FRC VDDC10
L5205
CIC21J501NE
C5210 C5211 C5243 C5225 C5228 C5213
C5201
0.1uF
0.1uF 22uF 22uF 0.22uF 0.1uF 0.1uF
10V 10V 6.3V
+1.26V_FRC DVDD_DDR_1V
L5201
CIC21J501NE
C5202 C5246 C5206
0.1uF 22uF 0.1uF
10V
Place Close to Bead
VDD33 VDD33 (VDDP)
+3.3V_FRC
L5202
CIC21J501NE
C5203 C5207 C5214 C5219 C5245
0.1uF 0.1uF 0.1uF 0.1uF 0.22uF
6.3V
AVDD33
+3.3V_FRC AVDD33
L5206
CIC21J501NE
C5238 C5239
C5233 C5236
0.1uF 0.1uF
0.1uF 0.1uF
AVDD_PLL AVDD_PLL
+3.3V_FRC
L5203
CIC21J501NE
C5204 C5208 C5215 C5217
0.1uF 0.1uF 10uF 0.1uF
6.3V
AVDD_LVDS_3.3V
+3.3V_FRC AVDD_LVDS_3.3V
L5204
CIC21J501NE
C5205 C5209 C5216 C5220 C5223 C5227
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
GPIO1 : HI => B8/94, LOW => B4/98
CHIP_CONF : {GPIO8, PWM1, PWM0}
CHIP_CONF = 3'd5 : boot from interal SRAM
CHIP_CONF = 3'd6 : boot from EEPROM
CHIP_CONF = 3'd7 : boot from SPI Flash
URSA5 CONFIGURATION
+3.3V_FRC
PWM0
PWM1
GPIO[8]
GPIO[1]
URSA5 H/W OPTION
+3.3V_FRC
URSA_MODEL_OPT_0
URSA_MODEL_OPT_1
URSA_MODEL_OPT_2
2D/3D_CTL
MODEL OPTION
PIN NAME PIN NO. HIGH
MODEL_OPT_0 D10 L/DIM_10BLOCK
MODEL_OPT_1 D11 RESERVED
D12
MODEL_OPT_2 LVDS_EXT_URSA5
D13
MODEL_OPT_3 RESERVED
Debugging for URSA5
P5201
12507WR-04L
URSA5_DEBUG
1
2
SCL1_3.3V
URSA5_DEBUG
R5258
R5201 22
3 0
SCL1_+3.3V_DB
URSA5_MP
SCL1_+3.3V_URSA
URSA5_DEBUG
R5260
R5202 22
4 0
SDA1_+3.3V_DB OPT
SCL1_+3.3V_DB
5
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
C5244 C5231 C5232 C5234 C5247
0.22uF 0.1uF 0.1uF 0.1uF 1uF
6.3V 6.3V
FRC_A[0-13]
FRC_A[0] P14
DDR3_A0/DDR2_NC
FRC_A[1] G15
DDR3_A1/DDR2_A8
FRC_A[2] N14
DDR3_A2/DDR2_NC
FRC_A[3] L15
DDR3_A3/DDR2_A10
FRC_A[4] H15
DDR3_A4/DDR2_A2
FRC_A[5] L14
DDR3_A5/DDR2_A3
FRC_A[6] G14
DDR3_A6/DDR2_A4
FRC_A[7] N12
DDR3_A7/DDR2_A5
FRC_A[8] G13
DDR3_A8/DDR2_A6
FRC_A[9] N13
DDR3_A9/DDR2_A9
FRC_A[10] H14
DDR3_A10/DDR2_RASZ
FRC_A[11] F15
DDR3_A11/DDR2_A11
FRC_A[12] H13
DDR3_A12/DDR2_A0
P13
FRC_A[13]
DDR3_A13/DDR2_A12
M12
FRC_BA0
DDR3_BA0/DDR2_BA2
H12
FRC_BA1 DDR3_BA1/DDR2_CASZ
L13
FRC_BA2
DDR3_BA2/DDR2_A1
F16
FRC_MCLK
DDR3_MCLK/DDR2_MCLK
F17
FRC_MCLKB DDR3_MCLKZ/DDR2_MCLKZ
J13
FRC_CKE DDR3_CKE/DDR2_ODT
K12
FRC_ODT DDR3_ODT/DDR2_CKE
L12
FRC_RASB DDR3_RASZDDR2_WEZ
K13
FRC_CASB DDR3_CASZ/DDR2_BA1
K14
FRC_WEB
DDR3_WEZ/DDR2_BA0
M14
FRC_DDR3_RESETB
DDR3_RESET/DDR2_A7
N16
FRC_DQSL
DDR3_DQSL/DDR2_DQSL
M17
FRC_DQSU DDR3_DQSU/DDR2_DQSU
M16
FRC_DQSLB DDR3_DQSBL/DDR2_DQSBL
M15
FRC_DQSUB DDR3_DQSBU/DDR2_DQSBU
J15
FRC_DML DDR3_DQML/DDR2_DQU5
R16
FRC_DQL[0-7]
FRC_DMU DDR3_DQMU/DDR2_DQU4
FRC_DQL[0] R17
DDR3_DQL0/DDR2_DQU3
FRC_DQL[1] H17
DDR3_DQL1/DDR2_DQL0
FRC_DQL[2] R15
DDR3_DQL2/DDR2_DQL6
FRC_DQL[3] J17
DDR3_DQL3/DDR2_DQL7
FRC_DQL[4] T17
DDR3_DQL4/DDR2_DQL3
FRC_DQL[5] H16
DDR3_DQL5/DDR2_DQL2
FRC_DQL[6] T15
DDR3_DQL6/DDR2_DQL1
FRC_DQL[7] G16
DDR3_DQL7/DDR2_DQL5
FRC_DQU[0] K15
DDR3_DQU0/DDR2_DQU7
FRC_DQU[1] N15
DDR3_DQU1/DDR2_DQML
FRC_DQU[2] K17
DDR3_DQU2/DDR2_DQU2
FRC_DQU[3] P17
DDR3_DQU3/DDR2_DQU6
FRC_DQU[4] L17
DDR3_DQU4/DDR2_NC
FRC_DQU[5] P16
DDR3_DQU5/DDR2_DQU1
FRC_DQU[6] K16
DDR3_DQU6/DDR2_DQU0
FRC_DQU[7] P15
DDR3_DQU7/DDR2_DQMU
FRC_DQU[0-7] F14
DDR3_NC/DDR2_A13
T16
+3.3V_FRC
DDR3_NC/DDR2_DQL4
R5220 4.7K OPT
D14
I2CM_SCL
R5221 4.7K OPT
D15
I2CM_SDA
P1
33 R5222
SCL1_+3.3V_URSA I2CS_SCL
33 R5223 P2
I2CS_SDA
SDA1_+3.3V_URSA
LOW
L/DIM_16BLOCK
RESERVED
LVDS_S7M_PLUS
RESERVED
SW5201
JS2235S
1 6
SDA1_3.3V
R5259
0
URSA5_MP
2 5
SDA1_+3.3V_URSA
URSA5_DEBUG R5261
0
OPT
3 4
SDA1_+3.3V_DB
PLACE TERMINATION RESISTORS CLOSE TO URSA5
R5224 R5230
100 100
R5225 R5231
100 100
R5226 R5232
100 100
R5227 R5233
1M
100 100
R5237
R5228 R5234
100 100
R5229 R5235
100 100
IC5201
LGE7303C
URSA5_UO2_RESET
+3.3V_FRC
Q5202
AO3407A
URSA5_UO2_RESET
R5255 C5212
R5219 22K 4.7uF
10K 16V URSA5_UO2_RESET
OPT
URSA5_UO2_RESET
R5262
2.2K
URSA5_UO2_RESET
C
R5254
4.7K B Q5201
FRC_RESET
2SC3052
URSA5_UO2_RESET
R5256 E
10K
OPT
R5243 33
URSA5_UO3_RESET
[SPI FLASH(2Mbit)] +3.3V_FRC
IC5202
R5244 R5246 W25X20BVSNIG
4.7K 10K
CS VCC
1 8
SPI_CS
R5245 DO HOLD R5252
2 7
SPI_DO
33 3.3K
WP CLK
3 6
SPI_SCLK
GND DIO
4 5
SPI_DI
URSA5_FLASH_WINBOND_2M
IC5202-*1
MX25L2006EM1I-12G, HF
CS
1 8
SO/SIO1
2 7
WP
3 6
GND
4 5
URSA5_FLASH_MACRONIX_2M
C8
RXA0+
TXA0P/GCLK6/BLUE[7]
C9
TXA0N/GCLK5/BLUE[6] RXA0-
B8
RXA1+
TXA1P/OPT_N/LK3/BLUE[9]
A8
TXA1N/FLK/BLUE[8] RXA1-
A7
RXA2+
TXA2P/GREEN[1]
B7
TXA2N/OPT_P/LK2/GREEN[0] RXA2-
C6
RXACK+
TXACLKP/RLV0N/GREEN[3]
C7
TXACLKN/RLV0P/GREEN[2] RXACK-
B6
TXA3P/RLV1N/GREEN[5] RXA3+
A6
TXA3N/RLV1P/GREEN[4] RXA3-
A5
TXA4P/RLV2N/GREEN[7] RXA4+
B5
TXA4N/RLV2P/GREEN[6] RXA4-
C4
RXB0+
TXB0P/RLV3N/GREEN[9]
C5
TXB0N/RLV3P/GREEN[8] RXB0-
B4
RXB1+
TXB1P/RLVCLKN/RED[1]
A4
TXB1N/RLVCLKP/RED[0] RXB1-
A3
RXB2+
TXB2P/RLV4P/RED[3]/EPI_A3P
B3
TXB2N/RLV4N/RED[2]/EPI_A3N RXB2-
C2
RXBCK+
TXBCLKP/RLV5N/RED[5]/EPI_A2P
C3
TXBCLKN/RLV5P/RED[4]/EPI_A2N RXBCK-
B2
TXB3P/RLV6N/RED[7]/EPI_A1P RXB3+
A2
TXB3N/RLV6P/RED[6]/EPI_A1N/ RXB3-
C1
TXB4P/RLV7N/RED[9]/EPI_A0P RXB4+
B1
TXB4N/RLV7P/RED[8]/EPI_A0N RXB4-
C16
RXC0+
TXC0P/SOE
B17
TXC0N/POL RXC0-
B16
RXC1+
TXC1P/GSP_R
A16
TXC1N/GSP/VST RXC1-
A15
RXC2+
TXC2P/GOE/GCLK1
B15
TXC2N/GSC/GCLK3 RXC2-
C14
RXCCK+
TXCCLKP/LLV0N
C15
TXCCLKN/LLV0P RXCCK-
B14
TXC3P/LLV1N RXC3+
A14
TXC3N/LLV1P RXC3-
A13
TXC4P/LLV2N RXC4+
B13
TXC4N/LLV2P RXC4-
C12
RXD0+
TXD0P/LLV3N
C13
TXD0N/LLV3P RXD0-
B12
RXD1+
TXD1P/LLVCLKN
A12
TXD1N/LLVCLKP RXD1-
A11
RXD2+
TXD2P/LLV4N/EPI_B3P
B11
TXD2N/LLV4P/EPI_B3N RXD2-
C10
RXDCK+
TXDCLKP/LLV5N/BLUE[1]/EPI_B2P
C11
TXDCLKN/LLV5P/BLUE[0]/EPI_B2N RXDCK-
B10
RXD3+
TXD3P/LLV6N/BLUE[3]
A10
TXD3N/LLV6P/BLUE[2]/EPI_B1N RXD3-
A9
TXD4P/LLV7N/BLUE[5]/EPI_B0P RXD4+
B9
TXD4N/LLV7P/BLUE[4]/EPI_B0N RXD4-
D10
MOD_GPIO0/VDD_ODD/HSYNC URSA_MODEL_OPT_0
D11
URSA_MODEL_OPT_1
MOD_GPIO1/VDD_EVEN/VSYNC
D12
MOD_GPIO2/PWM13/GCLK4/LCK URSA_MODEL_OPT_2
D13
2D/3D_CTL
MOD_GPIO3/PWM14/GCLK2/LDE
R5253 3D-SG 33
3D_SYNC_RF 3D_SYNC_RF
U12
R5250
33
PWM0/SCAN_BLK1 PWM0
T12
R5251 33
PWM1
PWM1/SCAN_BLK2
G3
LPLL_FBCLK
E17
LPLL_OUTCLK
H3
LPLL_REFIN
MStar URSA5 2010. 08.18
FRC block
52 55
VCC
HOL
SCL
SI/S