LG 32LW5700 Manual page 36

Close to DDR Pin
+1.5V_FRC_DDR
+1.5V_FRC_DDR
R5301
1K
1%
MVREFCA
R5302
1K
1% C5301
0.1uF
+1.5V_FRC_DDR
R5303
1K
1%
MVREFDQ
R5304
1K
1%
C5302
0.1uF
+1.5V_FRC_DDR
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
+1.5V_FRC_DDR
DDR3 1.5V De-Cap
C5303 C5304
0.1uF 22uF
16V 10V
Place Close to DDR Pin
IC5301
H5TQ1G63DFR-PBC
URSA5_DDR3_HYNIX
M8 N3 DDR3_A[0]
MVREFCA
VREFCA A0
P7 DDR3_A[1]
A1
P3 DDR3_A[2]
A2
H1 N2 DDR3_A[3]
MVREFDQ
VREFDQ A3
P8 DDR3_A[4]
A4
P2 DDR3_A[5]
A5
R5305
L8 R8 DDR3_A[6]
ZQ A6
R2 DDR3_A[7]
240
A7
1% T8 DDR3_A[8]
A8
B2 R3 DDR3_A[9]
VDD_1 A9
D9 L7 DDR3_A[10]
VDD_2 A10/AP
G7 R7 DDR3_A[11]
VDD_3 A11
K2 N7 DDR3_A[12]
VDD_4 A12/BC
K8 T3 DDR3_A[13]
VDD_5 A13
N1
VDD_6
N9 M7
VDD_7 A15
R1
VDD_8
R9 M2
VDD_9 BA0 DDR3_BA0
N8
BA1 DDR3_BA1
M3
DDR3_BA2
BA2
A1
VDDQ_1
A8 J7
VDDQ_2 CK
C1 K7
VDDQ_3 CK
C9 K9
VDDQ_4 CKE
D2
VDDQ_5
E9 L2
VDDQ_6 CS
F1 K1
DDR3_ODT
VDDQ_7 ODT
H2 J3
VDDQ_8 RAS DDR3_RASB
H9 K3
VDDQ_9 CAS DDR3_CASB
L3
DDR3_WEB
WE
J1
NC_1
J9 T2
NC_2 RESET
L1
NC_3
L9
NC_4
T7 F3
NC_6 DQSL DDR3_DQSL
G3
DDR3_DQSLB
DQSL
A9 C7
VSS_1 DQSU DDR3_DQSU
B3 B7
DDR3_DQSUB
VSS_2 DQSU
E1
VSS_3
G8 E7
VSS_4 DML DDR3_DML
J2 D3
VSS_5 DMU DDR3_DMU
J8
VSS_6
M1 E3 DDR3_DQL[0]
VSS_7 DQL0
M9 F7 DDR3_DQL[1]
VSS_8 DQL1
P1 F2 DDR3_DQL[2]
VSS_9 DQL2
P9 F8 DDR3_DQL[3]
VSS_10 DQL3
T1 H3 DDR3_DQL[4]
VSS_11 DQL4
T9 H8 DDR3_DQL[5]
VSS_12 DQL5
G2 DDR3_DQL[6]
DQL6
H7 DDR3_DQL[7]
DQL7
B1
VSSQ_1
B9 D7 DDR3_DQU[0]
VSSQ_2 DQU0
D1 C3 DDR3_DQU[1]
VSSQ_3 DQU1
D8 C8 DDR3_DQU[2]
VSSQ_4 DQU2
E2 C2 DDR3_DQU[3]
VSSQ_5 DQU3
E8 A7 DDR3_DQU[4]
VSSQ_6 DQU4
F9 A2 DDR3_DQU[5]
VSSQ_7 DQU5
G1 B8 DDR3_DQU[6]
VSSQ_8 DQU6
G9 A3 DDR3_DQU[7]
VSSQ_9 DQU7
Place near Memory
Place Close to DDR Pin
R5309
56
R5310
56
C5315
0.01uF
25V
IC5301-*1
K4B1G1646G-BCK0
DDR3_A[0-13]
URSA5_DDR3_SS
M8
VREFCA
H1
VREFDQ
L8
ZQ
B2
VDD_1
D9
VDD_2
G7
VDD_3
K2
VDD_4
K8
VDD_5
N1
VDD_6
N9
VDD_7
R1
VDD_8
R9
VDD_9
A1
DDR3_MCK
VDDQ_1
A8
VDDQ_2
C1
VDDQ_3
DDR3_MCKB C9
VDDQ_4
D2
DDR3_CKE
VDDQ_5
E9
VDDQ_6
F1
VDDQ_7
H2
VDDQ_8
+1.5V_FRC_DDR
H9
VDDQ_9
J1
R5308 0
NC_1
J9
DDR3_RESETB NC_2
L1
NC_3
L9
NC_4
T7
NC_6
A9
VSS_1
B3
VSS_2
E1
VSS_3
G8
VSS_4
J2
DDR3_DQL[0-7]
VSS_5
J8
VSS_6
M1
VSS_7
M9
VSS_8
P1
VSS_9
P9
VSS_10
T1
VSS_11
T9
VSS_12
B1
VSSQ_1
B9
VSSQ_2
D1
VSSQ_3
D8
VSSQ_4
E2
VSSQ_5
E8
VSSQ_6
F9
VSSQ_7
G1
VSSQ_8
G9
VSSQ_9
DDR3_DQU[0-7]
DDR3_MCK
Place the serail damping resistors
DDR3_MCKB
in the middle of DRAM pattern
R5311 22
FRC_DMU DDR3_DMU
R5312 22
FRC_DQSL DDR3_DQSL
R5313 22
FRC_DQSLB DDR3_DQSLB
R5314 22
N3 FRC_DQSU DDR3_DQSU
A0
P7
A1
P3 R5315 22
A2 FRC_DQSUB DDR3_DQSUB
N2
A3
P8
R5316 22
A4
P2 FRC_DML DDR3_DML
A5
R8
A6
R2 R5317 22
FRC_ODT DDR3_ODT
A7
T8
A8
R3
R5318 22
A9
L7 FRC_RASB DDR3_RASB
A10/AP
R7
A11
N7 R5319 22
A12/BC FRC_CKE DDR3_CKE
T3
A13
R5320 22
M7 FRC_MCLK DDR3_MCK
NC_5
M2 R5321 22
BA0 FRC_MCLKB DDR3_MCKB
N8
BA1
M3
BA2
R5322 22
FRC_DDR3_RESETB DDR3_RESETB
J7
CK
K7
AR5301
CK
K9
FRC_A[10] DDR3_A[10]
CKE
FRC_BA1 DDR3_BA1
L2
FRC_A[12] DDR3_A[12]
CS
K1
FRC_A[4] DDR3_A[4]
ODT
J3
22
RAS
K3
CAS
L3
WE
AR5302
FRC_A[6] DDR3_A[6]
T2
RESET
FRC_A[8] DDR3_A[8]
FRC_A[1] DDR3_A[1]
FRC_A[11] DDR3_A[11]
F3
DQSL
22
G3
DQSL
C7
AR5303
DQSU
B7
DDR3_A[0]
FRC_A[0]
DQSU
FRC_A[2] DDR3_A[2]
E7
FRC_A[13] DDR3_A[13]
DML
D3
FRC_A[9] DDR3_A[9]
DMU
22
E3
DQL0
F7
DQL1
AR5304
F2
DQL2
F8
DQL3
FRC_A[7] DDR3_A[7]
H3
DQL4
FRC_A[5] DDR3_A[5]
H8
DQL5
FRC_A[3] DDR3_A[3]
G2
DQL6
22
H7
DQL7
D7
AR5305
DQU0
C3
FRC_BA2 DDR3_BA2
DQU1
C8
FRC_BA0 DDR3_BA0
DQU2
C2
FRC_WEB DDR3_WEB
DQU3
A7
FRC_CASB DDR3_CASB
DQU4
A2
22
DQU5
B8
DQU6
A3
DQU7
MStar URSA5
DDR3 4Mbit
AR5306
FRC_DQL[4] DDR3_DQL[4]
FRC_DQL[6] DDR3_DQL[6]
FRC_DQL[2] DDR3_DQL[2]
FRC_DQL[0] DDR3_DQL[0]
22
AR5307
FRC_DQU[5] DDR3_DQU[5]
FRC_DQU[3] DDR3_DQU[3]
FRC_DQU[7] DDR3_DQU[7]
FRC_DQU[1] DDR3_DQU[1]
22
AR5308
FRC_DQU[4] DDR3_DQU[4]
FRC_DQU[6] DDR3_DQU[6]
FRC_DQU[2] DDR3_DQU[2]
FRC_DQU[0] DDR3_DQU[0]
22
AR5309
FRC_DQL[3] DDR3_DQL[3]
FRC_DQL[1] DDR3_DQL[1]
FRC_DQL[5] DDR3_DQL[5]
FRC_DQL[7] DDR3_DQL[7]
22
2010. 08.18
53 55