Epson RX-8564LC Applications Manual page 25

RX 8564 LC
6) TIE bit ( Timer Interrupt Enable )
This bit is used to control output of interrupt signals from the /INT pin when a fixed-cycle timer interrupt
event has occurred.
When a "1" is written to this bit, occurrence of an interrupt event causes a low-level interrupt signal to be
output from /INT pin.
When a "0" is written to this bit, output from the /INT pin is prohibited (disabled).
TIE
Write / Read
13.2.3. Fixed-cycle timer interrupt interval (example)
The combination of the source clock settings (settings in TD1 and TD0) and fixed-cycle timer countdown
setting (Reg C setting) sets the fixed-cycle timer interrupt interval, as shown in the following examples.
Timer Counter
setting
0
(00h)
1
(01h)
2 (02h)
3 (03h)
255
(FFh)
Fixed-cycle timer interrupt time error and fixed-cycle timer interrupt interval time
A fixed-cycle timer interrupt time error is an error in the selected source clock's
Accordingly, the fixed-cycle timer interrupt's interval (one cycle) falls within the following range in
relation to the set time.
Fixed-cycle timer interrupt's interval
(Fixed-cycle timer interrupt's set time( )
The time actually set to the timer is adjusted by adding the time described above to the
communication time for the serial data transfer clock used for the setting.
Data
1) When a fixed-cycle timer interrupt event occurs, an interrupt signal is not
generated or is canceled (/INT status remains Hi-Z).
0
2) When a fixed-cycle timer interrupt event occurs, the interrupt signal is
canceled (/INT status changes from low to Hi-Z).
When a fixed-cycle timer interrupt event occurs, an interrupt signal is
generated (/INT status changes from Hi-Z to low).
1
Level interrupt mode (single-shot operation)
If the TIE bit value is changed from "0" to "1" without first canceling the
interrupt event, the /INT pin immediately goes to low level.
4096 Hz
TD1,0 = 0,0
244.14 s
488.28 s
732.42 s
62.26 ms
) Fixed-cycle timer interrupt's set time = Source clock setting
Description
Source clock
64 Hz
setting is updated)
TD1,0 = 0,1
15.625 ms
31.250 ms
46.875 ms
3.984 s
source clock interval) to (fixed-cycle timer interrupt set time)
Page 22
1 Hz 1/60 Hz
(When seconds (When minutes
setting is updated)
TD1,0 = 1,0 TD1,0 = 1,1
1 s
2 s
3 s
255 s 255 min
+0
/ interval time.
1
Countdown timer setting for fixed-cycle timer
ETM12E-01
1 min
2 min
3 min