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SCHEMATIC DIAGRAM-2
+3.3D
C29 0.1
1
6
25
VCC VCC
VCC
35
LCAS
NC
11
34
BCAS
NC
15
33
DE
NC
16
18
RAS
NC
36
17
W
NC
40
D(31)
15
49
D(30)
14
48
D(29)
13
47
D(28)
12
46
A(13)
D(27)
19
11
11
44
A(12)
D(26)
20
10
10
43
A(11)
D(25)
32
9
9
42
A(10)
D(24)
31
8
8
41
A(9)
D(23)
30
7
AD
DT
7
10
A(8)
D(22)
29
6
6
9
A(7)
D(21)
28
5
5
8
A(6)
D(20)
27
4
4
7
A(5)
D(19)
24
3
3
5
A(4)
D(18)
23
2
2
4
A(3)
D(17)
22
1
1
3
A(2)
D(16)
21
0
0
2
VSS
VSS
VSS
26
45
50
IC10
C3ABMG000166
MSM51V18265DSL
(16M DRAM)
+3.3D
C30 0.1
1
6
25
VCC
VCC
VCC
35
LCAS
NC
11
34
BCAS
NC
15
33
OE
NC
16
18
RAS
NC
36
17
W
NC
40
D(15)
15
49
D(14)
14
48
D(13)
13
47
D(12)
12
46
A(13)
D(11)
19
11
11
44
A(12)
D(10)
20
10
10
43
A(11)
D(9)
32
9
9
42
A(10)
D(8)
31
8
8
41
A(9)
D(7)
30
7
AD
DT
7
10
A(8)
D(6)
29
6
6
9
A(7)
D(5)
28
5
5
8
A(6)
D(4)
27
4
4
7
A(5)
D(3)
24
3
3
5
A(4)
D(2)
23
2
2
4
A(3)
D(1)
22
1
1
3
A(2)
D(0)
21
0
0
2
VSS
VSS
VSS
26
45
50
IC11
C3ABMG000166
MSM51V18265DSL
(16M DRAM)
+3.3D
R43
0
C31 0.1
37
47
VCC
BYTE
12
RESET
NC
13
A(22)
15
RY/BY
ACC
14
A(22)
A(21)
10
20
CE
26
A(21)
A(20)
9
19
DE
28
A(19)
A(20)
16
18
WE
11
A(19)
A(18)
17
17
A(18)
D(31)
A(17)
40
16
15
45
A(16)
A(17)
D(30)
1
15
14
43
A(16)
D(29)
A(15)
2
14
13
41
A(15)
D(28)
A(14)
3
13
12
39
A(13)
A(14)
D(27)
4
12
11
36
A(13)
D(26)
A(12)
5
11
10
34
A(12)
D(25)
A(11)
6
10
9
32
A(10)
A(11)
D(24)
7
9
8
30
A(10)
D(23)
A(9)
8
8
AD
DT
7
44
A(9)
D(22)
A(8)
18
7
6
42
A(7)
A(8)
D(21)
19
6
5
40
A(7)
D(20)
A(6)
20
5
4
38
A(6)
D(19)
A(5)
21
4
3
35
A(4)
A(5)
D(18)
22
3
2
33
A(4)
D(17)
A(3)
23
2
1
31
A(3)
D(16)
A(2)
24
1
0
29
A(1)
A(2)
25
0
VSS
VSS
27
46
IC12
C3FBNG000007
(32M DRAM)
+3.3D
R44
0
C35 0.1
37
47
VCC
BYTE
12
RESET
NC
13
15
RY/BY
ACC
14
A(22)
10
20
CE
26
A(21)
9
19
OE
28
A(20)
16
18
WE
11
A(19)
17
17
A(18)
D(15)
40
16
15
45
A(17)
D(14)
1
15
14
43
A(16)
D(13)
2
14
13
41
A(15)
D(12)
3
13
12
39
A(14)
D(11)
4
12
11
36
A(13)
D(10)
5
11
10
34
A(12)
D(9)
6
10
9
32
A(11)
D(8)
7
9
8
30
A(10)
D(7)
8
8
AD
DT
7
44
A(9)
D(6)
10
7
6
42
A(8)
D(5)
19
6
5
40
A(7)
D(4)
20
5
4
38
A(6)
D(3)
21
4
3
35
A(5)
D(2)
22
3
2
39
A(4)
D(1)
23
2
1
31
A(3)
D(0)
24
1
0
29
A(2)
25
0
VSS
VSS
27
45
IC13
C3FBNG000007
(32M DRAM)
+3.3D
R10
10K
C32 0.1
37
47
VCC
BYTE
12
RESET
RY/BY
15
13
21
ACC
14
10
CE
26
20
D(23)
9
19
DE
28
D(22)
16
18
WE
11
D(21)
17
17
D(31)
D(20)
40
16
15
45
D(30)
D(19)
1
15
14
43
D(29)
D(18)
2
14
13
41
+3.3D
D(28)
D(17)
3
13
12
39
D(27)
D(16)
4
12
11
36
D(26)
5
11
10
34
D(25)
6
10
9
32
D(24)
7
9
8
30
D(23)
8
8
AD
DT
7
44
D(22)
18
7
6
42
D(21)
19
6
5
40
D(20)
20
5
4
38
IC17
D(19)
21
4
3
35
C0JBAE000093
D(18)
22
3
2
33
D(17)
23
2
1
31
D(16)
24
1
0
29
25
0
VSS
VSS
27
46
D(21)
D(20)
IC14
D(19)
C3ZBNG000023
D(18)
(64M FLUSH ROM)
D(17)
D(16)
D(21)
D(20)
D(19)
D(18)
D(17)
D(16)
R46
4.7K
SX-KN2600 MAIN 1/5 SCHEMATIC DIAGRAM
PORT.EX4
+3.3D
C37
0.1
16
VCC
3
D1
Q1
2
4
D2
Q2
5
7
D3
Q3
6
SD.CLK
8
D4
Q4
9
SD.SO
13
D5
Q5
12
SD.PLY
14
D6
Q6
15
SD.MRQ
17
D7
Q7
16
SD.MODE
18
D8
Q8
19
SD.CS
1
RESET
11
CLOCK
GND
IC20
10
C0JBAF000241
(D TYPE FLIPFLOP)
PORT.EX2
+5D
16
VCC
3
D1
Q1
2
4
D2
Q2
5
6
7
DSP.INT3
D3
Q3
11
D4
Q4
10
DSP.CS
13
D5
Q5
12
DSP.RST
14
D6
Q6
15
DSP.INT
1
RESET
9
CLOCK
IC21
GND
IC18
C0JBAF000232
8
(D TYPE FLIPFLOP)
C0JBAE000098
+3.3D
VCC
IC18
GND
C0JBAE000098
(DUAL 2 INPUT OR GATE)
PORT.EX3
+3.3D
C38
0.1
16
VCC
3
D1
Q1
2
DAC.MD
4
D2
Q2
5
DAC.MC
6
D3
Q3
7
DAC.ML
11
D4
Q4
10
REAL.SCL
13
D5
Q5
12
USB.MSL
14
D6
Q6
15
USB.WAITM
1
RESET
9
CLOCK
GND
IC18
8
C0JBAE000098
IC22
C0JBAF000232
R45
3.3K
(D TYPE FLIPFLOP)
R48
2.2K
+3.3D
C36 0.1
IC23
C3EBDC000020
R47
(EEPROM(2K))
4.7K
8
VCC
A0
1
7
WP
A1
2
6
SCL
A2
3
5
SDA
GND
4
REAL.SDA
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