LG 50UH5500 Service Manual page 41

IC100
LGE6551-CA1
G28
M0_DDR_A0 DC1_A0
J31
M0_DDR_A1 DC1_A1
F30
M0_DDR_A2 DC1_A2
E28
M0_DDR_A3 DC1_A3
L28
M0_DDR_A4 DC1_A4
F27
M0_DDR_A5
DC1_A5
K27
M0_DDR_A6 DC1_A6
F28
M0_DDR_A7 DC1_A7
J28
M0_DDR_A8 DC1_A8
G31
M0_DDR_A9 DC1_A9
M27
M0_DDR_A10 DC1_A10
H28
M0_DDR_A11
DC1_A11
L27
M0_DDR_A12
DC1_A12
G30
M0_DDR_A13 DC1_A13
J30
M0_DDR_A14 DC1_A14
L31
DC1_A15
K29
M0_DDR_A4_1 DC1_A4_EXT
G27
M0_DDR_A5_1
DC1_A5_EXT
E27
M0_DDR_BA0 DC1_BA0
K30
M0_DDR_BA1 DC1_BA1
H27
M0_DDR_BA2 DC1_BA2
H30
M0_DDR_CASN
DC1_CASN
M28
M0_DDR_CKE
DC1_CKE
M30
M0_CLK DC1_CLK
L30
M0_CLKN DC1_CLKB
M29
M0_CS0_N
DC1_CSN
AD26
M0_CS1_N DC1_CSN_1
E30
M0_DDR_ODT DC1_ODT
J27
M0_DDR_RASN
DC1_RASN
F29
M0_DDR_RESET_N DC1_RST
H29
M0_DDR_WEN DC1_WEN
U31
M0_DDR_DQ0 DC1_DQ0
P29
M0_DDR_DQ1 DC1_DQ1
U30
M0_DDR_DQ2
DC1_DQ2
R30
M0_DDR_DQ3
DC1_DQ3
T29
M0_DDR_DQ4
DC1_DQ4
P30
M0_DDR_DQ5 DC1_DQ5
T30
M0_DDR_DQ6 DC1_DQ6
R31
M0_DDR_DQ7 DC1_DQ7
N28
M0_DDR_DQ8 DC1_DQ8
U28
M0_DDR_DQ9
DC1_DQ9
N27
M0_DDR_DQ10
DC1_DQ10
U27
M0_DDR_DQ11 DC1_DQ11
P27
M0_DDR_DQ12 DC1_DQ12
T27
M0_DDR_DQ13 DC1_DQ13
P28
M0_DDR_DQ14 DC1_DQ14
T28
M0_DDR_DQ15
DC1_DQ15
AC31
M0_DDR_DQ16
DC1_DQ16
Y29
M0_DDR_DQ17
DC1_DQ17
AC30
M0_DDR_DQ18 DC1_DQ18
AA30
M0_DDR_DQ19 DC1_DQ19
AB29
M0_DDR_DQ20 DC1_DQ20
Y30
M0_DDR_DQ21 DC1_DQ21
AB30
M0_DDR_DQ22
DC1_DQ22
AA31
M0_DDR_DQ23
DC1_DQ23
W28
M0_DDR_DQ24 DC1_DQ24
AC28
M0_DDR_DQ25 DC1_DQ25
W27
M0_DDR_DQ26 DC1_DQ26
AC27
M0_DDR_DQ27 DC1_DQ27
Y27
M0_DDR_DQ28
DC1_DQ28
AB27
M0_DDR_DQ29
DC1_DQ29
Y28
M0_DDR_DQ30
DC1_DQ30
AB28
M0_DDR_DQ31 DC1_DQ31
V30
M0_DDR_DQS0 DC1_DQS0
V29
M0_DDR_DQS_N0 DC1_DQS0B
R27
M0_DDR_DQS1
DC1_DQS1
R28
M0_DDR_DQS_N1 DC1_DQS1B
AD30
M0_DDR_DQS2 DC1_DQS2
AD29
M0_DDR_DQS_N2 DC1_DQS2B
AA27
M0_DDR_DQS3 DC1_DQS3
AA28
M0_DDR_DQS_N3 DC1_DQS3B
N30
M0_DDR_DM0 DC1_DM0
U26
M0_DDR_DM1 DC1_DM1
W30
M0_DDR_DM2 DC1_DM2
AD27
M0_DDR_DM3
DC1_DM3
VREF_M0
1%
R400 D30
240
DDR1_ZQ
D31
DC1_VREF
A18
DDR_1V5_1
A19
DDR_1V5_2 DDR2_ZQ
B18
DDR_1V5_3 DC2_VREF
B19
DDR_1V5_4
C18
DDR_1V5_5
C19
DDR_1V5_6
D18
DDR_1V5_7
D19
+1.5V_DDR DDR_1V5_8
N19
DDR_1V5_9
N20
DDR_1V5_10
N21
DDR_1V5_11
N22
DDR_1V5_12
N23
DDR_1V5_13
N24
DDR_1V5_14
P24
DDR_1V5_15
R24
DDR_1V5_16
T24
DDR_1V5_17
U24
DDR_1V5_18
V24
DDR_1V5_19
W24
DDR_1V5_20
Y24
DDR_1V5_21
+1.5V_DDR_INSTANTBOOT
OPT
R422
R423
OPT
M0_CS0_N
M0_CS1_N
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
Copyright 2016 LG Electronics Inc. All rights reserved.
Only for training and service purposes
M0_DDR_CKE
+1.5V_DDR
M0_DDR_VREFCA
C400
0.1uF
16V
+1.5V_DDR
M0_DDR_VREFDQ
C401
0.1uF
16V
R416
0
M0_CLK
0 R417
M0_CLKN
1% VREF_M1
D28 240 R401
D27
+1.5V_DDR
C424 C425 C426 C427 C428 C429
+1.5V_DDR
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
16V 16V 16V 16V 16V 16V
0
0
Place Near SoC
M0_CS0_N
M0_CS1_N
+1.5V_DDR +1.5V_DDR
VREF_M0 VREF_M1
R426
1K
M0_DDR_A0
+1.5V_DDR
M0_DDR_A1
M0_DDR_A2
M0_DDR_A3
M0_DDR_A4
M0_DDR_A5
M0_DDR_A6
M0_DDR_A7
C404 C405 C407
C443 C441
0.1uF 0.1uF 0.1uF M0_DDR_A8
10uF 10uF
16V 16V 16V
M0_DDR_A9
10V 10V
M0_DDR_A10
M0_DDR_A11
M0_DDR_A12
M0_DDR_A13
Place M0 POWER PLANE
M0_DDR_A14
+1.5V_DDR
+1.5V_DDR
M0_DDR_BA0
M0_1_DDR_VREFCA
M0_DDR_BA1
M0_DDR_BA2
M0_U_CLK
M0_U_CLKN
C432 C434 C436
C442
C444 0.1uF 0.1uF 0.1uF M0_DDR_CKE
10uF 10uF 16V 16V 16V +1.5V_DDR
C402 10V
10V
M0_CS0_N
0.1uF
16V M0_DDR_ODT
R436
M0_DDR_RASN
1K
M0_DDR_CASN
Place M0 POWER PLANE
M0_DDR_WEN
M0_DDR_RESET_N
M0_DDR_DQS0
M0_DDR_DQS_N0
M0_DDR_DQS1
M0_DDR_DQS_N1
+1.5V_DDR
M0_1_DDR_VREFDQ
M0_DDR_DM0
M0_DDR_DM1
M0_DDR_DQ0
M0_DDR_DQ1
M0_DDR_DQ2
M0_DDR_DQ3
C403 M0_DDR_DQ4
0.1uF
M0_DDR_DQ5
16V
M0_DDR_DQ6
M0_DDR_DQ7
M0_DDR_DQ8
M0_DDR_DQ9
M0_DDR_DQ10
M0_DDR_DQ11
M0_DDR_DQ12
M0_DDR_DQ13
M0_DDR_DQ14
M0_U_CLK
M0_DDR_DQ15
M0_U_CLKN
R420
27
C431
27 R421
0.1uF
16V
DDR_HYNIX
IC401
M0_DDR_VREFCA
H5TQ4G63CFR-TEC
DDR3
4Gbit M0_DDR_VREFDQ
N3 M8
A0 VREFCA
P7 (x16)
A1
P3
A2
N2 H1
A3 VREFDQ
P8
A4 M0_DDR_A4_1
P2 +1.5V_DDR
A5 M0_DDR_A5_1
R439
R8 L8
A6 ZQ
R2 240
A7 1%
T8
A8
R3 B2
A9 VDD_1
L7 D9
A10/AP VDD_2 M0_DDR_A10
R7 G7
A11 VDD_3 M0_DDR_A11
N7 K2
M0_DDR_A12
A12/BC VDD_4
T3 K8
M0_DDR_A13
A13 VDD_5
T7 N1
A14 VDD_6 M0_DDR_A14
M7 N9
NC_5 VDD_7
R1
VDD_8
M2 R9
BA0 VDD_9 M0_DDR_BA0
N8
BA1 M0_DDR_BA1
M3
M0_DDR_BA2
BA2
A1
VDDQ_1
J7 A8
CK VDDQ_2
K7 C1
CK VDDQ_3
K9 C9
CKE VDDQ_4 M0_DDR_CKE
D2
VDDQ_5
L2 E9
CS VDDQ_6
K1 F1
M0_DDR_ODT
ODT VDDQ_7
J3 H2 C412 0.1uF
RAS VDDQ_8 M0_DDR_RASN
K3 H9 0.1uF
C413
CAS VDDQ_9 M0_DDR_CASN
L3
WE M0_DDR_WEN
J1
NC_1
T2 J9
RESET M0_DDR_RESET_N
NC_2
L1
NC_3
L9
NC_4
F3
DQSL M0_DDR_DQS2
G3
DQSL M0_DDR_DQS_N2
C7 A9
DQSU VSS_1 M0_DDR_DQS3
B7 B3
M0_DDR_DQS_N3
DQSU VSS_2
E1
VSS_3
E7 G8
DML VSS_4 M0_DDR_DM2
D3 J2
DMU VSS_5 M0_DDR_DM3
J8
VSS_6
E3 M1
DQL0 VSS_7 M0_DDR_DQ16
F7 M9
M0_DDR_DQ17
DQL1 VSS_8
F2 P1
M0_DDR_DQ18
DQL2 VSS_9
F8 P9
DQL3 VSS_10 M0_DDR_DQ19
H3 T1
DQL4 VSS_11 M0_DDR_DQ20
H8 T9
DQL5 VSS_12 M0_DDR_DQ21
G2
DQL6 M0_DDR_DQ22
H7
DQL7 M0_DDR_DQ23
B1
VSSQ_1
D7 B9
DQU0 VSSQ_2 M0_DDR_DQ24
C3 D1
DQU1 VSSQ_3 M0_DDR_DQ25
C8 D8
DQU2 VSSQ_4 M0_DDR_DQ26
C2 E2
DQU3 VSSQ_5 M0_DDR_DQ27
A7 E8
DQU4 VSSQ_6 M0_DDR_DQ28
A2 F9
M0_DDR_DQ29
DQU5 VSSQ_7
B8 G1
M0_DDR_DQ30
DQU6 VSSQ_8
A3 G9
DQU7 VSSQ_9 M0_DDR_DQ31
DDR_MICRON
IC401-*1
MT41K256M16LY-093:N
N3 A0 VREFCA M8
P7
A1
P3
N2 A2 H1
A3 VREFDQ
P8
P2 A4
A5
R8 L8
A6 ZQ
R2 A7
T8
A8
R3 B2
L7 A9 VDD_1 D9
A10/AP VDD_2
R7 G7
N7 A11 VDD_3 K2
A12/BC VDD_4
T3 K8
A13 VDD_5
N1
M7 VDD_6 N9
NC_5 VDD_7
R1
M2 VDD_8 R9
BA0 VDD_9
N8
BA1
M3 BA2
A1
VDDQ_1
J7 A8
K7 CK VDDQ_2 C1
CK VDDQ_3
K9 C9
CKE VDDQ_4 D2
VDDQ_5
L2 E9
CS VDDQ_6
K1 ODT VDDQ_7 F1
J3 H2
RAS VDDQ_8
K3 H9
L3 CAS VDDQ_9
WE
J1
T2 NC_1 J9
RESET NC_2
L1
NC_3
NC_4 L9
F3 T7
LDQS A14
G3
LDQS
C7 A9
B7 UDQS VSS_1 B3
UDQS VSS_2
E1
VSS_3
E7 G8
D3 LDM VSS_4 J2
UDM VSS_5
J8
E3 VSS_6 M1
DQ0 VSS_7
F7 M9
DQ1 VSS_8
F2 DQ2 VSS_9 P1
F8 P9
DQ3 VSS_10
H3 T1
H8 DQ4 VSS_11 T9
DQ5 VSS_12
G2
H7 DQ6
DQ7
B1
VSSQ_1
D7 DQ8 VSSQ_2 B9
C3 D1
DQ9 VSSQ_3
C8 D8
C2 DQ10 VSSQ_4 E2
DQ11 VSSQ_5
A7 E8
A2 DQ12 VSSQ_6 F9
DQ13 VSSQ_7
B8 G1
DQ14 VSSQ_8
A3 VSSQ_9 G9
DQ15
DDR_HYNIX
IC403 M0_1_DDR_VREFCA
H5TQ4G63CFR-TEC
M0_1_DDR_VREFDQ
DDR3
N3 4Gbit M8
M0_DDR_A0
A0 VREFCA
P7
(x16)
M0_DDR_A1 A1
P3
M0_DDR_A2 A2
N2 H1
M0_DDR_A3 A3 VREFDQ
P8
A4
P2 +1.5V_DDR
A5
R443
R8 L8
M0_DDR_A6
A6 ZQ
R2 240
M0_DDR_A7 A7
T8 1%
M0_DDR_A8 A8
R3 B2
M0_DDR_A9 A9 VDD_1
L7 D9
A10/AP VDD_2
R7 G7
A11 VDD_3
N7 K2
A12/BC VDD_4
T3 K8
A13 VDD_5
T7 N1
A14 VDD_6
M7 N9
NC_5 VDD_7
R1
VDD_8
M2 R9
BA0 VDD_9
N8
BA1
M3
BA2
A1
VDDQ_1
J7 A8
M0_U_CLK CK VDDQ_2
K7 C1
M0_U_CLKN CK VDDQ_3
K9 C9
CKE VDDQ_4
D2
VDDQ_5
L2 E9
M0_CS1_N
CS VDDQ_6
K1 F1
ODT VDDQ_7
J3 H2 C416 0.1uF
RAS VDDQ_8
K3 H9 0.1uF
C417
CAS VDDQ_9
L3
WE
J1
NC_1
T2 J9
RESET
NC_2
L1
NC_3
L9
NC_4
F3
DQSL
G3
DQSL
C7 A9
DQSU VSS_1
B7 B3
DQSU VSS_2
E1
VSS_3
E7 G8
DML VSS_4
D3 J2
DMU VSS_5
J8
VSS_6
E3 M1
DQL0 VSS_7
F7 M9
DQL1 VSS_8
F2 P1
DQL2 VSS_9
F8 P9
DQL3 VSS_10
H3 T1
DQL4 VSS_11
H8 T9
DQL5 VSS_12
G2
DQL6
H7
DQL7
B1
VSSQ_1
D7 B9
DQU0 VSSQ_2
C3 D1
DQU1 VSSQ_3
C8 D8
DQU2 VSSQ_4
C2 E2
DQU3 VSSQ_5
A7 E8
DQU4 VSSQ_6
A2 F9
DQU5 VSSQ_7
B8 G1
DQU6 VSSQ_8
A3 G9
DQU7 VSSQ_9
DDR_MICRON
IC403-*1
MT41K256M16LY-093:N
N3 A0 VREFCA M8
P7
A1
P3
N2 A2 H1
A3 VREFDQ
P8
P2 A4
A5
R8 L8
A6 ZQ
R2 A7
T8
A8
R3 B2
L7 A9 VDD_1 D9
A10/AP VDD_2
R7 G7
N7 A11 VDD_3 K2
A12/BC VDD_4
T3 K8
A13 VDD_5
N1
M7 VDD_6 N9
NC_5 VDD_7
R1
M2 VDD_8 R9
BA0 VDD_9
N8
BA1
M3 BA2
A1
VDDQ_1
J7 A8
K7 CK VDDQ_2 C1
CK VDDQ_3
K9 C9
CKE VDDQ_4 D2
VDDQ_5
L2 E9
CS VDDQ_6
K1 ODT VDDQ_7 F1
J3 H2
RAS VDDQ_8
K3 H9
L3 CAS VDDQ_9
WE
J1
T2 NC_1 J9
RESET NC_2
L1
NC_3
NC_4 L9
F3 T7
LDQS A14
G3
LDQS
C7 A9
B7 UDQS VSS_1 B3
UDQS VSS_2
E1
VSS_3
E7 G8
D3 LDM VSS_4 J2
UDM VSS_5
J8
E3 VSS_6 M1
DQ0 VSS_7
F7 M9
DQ1 VSS_8
F2 DQ2 VSS_9 P1
F8 P9
DQ3 VSS_10
H3 T1
H8 DQ4 VSS_11 T9
DQ5 VSS_12
G2
H7 DQ6
DQ7
B1
VSSQ_1
D7 DQ8 VSSQ_2 B9
C3 D1
DQ9 VSSQ_3
C8 D8
C2 DQ10 VSSQ_4 E2
DQ11 VSSQ_5
A7 E8
A2 DQ12 VSSQ_6 F9
DQ13 VSSQ_7
B8 G1
DQ14 VSSQ_8
A3 VSSQ_9 G9
DQ15
2015-04-27
K2L
K2L DDR 03
LGE Internal Use Only