Panasonic AG-DVC30P Service Manual page 17

SENSOR/PROCESS(CAMERA) BLOCK DIAGRAM
CCD FLEX.CARD
P1
2A 2A SIG_R
4A 4A SIG_G
19B 19B SIG_B
X1000<3>
CLK
OSC
IC1016<3>(H.DRIVER)
P1
H1_R
8B 8B H1_R 7
H1_G
10A 10A H1_G 3
H1_B
H1_B
13B 13B 2
9B 9B H2_R
11A 11A H2_G
14B 14B H2_B
6B 6B RG
IC1015<3>(H.DRIVER)
H2_R
7
H2_G
5
H2_B
2
B CCD
R CCD
LENS UNIT
LIGHT
3CCD METHOD
IC1023<3>(V.DRIVER(B))
G CCD
P1
V1_B
5
16A 16A V1_B
V2_B
17A 17A V2_B 3
V3_B
18A 18A V3_B 17
V4_B
19A 19A V4_B 18
VH
16B 16B CAM15V
PT
11B 11B CAM-7V
15A 15A SUB_B 1
3.1V
CAM-7V
CAM15V
IC1022<3>(V.DRIVER(R,G))
P1
13A 13A SUB_R 1
7A 7A SUB_G
V1_RG
5
1B 1B V1_RG
V2_RG
2B 2B V2_RG 3
V3_RG
3B 3B V3_RG 17
V4_RG
4B 4B V4_RG
18
IC1006 - 8 <3>
IC1002<3> SHP
IC1001<3> 5 GEN
31.5MHz 1 7 1
CLK
DRIVER 3
IC1004,5,25<3>
IC1013,14<3> SHD
GEN
15.75MHz
H1
1
H.PULSE
5
IC1003<3>
DECODER
H2
6
CLK 5 15.75MHz
1
DRIVER
IC1000<3>(CCD DRIVE,PULSE GEN)(PLD)
HGT_N
1 32
3
15.75MHz
6
16
IC1010,11,24<3>
RESET
R
HCLR
PULSE
33
DECODER
HGT
35
CH1
8
CH2
13
16
20
INPUT
2
I/F
XV1_B
7 5
XV2_B
9 6
XV3_B
14 7
XV4_B
12 10
ISUB
10
25
12
11
16
20
2
CH1
8
CH2
13
XV1_RG
1
7
INPUT XV2_RG
9 2
I/F
XV3_RG
14 3
XV4_RG
12 4
ISUB
10
IC3500<5>(CAMERA UCOM)
TG_SDATA
103 M1
C_V_DATA K4
TG_SCLK
104 M5
V_C_DATA K3
TG_CS
100 H2
CAM_SCK R2
CAM_RTN B10
RTN_FLD C12
ANA_LDR
F2
ANA_LDG
E3
E1
ANA_LDB
ADDRESS
DATA
A15-17, B14,15,17
C15-17,19, D16-19
E16-19, F16,19
G17
IC2000<4>(CAMERA DSP)
M3, N1-6
P1-7, R3-5
T3-6
DSP
UCOM
I/F
BLOCK
MEMORY
38,39
133,134
E1-4
139-144
F1-4
G1,2
PLD_R(0-9)
R
109-114
119-122
K1-4
L1-4
M1,2
PLD_G(0-9)
G
123-132
H1-4
J1-4
G3,4
PLD_B(0-9)
B
AFE_B(0-11)
53-62
67,68
AFE_G(0-11)
35,36 39-42
47-52
AFE_R(0-11)
AFE_B(0-11)
69-72
AFE_G(0-11)
73-79
82
AFE_R(0-11)
IC104<2>(CDS/PGA/AD)(R)
SHP
21
TIMING
SHD
22
CONTROL
16 ADCLK
SLOAD
46
SDATA SERIAL
47
48 SCLK I/F
SIG_R
CCDIN
30 CDS PGA A/D
12
IC105<2>(CDS/PGA/AD)(G)
SHP
21
TIMING
SHD
22
CONTROL
ADCLK
16
SLOAD
46
SDATA SERIAL
47
SCLK I/F
48
SIG_G
CCDIN
30 CDS PGA A/D
12
IC106<2>(CDS/PGA/AD)(B)
SHP
21
TIMING
SHD
22
CONTROL
ADCLK
16
SLOAD
46
SERIAL
SDATA
47
SCLK I/F
48
SIG_B
CCDIN
30 CDS PGA A/D
12
INV G15
INH G16
D16, E14-16
F14-16, G14
Y,C
DSC
MATRIX
I/F
H14-16
J14-16
K14,15
MEMORY
P2 P2200
C_V_DATA
58B 58A
V_C_DATA 59B 59A
CAM_SCK 60B 60A
CAM_RTN 56B 56A
RTN_FLD 32B 32A
1
1
1
P2 P2200
INV 51A 51B
INH 42A 42B
P2 P2200
YDATA(0-7)
53A 53B
YSI(0-7)
60A 60B
P2 P2200
CDATA(0-7)
43A 43B
CSI(0-7)
50A 50B