Triggering
To find the nth assertion of a chip select line
To find the nth assertion of a chip select line
Select the timing analyzer Trigger menu.
1
Define the glitch/edge1 term to represent the asserting transition on
2
the chip select line.
You can rename the Edge1 term to make it correspond more closely to the
problem domain, for example, to CHIP_SEL.
Under Timing Sequence Levels, enter the following sequence
3
specification:
TRIGGER on "CHIP_SEL" 10 times
Triggering on the 10th Assertion of a Chip Select Line
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