Maximum Time Deviation Between Internal Clocks; Setting The Maximum Time Deviation - Hitachi 670 Series Application Manual

1MRK505382-UEN Rev. K
IEC07000221 V2 EN-US
Figure 3:
2.3.1

Maximum time deviation between internal clocks

2.3.1.1

Setting the maximum time deviation

Maximum time deviation between internal clocks is set using the MaxtDiffLevel parameter in the
respective (one to five) line differential protection IEDs. The setting is done on the local HMI or via
PCM600 (see Figure 4). Maximum time deviation depends on:
• Jitter and wander in the telecommunication network: typically ±100-200 μs in PDH networks and
±50 μs in SDH networks (< ±100 μs according to telecommunication standards).
• Acceptable small asymmetric delay: typically ±50–100 μs. A constant (fixed) asymmetric delay
in the duplex channels can be adjusted by setting the asymmetric delay on the local HMI or via
the parameter setting tool (PST) which is part of PCM600.
• Buffer memory in the telecommunication network: typically < +100 μs (buffer memories should
be avoided).
• Clock drift during two seconds: < ±100 μs.
IEC10000062 V1 EN-US
Figure 4:
Communication set-up, 670/650 series
Application Guide
Three-end application (protection master/slave)
Setting the MaxtDiffLevel in PCM600
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Telecommunication networks and line differential protection
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Section 2
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