Sony RCP-730 Maintenance Manual page 54

IC
HN58C257T (HITACHI)FLAT PACKAGE
32K(32768×8)-BIT EEPROM
-TOP VIEW-
OE 1
A11 2
A9 3 NC
A8 4
A13 5
WE 6
RES 7
V
DD
8
(+ 5V )
RDY/B 9 GND
USY
A14 10
A12 11
A7 12
A6 13 NC
A5 14
A4 15
A3 16
PIN
CE OE WE
MODE
READ 0 0 1
STANDBY 1 X X
WRITE 0 1 0
DESELECT 0 1 1
WRITE INHIBIT X X 1
WRITE INHIBIT X 0 X
DATA POLLING 0 0 1
PROGRAM RESET X X X
0 ; LOW LEVEL
1 ; HIGH LEVEL
X ; DON'T CARE
HI-Z ; HIGH IMPEDANCE
8
HIGH VOLTAGE
V
DD
24
GENERATOR
GND
7
RES
1
OE
31
CE
CONTROL LOGIC AND TIMING
6
WE
19-14
A0-A5 Y DECODER
ADDRESS
BUFFER
AND
LATCH
X DECODER
13-14
A6-A4
4-6
19 21
A0 I/O0
32 A10
18 22
A1 I/O1
17 23
A2 I/O2
31 CE
16 25
A3 I/O3
15 26
A4 I/O4
30
14 27
A5 I/O5
13 28
A6 I/O6
29 I/O7
12 29
A7 I/O7
4
A8
28 I/O6
3
A9
32
A10
27 I/O5
2
A11
11
A12
26 I/O4
5
A13
10
A14
25 I/O3
1
OE
24
6
WE
23 I/O2
7
RES
22 I/O1
9
RDY/B
USY
21 I/O0
31
CE
20
A0-A14 ; ADDRESS INPUT
19 A0 I/O0-I/O7 ; DATA INPUT/OUTPUT
CE ; CHIP ENABLE INPUT
OE ; OUTPUT ENABLE INPUT
18 A1
RDY/BUSY ; REDY/BUSY INPUT
17 A2 RES ; RESET INPUT
WE ; WRITE ENABLE INPUT
RDY/BUSY RES I/O
HIGH Z 1 D
OUT
HIGH Z X HIGH Z
HIGH Z V 1 D
OL IN
HIGH Z 1 HIGH Z
HIGH Z X -
HIGH Z X -
V 1 DATA OUT
OL
HIGH Z 0 HIGH Z
9
I/O BUFFER
AND
INPUT LATCH
Y GATING
MEMORY
ARRAY
DATA LATCH
KM681000BLT-7LT (SAMSUNG)FLAT PACKAGE
×
C-MOS 1M (131,072 8)-BIT STATIC RAM
- TOP VIEW -
V
DD
1 NC 32
(+5 V)
A16 2 31 A15
A14 3 30 CE2
A12 4 29 WE
A7 5 28 A13
A6 6 27 A8
A5 7 26 A9
A4 8 25 A11
A3 9 24 OE
A2 10 23 A10
A1 11 22 CE1
A0 12 21 I/O8
A0 - A16
I/O1 - I/O8
I/O1 13 20 I/O7
CE1, CE2
WE
I/O2 14 19 I/O6
OE
I/O3 15 18 I/O5
16 GND 17 I/O4
CE1
CE2 OE WE MODE I/O TERMINAL
1
X X X NOT SELECT
X
0 X X NOT SELECT
0 1 1 1 OUTPUT DISABLE
0 1 0 1 READ DATA OUTPUT
0 1 X 0 WRITE DATA INPUT
23
A10
25
A11
26
A9
27
A8
28
BUFFER
A13
31
A15
2
A16
3
A14
4
A12
5
A7
6
A6
7
A5
8
A4
BUFFER
9
A3
10
A2
11
A1
12
A0
24
OE
BUFFER
29
WE
22
CE1
30
CE2
IL11
12
A0
11
A1
10
A2
9
A3
8 13
A4 I/O1
7 14
A5 I/O2
6 15
A6 I/O3
5 17
A7 I/O4
18
27
I/O5
A8
26 19
A9 I/O6
23 20
A10 I/O7
25 21
A11 I/O8
4
A12
28
A13
3
A14
31
A15
2
A16
CE1 CE2 WE OE
22 30 29 24
; ADDRESS INPUT
; DATA OUTPUTS
; CHIP ENABLE INPUTS
; WRITE ENABLE INPUT
; OUTPUT ENABLE INPUT
HI-Z
HI-Z
0 ; LOW LEVEL
HI-Z
1 ; HIGH LEVEL
X ; DON'T CARE
HI-Z ; HIGH IMPEDANCE
ROW DECODER
MEMORY MATRIX
512×2048 BITS
DATA I/O GATE
COLUMN DECODER
DATA I/O BUFFER
13-15 17-21
I/O1-I/O8
RCP-730
RCP-731