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Section
II
Paragraphs 2-103 to
2-
116
2-103.
HOLDOFF. A secondoutput fromthe sample-
rate multivibrator
is
amplified by
Q10
to
drive
the
holdoff one-shot
multivibrator
(Q11-Q12). The holdoff
multivibrator
output
consists
of
a
positive pulse which
normally
begins about
1
microsecond after the
end of
the gating signal
and ends
55
milliseconds after
the
end of
the sample-rate
pulse. A
holdoff
pulse
is
also
generated as a
result of
manual
reset
(-15
volts from
manual
reset line through
CR6 and
Q9
to
Ql1-Q12)
so
that
counting cannot start unti.l after reset switching
transients
have
ended.
2-L04,
CIRCUIT
DETAILS.
Refer to the schematic
diagram, Figure 7-20,
for
circuit
details.
Inhibit
amplifier
Q3
is in
series with the
Q4
collector; inhibi-
tion
of
the sample-rate
multivibrator
occurs
whenQ3
is
cutoff
by
a
positive
inhibit
signal
(whicheffectively
disconnects
theQ4
collector). At
theendof the
multi-
vibrator
cycle,
recovery amplifier
QT
conducts
heavily
to
discharge C4
rapidly
in
preparation
for
the next
cycle. RefertoParagraphs z-Lg thru2-22 for
a
basic
one -
shot
multivibrator
discussion.
2-105.
OSCILLATOR AND
OVEN A24
A25
A26
2-106.
GENERAL. Crystal
oven
assemblyA24,
oven
control assembly A25,
and
the
first
portion of oscil-
lator
assembly
A26
provide
an
extremely stable
1
MHz
signal.
The
secondportion
of 4.26
amplifies
and
shapes
either the internally
generated
tMHz, an
externally
supplied
1MHz,
or, for
scaler
operation, the
output
of the decimalcounterAlT or A16. Refer tothe sche-
matic diagram,
Figure
7-21, during
the following
explanation.
2-t07.
CRYSTAL
OVEN
ASSEMBLY AZ4.
The
crys-
tal
oven assembly
is
a
thermally insulated
chamber
which contains
a
heating element,
a
temperature
sensing
circuit,
and
a
1
MHz
piezo-electric crystal.
2-108.
O\mN CONTROL ASSEMBLY
A25.
The
oven
control assembly includes
oscillator
A2SQl
which
pro-
duces
a
3
kHz
output whose
amplitude
is
controlled by
the
temperature-sensing element
in the oven.
The
oscillator
output
is
amplified by A25q2,
detected
to
produce
a
DC
level
whose
amplitude
is
inversely pro-
portional to
oven
temperature.
The DC
level
is
amp-
Iified
and applied to the heating element in the
oven.
The oven control assembly contains
its
own power
supply which operates continuously whenever power
is
connected
to the counter.
2-109.
OSCILLATOR ASSEMBLY ,4,26. The
oscilla-
tor
assembly includes
the
Q1
oscillator cireuit
which
is
corurectedtothe
l
MHz
crystal
inA24.
The
1 MHz
oscillator
output
is
amplified by A26Q2, A26Q3,
and
A26Q4.
A portion of the
A26Q4
output
is
detected
and
applied
to
A26Q1
as AGC
so
that power dissipation in
the crystal
can
be held
at a constant low
value.
An-
other portion of the
A26Q4 output
is
supplied
to
the
rear
panel MODE
switch where
it
usually
is
switched
through
to amplifier
A26Q5
and
trigger
A26Q6-A26Q?.
Outputs
of
1
MHz are taken
from
both
A26Qb
and
A26Q6-
A26Q7.
2-22
Model 5245L
2-110.
CIRCUIT
DETAILS.
Refer to the schematic
diagram, Figure 7-2L,
for circuit details.
The
oscil-
lator
A25Q1
is
controlled by the Wien bridge in
A24.
Positive
feedback
from
the
A25Q2
emitter
through
A24R1-424C6
to
the
A25Q1
emitter maintains oscil-
Iation
at
the
frequency
of maximum feedback, which
occurs at
that
frequency
for
which
the
A24R1-A24Co
phase
shift
equals theA24R2-A23C7 phase
shift(about
3kHz). Degenerative
feedback
is
provided
from
the
425Q2
emitter
and
the
A24RT1-A24R3-A24R4
divider
to the
A25Q1
base; an increase in
oven
temperature
lowers the resistance of RT1, thus increasing
degen-
erative
feedback
and
lowering oscillator output;
like-
wise, a
temperature decrease results
in
increased
degenerative
feedback
to
produce increased
oscillator
output. The
detector
is
a
voltage doubler
circuit;
425C2 charges
fully
through
the negative half cycle,
and then discharges through A25CR2
in
series with
the driving
source during
the
positive
half
cycle.
Capacitor
A25C4
between
the collector
and
base
of
A25Q4
dampens
sudden
DC
voltage swings
and
filters
any AC
component
from the
detected
signal.
The
A26Q1
oscillator is
a
modified Pierce oscillator;
its
base
is
maintained
at a
DC level from the
A26R1=
A26R2
junction;
AGC
current
is
supplied
to
its
emit-
ter from
the
A26CR1-A26CR2
detector
(voltage
doubler) which
is
referenced
to the
A26R1-A26R2
junction. Limiter
A26CR5
holds signal extremities
to within about 0.6 volt of ground potential
(see
Para-
graph
2-8).
Operation of the
trigger circuit
(A26Q6-
A26Q?)
is
discussed
in
detail
in
Paragraphs
2-18.
z.LLT,
MULTIPLIER ASSEMBLY
A2?.
2-L12.
The
1
to
10
MHz
multiplier
assembly consists
of X2 multiplier
Q1, X5
multiplier
Q2 and
amplifier
Q3.
Circuit
details are
shown
in the schematic dia-
gram,
Figure 7-22.
Divider
R4-R5 and emitter
resistor
R6
provide optimum
DC
bias
toQl for efflc-
ient frequency doubling; likewise, divider RB-R9
and
emitter resistor
R10
provide optimum
DC
bias to
Q2
for
efficient fifth-harmonic generation. The inter-
stage coupling
transformers
(L1
-L2, L3-L4,
and
L5-
L6)
include capacitive dividers in
their
secondary
circuits
(CB-C9, C13-C14,
and
Cl9-C20) for inter-
stage impedance matching.
2-113.
5-MHz DECADE
DMDER
ASSEMBLY
A28.
2-LL4.
The
5
MHz decade
divider
assembly reduces
the
frequency of
its
input by
a
factor
of
ten (normally
l
MHzto 100kHz).
Basic
operation
is
identical to that
described
for
the
5
MHz
decimal counter (Paragraphs
2-76
through
2-?9),
except
that there
is
no
displayed
count. Refer to the schematic diagram, Figure
7-23,
for circuit
details.
2-IL5.
LOW.FREQUN
NCY DECADE DIVIDER
A
2-116.
A
block diagram
of a
typical
decade
divider
is
shown
in
Figure
2-L48. A
decade
divider is
an
arrangement
of four
cascaded
binaries (flip-flop)
so
that for
every ten input pulses there
is
one
output
02349-1
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