Read-Only Memory (Rom); Random Access Memory (Ram); Dma; Sdlc And Bisync Data Communication - HP 3000 Series Installation And Service Manual

Principles of Q?eration
requires. the use of logic buffers that convert CMOS/SOS levels to
the more conventional T'I1L signal levels. The !NP Microprocessor
instruct ion set has been optimized for efficient operations per-
fcrmed directly on the I/O registers.
The· INF Microprocessor is designed to facilitate functions such
as logical decision making, indexed branches, and external event
synchronization. These capabilities allow the !NP Microprocessor
to efficiently perfcrrn the functions required of an intelligent
network processor.
4-3. Read-Only Memory (ROM)
The !NP has a
2K
word, hjgh-speed CMOS/SOS ROM. The
ROM
contains
power-on and reset programs, functional diagncstics, loader/
dumper routines, and RAM fault location code.
4-4. Random Access Memory (RAM)
The !NP has
16K
words of dynamic
RAM
that store the· protocol
driver in use (such as BISYNC point-to-point), the INP's control
program, the
HP 3000
interface driver, and data buffers for the
communication channel.
Several circuits are required to support and insure the reliable
operation of the.· RAM. A refresh circuit is provided to refresh
(or renew) the contents of the dynamic RAM at regular intervals.
An LSI chip also aids in performing this function. A parity
circuit calculates a parity bit on each byte written to
RAM
and
verifies the bit or: each read from RAM. Memory-protect circuitry
and separate power supply lines are provided for the
RAM, RAM
refresh circuitry, and other associated support circuitry to
assure that no data will be lost in the event of a power failure
or "brcwnout".
4-5. Direct Memory Access (OMA)
The !NP uses an LSI OMA-controller chip to provide three high-
speed channels between data buffers in RAM and the
HP 300C
Inter face, as well as between RAM and data comm LSI de vices. Th
E'
function of the DMA logic is to move bytes betweo: external
de vices and RAM in such a way that they will be transparent to
the
H\J.t'
Mi
crop roce:::. sor sof tw CJ.re. This ability to transfer data
concurrently with instruction execution enables the !NP to
actieve high thrcughput rates.
4-6. SDLC and BISYNC Data Communication
The INF uses LSI datacomm devices that are programmed by the !NP
Microproce·ssor tc operate with BISYNC and SDLC protocols. When
transmitting, these devices receive data and control bytes in
4-3