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PLL Filters
(Main VCO Loop)
Pin 19
Lock Detector/Filter
(Acquisition Circuit)
Pin 18
AFT Output
Pin 11
In order to make the above drawing easier to comprehend, the vertical voltage axis was drawn to scale but the horizontal time axis was not. The typical slewing
time for each output with the component values shown in the application circuit is as follows:
PLL Filter (Main VCO Loop) Pin 19 – 3.5 ms total sweep time when discharging down from 4.2 V to 2.0 V and charging back up to 4.2 V.
Lock Detector/Filter (Acquisition Circuit) Pin 18 – 4.0 ms when slewing up from 0.8 V to 4.3 V.
AFT Output Pin 11 – 12 ms when slewing from 4.5 V or 0.5 V to the final static condition of 2.5 V.
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Figure 25. Acquisition Circuit Timing
4.2 V
3.2 V
VCO Sweep
Initiated
2.0 V
Signal
No
Signal
VCO Offset
Application
4.3 V
Start
3.7 V
Completed
3.0 V
2.7 V
Signal
Detection
1.3 V
0.8 V
Phase
Detector
Active
4.5 V
2.5 V
0.5 V
AFT
Static
MC44302A
PLL Lock
f IF High
VCO Offset
Removal
Completed
Start
Phase
Detector
Inhibited
Pin 12 = Gnd
Pin 12 = Open
Pin 12 = V CC
AFT Clamped
Signal
VCO Sweep
Inhibited
Phase
Detector
Active
AFT Correcting
MOTOROLA ANALOG IC DEVICE DATA
f IF Nominal
Final Static
Condition
AFT Static
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