HP 8340B Operating Instructions Manual page 116

Another type of leveling error arises from long pulse periods (low repetition rates), or more precisely,
long off times between pulses. The problem lies in the error detection and modulator drive circuits
shown in Figure 3-35. On the left is the comparison point, where the ALC input is compared to the
detector output. For this discussion assume the two resistors are equal in value, so if the ALC and
detector voltages are equal in magnitude but opposite in polarity, the error signal will be zero. The
error is fed to an integrator through the integrate/hold switch. This switch is closed continuously
during CW operation. Any error signal causes the integrator output to change at a controlled rate
(determined by capacitor C), changing the RF output via the linear modulator. The integrator output
continues to change until its input is zero, which means the detector voltage is balancing the ALC
input voltage. The time required to cancel an error is about 70 jisec (4 p.sec with AM on or when
sweeping fast, under which conditions a smaller value of C is switched into the circuit).
DETECTOR OUTPUT
+ 1.0V
HLC INPUT
-1.0V
INTEGRATOR
ERROR
VOLTRGE
0.0V
-0^0-
INTEGRATE/
HOLD
SWITCH
HP
r
TO LINEAR
MODULATOR
-►
Figure 3-35. Error Detection and Modulator Drive
Consider now pulse operation with a period of 1 msec. The detector S/H measures a pulse and holds
its value until the next pulse. Assuming an error is present, the integrator responds to that error,
reaching the proper modulator drive in about 40 jisec. Since the detector S/H is still holding the error
from the last pulse, the integrator keeps changing until the next pulse, overshooting its mark and
causing instability. For this reason the integrate/hold switch is only closed during a pulse. During the
period beween pulses, the switch is opened, thus the integrator input is zero so the modulator drive
doesn't change. This assures that the amplitude at the beginning of the next pulse is the same as at
the end of the previous pulse. Corrections take place only during the pulses, until equilibrium is
reached.
Since this may cause very long response times for narrow pulses, the integrate/hold switch is held
closed a minimum of 10 p.s per pulse, for pulses narrower than that. This is not long enough to cause
overcorrections but speeds response time for 100 ns pulses by a factor of 100.
During the period between pulses, the integrate/hold circuit is expected to hold the modulator drive
constant. Because of leakage currents, the output will in fact drift, causing the pulse amplitude to be in
error. This error will grow with off time and also temperature, as leakage is strongly temperature
dependent. The circuit is designed worst case for <0.1 dB droop in 10 msec at an ambient tem¬
perature of 55°C. At 25°C, a typical unit drifts about 1 dB per minute. The drift may be in either
direction.
HP 8340B/41B
Operating Information
3-113