Advertisement
ICF-SW1
AN-101
2-1-2.
2)
10801 (uPD1715G-545)
Pin Functions
DESCRIPTION
ON
THE
TERMINALS
1)
Terminal Arrangement
@7) CE
QE) E02
@5) EO |
@4) Vss |
@3) VCO _L
@2) VCO H
QI) M
Voo
@ CGP/PD3
8 VDP/PG 2
Vss 2
(© car |
(15) CAP 2
(14) Vss 3
ODO
ODE SHON
SCprorwnrtmn-
MN
—
aaanannaanannanktstzs
O'S -S°9'9 3 3.553 S98-8:8
PIN No.
SYMBOL
NAMING
DESCRIPTION
1
LCD9
LCD
Transmit the segment-output
signals to the LCD panel. When matrixes are configured to-
P..
|
SEGMENT
gether with the COM1
thru COM3, a display of 48 dots can be made.
These output signals
10
LCD1
SIGNALS
are output when the LCDD commands are made. The LCD-driving voltages are of 3.1V typi-
cal, 1/2 bias and 1/3 duty when the frame frequency is 100 Hz.
These LCD11
through LCD16
can also be used at the same as the key source signals for the
key matrix. These signal are output on time-division bases, and they are output as the key-
source signals at the repetition rate of 6.7 msec.
Whether the key-source signal are to be output while having displays on the panel is depend-
ent upon and selectable by the programs used.
These terminals become automatically in the '"'L" (low) state, i.e., non-display mode, at the
power-on reset (VDD changes from low to high state) and at the stoppage moment
of the
clock. The display mode does not change at the reset moment
in which CE changes from
low to high state.
11
COM3
LCD
Transmit common signals to the LCD panel. When the matrixes are configured together with
|
|
COMMON
the LCD1 through LCD16, a display of 48 dots can be made.
13
COM1
SIGNAL
Three distinctive signals of VSS3, VSS2 and VDD are output through these terminals at the
repetition rate of 50 Hz.
These terminals become
automatically in the '"'L" (low) state, i.e., non-display mode, at the
power-on reset (VDD changes from low to high state) and at the stoppage moment of the
clock.
14
VSS3
CAPACITOR
Capacitor-connection
terminals to make a pro-
15
CAP?
CONNECTION | per voltage doubler to build the 3.1V typical
TERMINAL
LCD-4driving voltage VDD.
16
CAP1
FOR
Normal circuit configuration is as follows.
17
VSS2
DOUBLER
18
PG2
VARIABLE;
| Outputs the variable-duty or the one-bit (PG2) signal.
(VDP)
DUTY
Not used.
PORT
fs
19
PD3
CLOCK
Outputs the clock-generator or the one-bit (PD3) signal.
(CGP)
GENERATOR
The selection of either of them is programmable. When used as the CGP, this terminal can
MUTE
PORT
transmit the pulse chain of 1 kHz of 46.6% duty or 3 kHz of 60% duty.
(MUTE
Outputs
signal to cut noise between
frequency
change due to key input and PLL lock,
SIGNAL)
Low level output actuates mute.
enna
essa Se
20
VDD
INPUT
Receives the power-supply voltage for this device. In operation, a voltage of 2.0 to 3.5 VDC
OF
POWER
is applied to this terminal. The input voltage can be lowered down to 1.5 VDC when any of
SUPPLY
the internal data in the RAM, i.e., when the CKSTP command
is under execution, is to be
VOLTAGE
holded.
The power-on reset circuit of device starts to operate at the instance this terminal receives a
voltage of 0 (zero) to 1.7 VDC, and the program starts from the location 0 (zero).
Note: This pin and pin 46 are connected
internally. So, it is not necessary to apply the
power-supply voltage to both of them. The ceramic-packaged device, however, has a
not-to-be connected pin 46, i.e., N.C. terminal.
—9—
Advertisement
