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Instruction Cycles
The following examples illustrate typical situations and the flow of information by large lines
with arrowheads indicating the direction of flow.
The steps are numbered to tie in with the
corresponding explanation.
These examples are for one 6.94 microsecond word time each.
The function the instruction cycle (Figure 7) performs is the initial decoding of the instruction
and the generation of the desired memory address and its transfer to the L-register. This
prepares the DATANET-30 for the execution cycles to follow:
1.
At the very start of the instruction cycle (actually slightly before) the address of the
next instruction is transferred from P to L. After this takes place, P is incremented
by plus 1.
2.
The L-register is transferred to the memory address lines.
3.
When the instruction is read out, it is transferred from M to N where, in this example,
a non general instruction is decoded.
4.
After the instruction is decoded the address modification mode is decoded and the
correct section of the arithmetic unit enabled (see "Addressing Memory").
5.
The desired memory address is transferred from the arithmetic unit to Z.
6.
The address is then sent to L to prepare for addressing memory on the next cycle.
7.
Simultaneously with steps 3, 4, and 5, the contents of M are being regenerated by the
memory drivers.
AID RESS
REGISTER
15
I
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0 - -
-
_
_l
B
REGISTER
18
Q
COUNTER
14
p
COUNTER
15
1
2
MEMORY
j1
UNIT
I
N
REGISTl!R
HEMlRY
ADDRESS
-1
LINES
15
I
I
I
MAGNETIC
CORE
MEK>RY
MEMORY
I
DRIVERS
18
I
18
I
I
7 I
---'
Figure 7. Detailed Block Diagram DATANET-30
Instruction Cycle
BRANCH
FLIP-FLOPS
PLUS
ZEIO
18
5
ARITHM!TIC
UNIT
4
Y
REGISTl!R
18
[Q)Li\u&~~uCJ ~@------------
I-17
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